JPH07115107A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07115107A JPH07115107A JP5257276A JP25727693A JPH07115107A JP H07115107 A JPH07115107 A JP H07115107A JP 5257276 A JP5257276 A JP 5257276A JP 25727693 A JP25727693 A JP 25727693A JP H07115107 A JPH07115107 A JP H07115107A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- pads
- semiconductor device
- potential power
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に係り、詳し
くは多数の電極パッドが形成され薄型パッケージに封止
される半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a large number of electrode pads are formed and sealed in a thin package.
【０００２】近年、半導体装置においては、集積化が進
められている。一方で実装密度を高めるために、半導体
チップを封止するパッケージの小型化及び薄型化が要求
されている。パッケージサイズは外部ピン数によって決
定される。特に、多ビット入出力構成の半導体メモリに
おいては、その入出力ピンの増加に比例して電源ピンが
増加する。そのため、パッケージサイズの小型化のため
に外部ピン数の低減が要求されている。In recent years, semiconductor devices have been increasingly integrated. On the other hand, in order to increase the mounting density, it is required to reduce the size and thickness of the package that seals the semiconductor chip. Package size is determined by the number of external pins. Particularly, in a semiconductor memory having a multi-bit input / output configuration, the number of power supply pins increases in proportion to the increase in the number of input / output pins. Therefore, it is required to reduce the number of external pins in order to reduce the package size.
【０００３】[0003]
【従来の技術】近年、半導体装置、例えば半導体メモリ
においては入出力線の多ビット化が押し進められてい
る。図６には半導体メモリの多ビットの入出力線を説明
する概念図が示されている。各入出力端子ＤＱ１〜ＤＱ
ｎには出力バッファであるＣＭＯＳ構造のインバータ回
路ＩＮＶ１〜ＩＮＶｎがそれぞれ接続されている。イン
バータ回路ＩＮＶ１〜ＩＮＶｎは高電位電源端子ＶＣＣ
と低電位電源端子ＶＳＳとの間に並列に接続され、各イ
ンバータ回路ＩＮＶ１〜ＩＮＶｎは駆動電源を供給され
る。2. Description of the Related Art In recent years, in semiconductor devices such as semiconductor memories, the number of input / output lines has been increased. FIG. 6 is a conceptual diagram illustrating a multi-bit input / output line of a semiconductor memory. Each input / output terminal DQ1 to DQ
Inverters INV1 to INVn having a CMOS structure, which are output buffers, are connected to n. The inverter circuits INV1 to INVn are high potential power supply terminals VCC
And the low-potential power supply terminal VSS are connected in parallel, and each inverter circuit INV1 to INVn is supplied with drive power.
【０００４】多ビット入出力線を有する半導体メモリで
は、その各インバータ回路ＩＮＶ１〜ＩＮＶｎが動作す
る時、各インバータ回路ＩＮＶ１〜ＩＮＶｎには電流Ｉ
１〜Ｉｎが流れる。そのため、高電位電源端子ＶＣＣ及
び低電位電源端子ＶＳＳには各電流Ｉ１〜Ｉｎを加算し
た電流が流れることになり、チップ内の電源線抵抗によ
る過大な電位降下が発生する。その電位降下が半導体メ
モリの動作を保証する電圧範囲を越えると、メモリが正
常に動作しなかったりメモリの内容が消去されてしまう
等の誤動作を起こす恐れがある。In a semiconductor memory having a multi-bit input / output line, when each of the inverter circuits INV1 to INVn operates, a current I is applied to each of the inverter circuits INV1 to INVn.
1-In flows. Therefore, a current obtained by adding the respective currents I1 to In flows through the high potential power supply terminal VCC and the low potential power supply terminal VSS, and an excessive potential drop occurs due to the power supply line resistance in the chip. If the potential drop exceeds the voltage range that guarantees the operation of the semiconductor memory, the memory may not operate normally or the contents of the memory may be erased.
【０００５】このようなメモリの誤動作の発生を抑える
ために、図７に示すように、入出力端子ＤＱ１〜ＤＱｎ
に対して高電位電源端子ＶＣＣ１〜ＶＣＣｎ及び低電位
電源端子ＶＳＳ１〜ＶＳＳｎをそれぞれ設ければよい。
実際には、入出力端子ＤＱ１〜ＤＱｎそれぞれに両電源
端子ＶＣＣ１〜ＶＣＣｎ及びＶＳＳ１〜ＶＳＳｎを設け
ると、その端子だけでチップが大きくなってしまう。そ
のため、複数の入出力端子に対して１対の電源端子を設
けている。この場合の電源端子の配置の一例を図８に示
す。In order to suppress the occurrence of such a memory malfunction, as shown in FIG. 7, input / output terminals DQ1 to DQn are provided.
However, the high-potential power supply terminals VCC1 to VCCn and the low-potential power supply terminals VSS1 to VSSn may be provided, respectively.
Actually, if both power supply terminals VCC1 to VCCn and VSS1 to VSSn are provided to the input / output terminals DQ1 to DQn, respectively, the chip becomes large only by the terminals. Therefore, a pair of power supply terminals is provided for the plurality of input / output terminals. An example of the arrangement of the power supply terminals in this case is shown in FIG.
【０００６】図８には４ビット入出力構成の半導体メモ
リのブロック図が示されている。チップ１の上面中央に
は複数の外部パッド２が１列に配置されている。外部パ
ッド２は高電位電源端子ＶＣＣ１〜ＶＣＣ４、低電位電
源端子ＶＳＳ１〜ＶＳＳ４、メモリ上の位置を指定する
アドレス信号を入力するアドレス端子Ａ１〜Ａ４及び４
ビットの入出力端子ＤＱ１〜ＤＱ４に割当られている。
外部パッド２の両側にはメモリセル３ａ〜３ｄ，ロウデ
コーダ４ａ〜４ｄ，コラムデコーダ５ａ〜５ｄ及び制御
回路６ａ，６ｂが形成されている。FIG. 8 shows a block diagram of a semiconductor memory having a 4-bit input / output configuration. A plurality of external pads 2 are arranged in a line at the center of the upper surface of the chip 1. The external pad 2 has high-potential power supply terminals VCC1 to VCC4, low-potential power supply terminals VSS1 to VSS4, and address terminals A1 to A4 and 4 for inputting an address signal designating a position on the memory.
Bits are assigned to input / output terminals DQ1 to DQ4.
Memory cells 3a to 3d, row decoders 4a to 4d, column decoders 5a to 5d, and control circuits 6a and 6b are formed on both sides of the external pad 2.
【０００７】そして、入出力端子ＤＱ１，ＤＱ４に対し
て高電位電源端子ＶＣＣ１と低電位電源端子ＶＳＳ１と
が設けられ、入出力端子ＤＱ２，ＤＱ３に対して高電位
電源端子ＶＣＣ２と低電位電源端子ＶＳＳ２とが設けら
れている。メモリセル３ａ〜３ｄ、ローデコーダ４ａ〜
４ｄ、コラムデコーダ５ａ〜５ｄ及び制御回路６ａ，６
ｂに対して高電位電源端子ＶＣＣ３と低電位電源端子Ｖ
ＳＳ３とが設けられている。又、アドレス端子Ａ１〜Ａ
４に対して高電位電源端子ＶＣＣ４と低電位電源端子Ｖ
ＳＳ４とが設けられている。A high potential power supply terminal VCC1 and a low potential power supply terminal VSS1 are provided for the input / output terminals DQ1 and DQ4, and a high potential power supply terminal VCC2 and a low potential power supply terminal VSS2 are provided for the input / output terminals DQ2 and DQ3. And are provided. Memory cells 3a to 3d, row decoder 4a to
4d, column decoders 5a to 5d and control circuits 6a, 6
b to high potential power supply terminal VCC3 and low potential power supply terminal V
SS3 and are provided. Also, address terminals A1 to A
4 to high potential power supply terminal VCC4 and low potential power supply terminal V
SS4 and are provided.
【０００８】図１０にはチップ１を封止した半導体メモ
リのパッケージの縦断面図がしめされている。メモリの
大容量化に伴って大きくなったチップサイズのため、こ
のパッケージはＬＯＣ（Lead On Chip）技術を採用し、
ＳＯＪ（Small Outline J-leaded Package）型に形成さ
れている。ＬＯＣ技術はＬＳＩ（Large Scale Integrat
ed circuit）のパッケージング技術の一種であって、チ
ップ１の長手方向の側縁からチップ１の中央にリードフ
レーム７が延びている。そして、リードフレーム７は外
部パッド２とボンディング・ワイヤ８で接続されてい
る。FIG. 10 shows a vertical sectional view of a semiconductor memory package in which the chip 1 is sealed. This package uses LOC (Lead On Chip) technology because the chip size has increased with the increase in memory capacity.
It is formed in the SOJ (Small Outline J-leaded Package) type. LOC technology is LSI (Large Scale Integrat)
ed circuit), which is a type of packaging technology, in which a lead frame 7 extends from the side edge of the chip 1 in the longitudinal direction to the center of the chip 1. The lead frame 7 is connected to the external pad 2 by the bonding wire 8.
【０００９】図９に示すように、リードフレーム７には
リードＬ１〜Ｌ１２が形成されている。リードＬ１及び
リードＬ６は連結部Ｌ２０により一体化されている。リ
ードＬ７及びリードＬ１２は連結部Ｌ２１により一体化
されている。連結部Ｌ２０と高電位電源端子ＶＣＣ１〜
ＶＣＣ４、連結部Ｌ２１と低電位電源端子ＶＳＳ１〜Ｖ
ＳＳ４がボンディング・ワイヤ８でそれぞれ接続されて
いる。そして、リードＬ２，Ｌ３，Ｌ１０，Ｌ１１と入
出力端子ＤＱ１〜ＤＱ４、リードＬ５，Ｌ４，Ｌ９，Ｌ
８とアドレス端子Ａ１〜Ａ４とが連結部Ｌ２０又はＬ２
１をまたぐボンディング・ワイヤ８でそれぞれ接続され
ている。As shown in FIG. 9, leads L1 to L12 are formed on the lead frame 7. The lead L1 and the lead L6 are integrated by a connecting portion L20. The lead L7 and the lead L12 are integrated by a connecting portion L21. The connecting portion L20 and the high potential power supply terminals VCC1 to VCC1
VCC4, connecting portion L21 and low potential power supply terminals VSS1 to V
SS4 are connected by bonding wires 8 respectively. Then, the leads L2, L3, L10, L11 and the input / output terminals DQ1 to DQ4, the leads L5, L4, L9, L
8 and the address terminals A1 to A4 connect to the connecting portion L20 or L2.
They are connected by bonding wires 8 extending over 1 respectively.
【００１０】チップ１とリードフレーム７はエポキシ樹
脂等の材料よりなる封止体１０によりモールドされてい
る。そして、各リードＬ１〜Ｌ１２の外端部は外部ピン
として図示しない基板に搭載し易いようにＪ字状に形成
されている。The chip 1 and the lead frame 7 are molded by a sealing body 10 made of a material such as epoxy resin. The outer ends of the leads L1 to L12 are formed in J-shape so as to be easily mounted on a substrate (not shown) as external pins.
【００１１】[0011]
【発明が解決しようとする課題】ところで、基板からの
高さを低くするためにチップ１を更に薄いＴＳＯＰ（Th
in Small Outline Package）型のパッケージに封止しよ
うとする。このとき、図１１に示すようにボンディング
・ワイヤ８がパッケージから飛び出てしまう可能性があ
り、そのような場合にはチップ１を封止することができ
ない。そこで、チップの外部パッド２とリードとをＴＡ
Ｂ（Tape Automated Bonding）技術を用いて導電性の金
属テープＴで接続する方法が用いられている。このＴＡ
Ｂ技術を用いたＴＳＯＰを図１２に示す。チップの外部
パッド２とリードにはそれぞれ導電性接着剤１１が塗布
され、導電性のテープＴが接着されている。By the way, in order to reduce the height from the substrate, the chip 1 has a thinner TSOP (Th
In Small Outline Package) type package. At this time, as shown in FIG. 11, the bonding wire 8 may pop out of the package, and in such a case, the chip 1 cannot be sealed. Therefore, the external pad 2 of the chip and the lead are connected to TA
A method of connecting with a conductive metal tape T using the B (Tape Automated Bonding) technique is used. This TA
A TSOP using the B technology is shown in FIG. A conductive adhesive 11 is applied to each of the external pad 2 and the lead of the chip, and a conductive tape T is bonded thereto.
【００１２】しかし、テープは打ち抜きによって全ての
テープが一括で形成されるので、平面的な２次元構造し
か許されず、ワイヤのようにリードをまたぐことができ
ない。そのため、チップ１をＴＡＢ技術を用いてＴＳＯ
Ｐ型のパッケージに封止しようとすると、図１３に示す
ようにチップ１上に形成した全ての外部パッド２に対応
してテープ及びリードを設けなくてはならない。その結
果、リードの数が多くなるので、チップを封止するパッ
ケージのパッケージサイズが大きくなってしまい、その
パッケージを基板に実装する際の実装面積が大きくなる
という問題があった。However, since all the tapes are formed at once by punching, only a two-dimensional planar structure is allowed, and the tape cannot straddle the leads like a wire. Therefore, the chip 1 is mounted on the TSO using the TAB technology.
When encapsulating in a P-type package, tapes and leads must be provided corresponding to all the external pads 2 formed on the chip 1 as shown in FIG. As a result, since the number of leads is increased, the package size of the package for encapsulating the chip is increased, and there is a problem that the mounting area for mounting the package on the substrate is increased.
【００１３】一方、パッケージを基板に実装するときの
実装面積を更に小さくするために、ＳＶＰ（Surface Ve
rtical Package）型のパッケージが採用されている。図
１４に示すように、ＳＶＰもＴＳＯＰと同様にＴＡＢ技
術を用いてパッケージが薄くなるように形成されてい
る。On the other hand, in order to further reduce the mounting area when mounting the package on the substrate, SVP (Surface Ve
(rtical Package) type package is adopted. As shown in FIG. 14, the SVP is also formed by using the TAB technique so that the package becomes thin like the TSOP.
【００１４】図１５に示すように、ＳＶＰ型のパッケー
ジは基板に対して垂直に実装するためのパッケージであ
って、外部ピンはパッケージの一辺にのみ設けられてい
る。同様のパッケージとしてＺＩＰ（Zigzag Inline Pa
ckage ）型のパッケージがあるが、ＺＩＰ型と比較する
と、ＳＶＰ型は外部ピンのピッチが狭くパッケージサイ
ズも小さく形成される。ＺＩＰ型はそのパッケージサイ
ズが外部ピンのピン数により決定される。一方、ＳＶＰ
型は内部に格納する半導体チップのチップサイズによ
り、ほぼそのパッケージサイズを決定し、外部ピン数が
増加した場合には外部ピンのピンピッチが小さく設定さ
れる。従って、ＳＶＰ型は外部ピンのピン数が多いほ
ど、そのピンピッチは細かくなる。As shown in FIG. 15, the SVP type package is a package for mounting vertically on a substrate, and external pins are provided only on one side of the package. As a similar package ZIP (Zigzag Inline Pa
ckage) type package, but compared with the ZIP type, the SVP type has a smaller pitch of external pins and a smaller package size. The package size of the ZIP type is determined by the number of external pins. On the other hand, SVP
The mold determines the package size substantially according to the chip size of the semiconductor chip stored inside, and when the number of external pins increases, the pin pitch of the external pins is set small. Therefore, in the SVP type, the larger the number of external pins, the finer the pin pitch.
【００１５】図１４に示すように、ＳＶＰ型ではテープ
ＴはＴＳＯＰ型に封止する場合と同様に打ち抜いて形成
されるので、平面的な２次元構造しか許されない。この
ため、ＴＡＢ技術を用いて封止する場合には、接続する
パッドの数だけ外部ピンが必要となる。その結果、ＳＶ
Ｐ型に多ビット入出力構成のメモリを封止する場合、電
源パッドが増加すると外部ピンも増加し、外部ピンピッ
チが狭くなり、基板への実装が困難になるという問題が
あった。As shown in FIG. 14, in the SVP type, since the tape T is formed by punching as in the case of sealing the TSOP type, only a two-dimensional planar structure is allowed. Therefore, when sealing is performed using the TAB technique, external pins are required for the number of pads to be connected. As a result, SV
When a P-type memory having a multi-bit input / output configuration is sealed, there is a problem that as the number of power supply pads increases, the number of external pins also increases, the external pin pitch becomes narrower, and it becomes difficult to mount on a substrate.
【００１６】本発明は上記問題点を解決するためになさ
れたものであって、その目的は小型かつ薄型のパッケー
ジで外部ピンのピン数の増加を抑えることができる半導
体装置を提供するにある。The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor device capable of suppressing an increase in the number of external pins in a small and thin package.
【００１７】[0017]
【課題を解決するための手段】本発明は上記目的を達成
するため、チップの上面中央に種々の電気信号を扱う複
数のパッドが、一方向に延びるように配置された半導体
チップを樹脂封止体で封止し、前記樹脂封止体の外側に
は信号を伝達するための複数の外部リードを設け、前記
樹脂封止体内において前記複数のパッドと前記複数のリ
ードとを複数の内部リードで接続した半導体装置におい
て、前記複数のパッドのうち、同一の電気信号を扱う複
数のパッドに対応する内部リードを、他の電気信号を扱
うパッドに対応する内部リードを迂回して形成し、その
内部リードを前記同一の電気信号を扱う複数のパッドに
接続した。In order to achieve the above object, the present invention achieves the above object by sealing a semiconductor chip in which a plurality of pads for handling various electric signals are arranged in the center of the upper surface of the chip so as to extend in one direction. A plurality of external leads for transmitting signals are provided outside the resin encapsulation body, and the plurality of pads and the plurality of leads are formed by a plurality of inner leads inside the resin encapsulation body. In the connected semiconductor device, an internal lead corresponding to a plurality of pads handling the same electric signal among the plurality of pads is formed by bypassing an internal lead corresponding to a pad handling another electric signal, and Leads were connected to the pads that handle the same electrical signal.
【００１８】又、請求項２に記載の発明は、前記内部リ
ードは導電性のテープを打ち抜いて形成したことを要旨
とする。又、請求項３に記載の発明は、前記内部リード
は外部リードと一体に形成したことを要旨とする。A second aspect of the invention is summarized in that the inner lead is formed by punching out a conductive tape. A third aspect of the invention is summarized in that the inner lead is formed integrally with the outer lead.
【００１９】又、請求項４に記載の発明は、前記外部リ
ードは、前記複数のパッドが配置された方向と平行に形
成された前記樹脂封止体の辺のうち、一方にのみ形成し
たことを要旨とする。Further, in the invention according to claim 4, the external lead is formed only on one of the sides of the resin encapsulant formed in parallel to the direction in which the pads are arranged. Is the gist.
【００２０】又、請求項５に記載の発明は、前記外部リ
ードは、前記複数のパッドが配置された方向と平行に形
成された前記樹脂封止体の辺の両方に形成したことを要
旨とする。The invention according to claim 5 is characterized in that the external leads are formed on both sides of the resin encapsulant formed parallel to a direction in which the pads are arranged. To do.
【００２１】[0021]
【作用】従って、請求項１に記載の発明によれば、同一
の電気信号を扱う複数のパッドに対応する内部リード
を、他の電気信号を扱うパッドに対応する内部リードを
迂回して形成し、その内部リードを前記同一の電気信号
を扱う複数のパッドに接続したので、外部リードの数を
減少させることができる。その結果、チップを封止する
樹脂封止体の大きさを小さくかつ薄くすることができ
る。Therefore, according to the first aspect of the invention, the internal leads corresponding to a plurality of pads handling the same electric signal are formed bypassing the internal leads corresponding to the pads handling other electric signals. Since the internal leads are connected to the plurality of pads that handle the same electric signal, the number of external leads can be reduced. As a result, the size of the resin sealing body that seals the chip can be made small and thin.
【００２２】又、請求項２に記載の発明によれば、内部
リードが導電性のテープを打ち抜いて形成したので、チ
ップを封止する樹脂封止体の大きさを小さくかつ薄くす
ることができる。According to the second aspect of the invention, since the inner lead is formed by punching out a conductive tape, the size of the resin sealing body for sealing the chip can be made small and thin. .
【００２３】又、請求項３に記載の発明によれば、内部
リードと外部リードとを一体に形成したので、チップを
封止する樹脂封止体の大きさを小さくかつ薄くすること
ができる。According to the third aspect of the invention, since the inner lead and the outer lead are integrally formed, the size of the resin encapsulant for encapsulating the chip can be made small and thin.
【００２４】又、請求項４，５に記載の発明によれば、
外部リードが複数のパッドが配置された方向と平行に形
成された樹脂封止体の一辺又は両辺に形成されたいずれ
にもチップを封止することができる。According to the inventions of claims 4 and 5,
The chip can be sealed either on one side or both sides of the resin sealing body in which the external leads are formed in parallel with the direction in which the plurality of pads are arranged.
【００２５】[0025]
（第一実施例）以下、本発明の半導体装置の第一実施例
について説明する。(First Embodiment) A first embodiment of the semiconductor device of the present invention will be described below.
【００２６】尚、説明の便宜上、図１３と同様の構成に
ついては同一の符号を付してその説明を一部省略する。
図１はＴＡＢ技術を用いてＴＳＯＰ型に封止した半導体
メモリのチップを示す。チップ１上に形成された外部パ
ッド２のうち、両端に形成された高電位電源端子ＶＣＣ
１，ＶＣＣ４、低電位電源端子ＶＳＳ１，ＶＳＳ４と各
入出力端子ＤＱ１〜ＤＱ４及び各アドレス端子Ａ１〜Ａ
４がテープＴ１〜Ｔ１２を介してリードＬ１〜Ｌ１２に
それぞれ接続されている。For convenience of explanation, the same components as those in FIG. 13 are designated by the same reference numerals, and the description thereof will be partially omitted.
FIG. 1 shows a semiconductor memory chip sealed in a TSOP type using the TAB technology. Of the external pads 2 formed on the chip 1, high potential power supply terminals VCC formed at both ends
1, VCC4, low-potential power supply terminals VSS1 and VSS4, input / output terminals DQ1 to DQ4, and address terminals A1 to A
4 are connected to leads L1 to L12 via tapes T1 to T12, respectively.
【００２７】テープＴ１とテープＴ６とが連結部Ｔ２０
で一体化され、テープＴ７とテープＴ１２とが連結部Ｔ
２１で一体化されている。連結部Ｔ２０はテープＴ１と
テープＴ６との間に他のテープが存在する場合、そのテ
ープが接続される外部パッド２とその１つ手前の外部パ
ッド２との間を通過し、その外部パッド２と次の外部パ
ッド２との間を通過して該テープを迂回するように形成
されている。又、連結部Ｔ２１はテープＴ７とテープＴ
１２との間に他のテープが存在する場合、そのテープが
接続される外部パッド２とその１つ手前の外部パッド２
との間を通過し、その外部パッド２と次の外部パッド２
との間を通過して該テープを迂回するように形成されて
いる。The tape T1 and the tape T6 are connected to each other at a connecting portion T20.
And the tape T7 and the tape T12 are connected to each other at the connecting portion T.
21 is integrated. When another tape exists between the tape T1 and the tape T6, the connecting portion T20 passes between the external pad 2 to which the tape is connected and the external pad 2 immediately before the tape, and the external pad 2 It is formed so as to bypass the tape by passing between the tape and the next external pad 2. In addition, the connecting portion T21 includes the tape T7 and the tape T.
When another tape exists between the external pad 2 and the external tape 12, the external pad 2 to which the tape is connected and the external pad 2 immediately before the external pad 2
Between the external pad 2 and the next external pad 2
It is formed so as to pass between the tape and the tape and bypass the tape.
【００２８】即ち、連結部Ｔ２０は外部パッド２の間を
通ってテープＴ２〜テープＴ５を迂回するように形成さ
れている。又、連結部Ｔ２１は外部パッド２の間を通っ
てテープＴ８〜テープＴ１１を迂回するように形成され
ている。That is, the connecting portion T20 is formed so as to pass between the external pads 2 and bypass the tape T2 to the tape T5. The connecting portion T21 is formed so as to pass between the external pads 2 and bypass the tapes T8 to T11.
【００２９】そして、連結部Ｔ２０にはテープＴ２２，
Ｔ２３が突出形成され、そのテープＴ２２，Ｔ２３は高
電位電源端子ＶＣＣ２，ＶＣＣ３に接続されている。即
ち、高電位電源端子ＶＣＣ２，ＶＣＣ３は連結部Ｔ２０
及びテープＴ２２，Ｔ２３を介してテープＴ１，Ｔ６に
接続されている。At the connecting portion T20, a tape T22,
T23 is formed to project, and the tapes T22 and T23 are connected to the high potential power supply terminals VCC2 and VCC3. That is, the high potential power supply terminals VCC2 and VCC3 are connected to the connecting portion T20.
And the tapes T1 and T6 via the tapes T22 and T23.
【００３０】又、連結部Ｔ２１にはテープＴ２４，Ｔ２
５が突出形成され、そのテープＴ２４，Ｔ２５は低電位
電源端子ＶＳＳ２，ＶＳＳ３に接続されている。即ち、
低電位電源端子ＶＳＳ２，ＶＳＳ３は連結部Ｔ２１及び
テープＴ２４，Ｔ２５を介して低電位電源端子ＶＳＳ１
又はＶＳＳ４に接続されたテープＴ７，Ｔ１２に接続さ
れている。Further, the connecting portion T21 has tapes T24 and T2.
5, the tapes T24 and T25 are connected to the low potential power supply terminals VSS2 and VSS3. That is,
The low potential power supply terminals VSS2 and VSS3 are connected to the low potential power supply terminal VSS1 via the connecting portion T21 and the tapes T24 and T25.
Alternatively, it is connected to the tapes T7 and T12 connected to VSS4.
【００３１】そして、各テープＴ１〜Ｔ１２，Ｔ２２〜
Ｔ２５及び連結部Ｔ２０，Ｔ２１は交差することなく、
同一平面で２次元的構造を取ることができる。従って、
高電位電源端子ＶＣＣ２，ＶＣＣ３及び低電位電源端子
ＶＳＳ２，ＶＳＳ３に対応した外部ピンを設ける必要が
なく、外部ピンの増加を抑えることができ、パッケージ
を小さくすることができる。Then, the tapes T1 to T12 and T22 to
T25 and the connecting portions T20 and T21 do not intersect,
It can have a two-dimensional structure on the same plane. Therefore,
It is not necessary to provide external pins corresponding to the high-potential power supply terminals VCC2 and VCC3 and the low-potential power supply terminals VSS2 and VSS3, the increase in external pins can be suppressed, and the package can be made smaller.
【００３２】このように、本実施例では、高電位電源端
子ＶＣＣ１とＶＣＣ４とを接続する連結部Ｔ２０と、低
電位電源端子ＶＳＳ１とＶＳＳ４とを接続する連結部Ｔ
２１とを互いに交わらないように形成するようにした。
更に、連結部Ｔ２０及び連結部Ｔ２１と他のテープＴ２
〜Ｔ５及びＴ７〜Ｔ１１とが交差する位置において、連
結部Ｔ２０及び連結部Ｔ２１を外部パッド２の間を通し
て他のテープＴ２〜Ｔ５及びＴ７〜Ｔ１１を迂回するよ
うにした。その結果、高電位電源端子ＶＣＣ２，ＶＣＣ
３及び低電位電源端子ＶＳＳ２，ＶＳＳ３に対応する外
部ピンが不要となり、外部ピンのピン数の増加を抑える
ことができ、パッケージのパッケージサイズを小さくす
ることができる。 （第二実施例）以下、本発明を具体化した第二実施例に
ついて説明する。As described above, in this embodiment, the connecting portion T20 connecting the high potential power supply terminals VCC1 and VCC4 and the connecting portion T connecting the low potential power supply terminals VSS1 and VSS4.
21 and 21 are formed so as not to intersect with each other.
Further, the connecting portion T20 and the connecting portion T21 and another tape T2
At the positions where ˜T5 and T7 to T11 intersect with each other, the connecting portion T20 and the connecting portion T21 are passed between the external pads 2 and bypass the other tapes T2 to T5 and T7 to T11. As a result, the high potential power supply terminals VCC2, VCC
3 and the low-potential power supply terminals VSS2 and VSS3 are not required, the increase in the number of external pins can be suppressed, and the package size can be reduced. (Second Embodiment) A second embodiment of the present invention will be described below.
【００３３】尚、説明の便宜上、図１４と同様の構成に
ついては同一の符号を付してその説明を一部省略する。
図２はＴＡＢ技術を用いてＳＶＰ型のパッケージに封止
した半導体メモリのチップを示す。本実施例において、
高電位電源端子ＶＣＣ１，ＶＣＣ２と低電位電源端子Ｖ
ＳＳ１，ＶＳＳ２は、低電位電源端子ＶＳＳ１，ＶＳＳ
２が高電位電源端子ＶＣＣ１，ＶＣＣ２に対して内側と
なるように配置されている。又、高電位電源端子ＶＣＣ
３，ＶＣＣ４と低電位電源端子ＶＳＳ３，ＶＳＳ４は低
電位電源端子ＶＳＳ３，ＶＳＳ４が高電位電源端子ＶＣ
Ｃ３，ＶＣＣ４に対して内側となるように配置されてい
る。即ち、両電源端子ＶＣＣ１とＶＣＣ２及びＶＳＳ１
とＶＳＳ２とがそれぞれ入れ子となるように配置されて
いる。そして、両電源端子ＶＣＣ３とＶＣＣ４及びＶＳ
Ｓ３とＶＳＳ４とがそれぞれ入れ子となるように配置さ
れている。For convenience of explanation, the same components as those shown in FIG. 14 are designated by the same reference numerals, and the description thereof will be partially omitted.
FIG. 2 shows a semiconductor memory chip encapsulated in an SVP type package using the TAB technology. In this example,
High potential power supply terminals VCC1 and VCC2 and low potential power supply terminal V
SS1 and VSS2 are low potential power supply terminals VSS1 and VSS
2 is arranged inside the high-potential power supply terminals VCC1 and VCC2. In addition, high potential power supply terminal VCC
3, VCC4 and low potential power supply terminals VSS3 and VSS4 are low potential power supply terminals VSS3 and VSS4 are high potential power supply terminals VC.
It is arranged so as to be inside with respect to C3 and VCC4. That is, both power supply terminals VCC1, VCC2 and VSS1
And VSS2 are arranged so as to be nested. Then, both power supply terminals VCC3, VCC4 and VS
S3 and VSS4 are arranged so as to be nested.
【００３４】チップ２１上に形成された外部パッド２の
うち、両端に形成された高電位電源端子ＶＣＣ１，ＶＣ
Ｃ４、低電位電源端子ＶＳＳ１，ＶＳＳ４と各入出力端
子ＤＱ１〜ＤＱ４及び各アドレス端子Ａ１〜Ａ４がテー
プＴ１〜Ｔ１２を介してリードＬ１〜Ｌ１２にそれぞれ
接続されている。Of the external pads 2 formed on the chip 21, high potential power supply terminals VCC1 and VC formed at both ends.
C4, low potential power supply terminals VSS1 and VSS4, input / output terminals DQ1 to DQ4, and address terminals A1 to A4 are connected to leads L1 to L12 via tapes T1 to T12, respectively.
【００３５】低電位電源端子ＶＳＳ２にはテープＴ３０
が接続され、そのテープＴ３０を介して低電位電源端子
ＶＳＳ１に接続されている。テープＴ３０は外部パッド
２に対してテープＴ３，Ｔ４とは反対側に形成され、テ
ープＴ３，Ｔ４を迂回している。A tape T30 is attached to the low potential power supply terminal VSS2.
Is connected to the low potential power supply terminal VSS1 via the tape T30. The tape T30 is formed on the opposite side of the external pad 2 from the tapes T3 and T4 and bypasses the tapes T3 and T4.
【００３６】低電位電源端子ＶＳＳ３にはテープＴ３１
が接続され、そのテープＴ３１を介して低電位電源端子
ＶＳＳ４に接続されている。テープＴ３１は外部パッド
２に対してテープＴ７〜Ｔ１０とは反対側に形成され、
テープＴ７〜Ｔ１０を迂回している。A tape T31 is attached to the low potential power supply terminal VSS3.
Is connected to the low potential power supply terminal VSS4 via the tape T31. The tape T31 is formed on the opposite side of the external pad 2 from the tapes T7 to T10,
It bypasses the tapes T7 to T10.
【００３７】高電位電源端子ＶＣＣ１及びＶＣＣ４は連
結部Ｔ３２によって接続されている。連結部Ｔ３２は外
部パッド２に対してテープＴ２〜Ｔ１１とは反対側に形
成され、テープＴ３０及びＴ３１の側方に形成されてい
る。従って、連結部Ｔ３２はテープＴ２〜Ｔ１１及びＴ
３０，Ｔ３１と交差することはない。The high potential power supply terminals VCC1 and VCC4 are connected by a connecting portion T32. The connecting portion T32 is formed on the side opposite to the tapes T2 to T11 with respect to the external pad 2, and is formed on the side of the tapes T30 and T31. Therefore, the connecting portion T32 includes the tapes T2 to T11 and T.
It does not intersect with 30, T31.
【００３８】連結部Ｔ３２にはテープＴ３３，Ｔ３４が
突出形成され、そのテープＴ３３，Ｔ３４は高電位電源
端子ＶＣＣ２，ＶＣＣ３にそれぞれ接続されている。従
って、高電位電源端子ＶＣＣ２はテープＴ３３及び連結
部Ｔ３２を介して高電位電源端子ＶＣＣ１，ＶＣＣ４に
接続されている。又、高電位電源端子ＶＣＣ３はテープ
Ｔ３４及び連結部Ｔ３２を介して高電位電源端子ＶＣＣ
１，ＶＣＣ４に接続されている。Tapes T33 and T34 are projectingly formed on the connecting portion T32, and the tapes T33 and T34 are connected to the high potential power supply terminals VCC2 and VCC3, respectively. Therefore, the high potential power supply terminal VCC2 is connected to the high potential power supply terminals VCC1 and VCC4 via the tape T33 and the connecting portion T32. The high potential power supply terminal VCC3 is connected to the high potential power supply terminal VCC via the tape T34 and the connecting portion T32.
1, connected to VCC4.
【００３９】そして、各テープＴ１〜Ｔ１２，Ｔ３０，
Ｔ３１、連結部Ｔ３２及びテープＴ３３，Ｔ３４は交差
することなく、同一平面で２次元的構造を取ることがで
きる。従って、高電位電源端子ＶＣＣ２，ＶＣＣ３及び
低電位電源端子ＶＳＳ２，ＶＳＳ３に対応した外部ピン
を設ける必要がなく、外部ピンの増加を抑えることがで
き、パッケージを小さくすることができる。Then, the tapes T1 to T12, T30,
The T31, the connecting portion T32, and the tapes T33 and T34 can have a two-dimensional structure on the same plane without intersecting each other. Therefore, it is not necessary to provide external pins corresponding to the high-potential power supply terminals VCC2 and VCC3 and the low-potential power supply terminals VSS2 and VSS3, the increase in external pins can be suppressed, and the package can be made smaller.
【００４０】このように、本実施例では、低電位電源端
子ＶＳＳ１とＶＳＳ２とを接続するテープＴ３０と、低
電位電源端子ＶＳＳ３とＶＳＳ４とを接続するテープＴ
３１を、外部パッド２に対してそれぞれテープＴ３，Ｔ
４及びＴ７〜Ｔ１０とは反対側に形成し、テープＴ３，
Ｔ４及びＴ７〜Ｔ１０を迂回するようにした。又、高電
位電源端子ＶＣＣ２，ＶＣＣ３と高電位電源端子ＶＣＣ
１，ＶＣＣ４とをつなぐ連結部Ｔ３２を外部パッド２に
対してテープＴ２〜Ｔ１１とは反対側に形成するととも
に、テープＴ３０，Ｔ３１の側方に形成し、テープＴ２
〜Ｔ１１及びテープＴ３０，Ｔ３１を迂回するようにし
た。その結果、高電位電源端子ＶＣＣ２，ＶＣＣ３及び
低電位電源端子ＶＳＳ２，ＶＳＳ３に対応する外部ピン
が不要となり、外部ピンのピン数の増加を抑えることが
できる。そして、外部ピンのピンピッチを図１４のパッ
ケージに比べて大きくすることができるので、実装を容
易にすることができる。As described above, in the present embodiment, the tape T30 connecting the low potential power supply terminals VSS1 and VSS2 and the tape T connecting the low potential power supply terminals VSS3 and VSS4.
31 to the external pads 2 and tapes T3 and T, respectively.
4 and T7 to T10 are formed on the side opposite to the tape T3.
Bypasses T4 and T7 to T10. In addition, the high potential power supply terminals VCC2 and VCC3 and the high potential power supply terminal VCC
A connecting portion T32 for connecting 1 and VCC4 is formed on the side opposite to the tapes T2 to T11 with respect to the external pad 2, and is formed on the side of the tapes T30 and T31.
˜T11 and tapes T30 and T31 are detoured. As a result, external pins corresponding to the high-potential power supply terminals VCC2 and VCC3 and the low-potential power supply terminals VSS2 and VSS3 become unnecessary, and the increase in the number of external pins can be suppressed. Since the pin pitch of the external pins can be made larger than that of the package of FIG. 14, mounting can be facilitated.
【００４１】なお、本発明は前記実施例に限定されるも
のではなく、以下の態様で実施するようにしてもよい。 （１）前記各実施例において高電位電源端子ＶＣＣ１，
ＶＣＣ４と低電位電源端子ＶＳＳ１，ＶＳＳ４に対応す
る外部ピンをそれぞれ設けたが、図３又は図４に示すよ
うに、何れか一方の高電位電源端子ＶＣＣ１と低電位電
源端子ＶＳＳ４に対応する外部ピンを設け、高電位電源
端子ＶＣＣ４と高電位電源端子ＶＣＣ１〜ＶＣＣ３、低
電位電源端子ＶＳＳ１と低電位電源端子ＶＳＳ２〜ＶＳ
Ｓ４とを接続するようにしてもよい。その結果、外部ピ
ンのピン数を１０ピンにすることができ、更にピン数の
低減又はピンピッチの拡大をすることができる。The present invention is not limited to the above embodiment, but may be carried out in the following modes. (1) In each of the above embodiments, the high potential power supply terminal VCC1,
Although the external pins corresponding to the VCC4 and the low-potential power supply terminals VSS1 and VSS4 are provided respectively, as shown in FIG. 3 or 4, one of the external pins corresponding to the high-potential power supply terminal VCC1 and the low-potential power supply terminal VSS4 is provided. Are provided, the high-potential power supply terminal VCC4 and the high-potential power supply terminals VCC1 to VCC3, the low-potential power supply terminal VSS1 and the low-potential power supply terminals VSS2 to VS.
You may make it connect with S4. As a result, the number of external pins can be reduced to 10, and the number of pins can be reduced or the pin pitch can be increased.
【００４２】又、高電位電源端子ＶＣＣ２（ＶＣＣ３）
と低電位電源端子ＶＳＳ２（ＶＳＳ３）に対応した外部
ピンを設け、他の電源端子を接続するようにしてもよ
い。１つだけ設けるようにしてもよい。Further, the high potential power supply terminal VCC2 (VCC3)
And an external pin corresponding to the low potential power supply terminal VSS2 (VSS3) may be provided to connect to another power supply terminal. You may make it provide only one.
【００４３】（２）本発明をパッケージとしてＴＳＯＰ
型又はＳＶＰ型のパッケージに用いたが、ＳＯＪ等他の
アウトラインパッケージに用いてもよい。又、ＤＩＰ
（DualInline Package ）型やＺＩＰ型等のインライン
パッケージに用いてもよい。(2) TSOP as a package of the present invention
Type or SVP type package, it may be used for other outline packages such as SOJ. Also, DIP
It may be used for in-line packages such as (DualInline Package) type and ZIP type.
【００４４】（３）前記各実施例ではチップ１，２１上
に形成する外部パッド２を１列に形成したが、２列以上
複数に形成してもよい。又、外部パッド２の数を適宜に
変更するようにしてもよい。(3) In each of the above embodiments, the external pads 2 formed on the chips 1 and 21 are formed in one row, but they may be formed in two or more rows. Further, the number of external pads 2 may be changed appropriately.
【００４５】（４）前記第二実施例ではチップ２１の両
電位電源端子の配列を接続し易いように変更してＳＶＰ
型のパッケージに封止したが、このチップ２１は図５に
示すようにＴＳＯＰ型パッケージにも容易に封止するこ
とができる。又、電源端子以外の端子の配列を任意に変
更して実施してもよい。(4) In the second embodiment, the arrangement of the both-potential power supply terminals of the chip 21 is changed so as to be easily connected, and the SVP is changed.
Although it is sealed in a mold package, this chip 21 can be easily sealed in a TSOP package as shown in FIG. Further, the arrangement of terminals other than the power supply terminal may be arbitrarily changed for implementation.
【００４６】（５）前記各実施例ではアドレス端子Ａ１
〜Ａ４、入出力端子ＤＱ１〜ＤＱ４を設けたが、アドレ
ス端子の数、入出力端子の数及び各電源端子の数を適宜
に変更して実施するようにしてもよい。又、前記各実施
例以外の信号に対する端子を加えて実施してもよい。(5) In each of the above embodiments, the address terminal A1
A4 to A4 and input / output terminals DQ1 to DQ4 are provided, the number of address terminals, the number of input / output terminals, and the number of power supply terminals may be changed as appropriate. Further, it may be carried out by adding terminals for signals other than those in the above-mentioned respective embodiments.
【００４７】（６）前記各実施例では高電位電源端子Ｖ
ＣＣ１〜ＶＣＣ４、低電位電源端子ＶＳＳ２〜ＶＳＳ４
を接続したが、何れか一方のみを接続するようにしても
よい。この時、上記各実施例よりも外部ピンのピン数が
多くなるが、従来のパッケージに比べて外部ピンのピン
数を少なくすることができる。(6) In each of the above embodiments, the high potential power supply terminal V
CC1 to VCC4, low potential power supply terminals VSS2 to VSS4
However, only one of them may be connected. At this time, the number of external pins is larger than that in each of the above-described embodiments, but the number of external pins can be reduced as compared with the conventional package.
【００４８】（７）前記各実施例では、同一の電気信号
として電源端子を例にあげたが、アドレス端子や入出力
端子、またはそれ以外の制御信号端子のうちで同一の電
気信号端子に対して実施してもよい。また、本来は同一
でなくとも、半導体装置の設計過程において同一とすべ
き理由が生じた電気信号端子に対して実施してもよい。(7) In each of the above embodiments, the power supply terminal is taken as an example of the same electric signal, but the same electric signal terminal among the address terminal, the input / output terminal, and the other control signal terminals is used. You may carry out. Further, the electrical signal terminals may be implemented for the same reason in the semiconductor device designing process, even if they are not the same originally.
【００４９】[0049]
【発明の効果】以上詳述したように、本発明によれば、
同一の電気信号を扱う複数のパッドに対応する内部リー
ドを、他の電気信号を扱うパッドに対応する内部リード
を迂回して形成し、その内部リードを前記同一の電気信
号を扱う複数のパッドに接続したので、外部リードの数
を減少させることができる。その結果、チップを封止す
る樹脂封止体の大きさを小さくかつ薄くすることができ
る優れた効果がある。As described in detail above, according to the present invention,
An internal lead corresponding to a plurality of pads handling the same electric signal is formed bypassing an internal lead corresponding to a pad handling another electric signal, and the internal lead is formed to the plurality of pads handling the same electric signal. Since it is connected, the number of external leads can be reduced. As a result, there is an excellent effect that the size of the resin sealing body that seals the chip can be made small and thin.
【図１】本発明の第一実施例の半導体装置を説明する平
面図である。FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment of the present invention.
【図２】第二実施例の半導体装置を説明する正面図であ
る。FIG. 2 is a front view illustrating a semiconductor device according to a second embodiment.
【図３】第一実施例の半導体装置の別例を説明する平面
図である。FIG. 3 is a plan view illustrating another example of the semiconductor device of the first embodiment.
【図４】第二実施例の半導体装置の別例を説明する正面
図である。FIG. 4 is a front view illustrating another example of the semiconductor device of the second embodiment.
【図５】第二実施例の半導体チップをＴＳＯＰ型パッケ
ージに封止した半導体装置を説明する平面図である。FIG. 5 is a plan view illustrating a semiconductor device in which the semiconductor chip of the second embodiment is sealed in a TSOP type package.
【図６】単一電源線における出力バッファ回路を説明す
る概念図である。FIG. 6 is a conceptual diagram illustrating an output buffer circuit in a single power supply line.
【図７】複数電源線における出力バッファ回路を説明す
る概念図である。FIG. 7 is a conceptual diagram illustrating an output buffer circuit in a plurality of power supply lines.
【図８】ＬＯＣ技術で封止する半導体チップを説明する
平面図である。FIG. 8 is a plan view illustrating a semiconductor chip sealed by the LOC technique.
【図９】従来のＳＯＪ型パッケージに封止した半導体装
置を説明する平面図である。FIG. 9 is a plan view illustrating a semiconductor device sealed in a conventional SOJ type package.
【図１０】従来のＳＯＪ型パッケージに封止した半導体
装置を説明する側面図である。FIG. 10 is a side view illustrating a semiconductor device sealed in a conventional SOJ type package.
【図１１】ＴＳＯＰ型パッケージに封止しようとした半
導体装置を説明する側面図である。FIG. 11 is a side view illustrating a semiconductor device which is to be sealed in a TSOP type package.
【図１２】ＴＡＢ技術を用いてＴＳＯＰ型パッケージに
封止した半導体装置を説明する側面図である。FIG. 12 is a side view illustrating a semiconductor device sealed in a TSOP type package by using TAB technology.
【図１３】ＴＡＢ技術を用いてＴＳＯＰ型パッケージに
封止した半導体装置を説明する平面図である。FIG. 13 is a plan view illustrating a semiconductor device sealed in a TSOP type package by using TAB technology.
【図１４】ＴＡＢ技術を用いてＳＶＰ型パッケージに封
止した半導体装置を説明する正面図である。FIG. 14 is a front view illustrating a semiconductor device sealed in an SVP type package by using TAB technology.
【図１５】ＴＡＢ技術を用いてＳＶＰ型パッケージに封
止した半導体装置を説明する側面図である。FIG. 15 is a side view illustrating a semiconductor device sealed in an SVP type package using the TAB technology.
１ チップ ２ 外部パッド Ｌ１〜Ｌ１２ リード Ｔ１〜Ｔ１２ テープ Ｔ２０，Ｔ２１ 連結部 Ｔ２２〜Ｔ２５ テープ Ｔ３０，Ｔ３１ テープ Ｔ３２ 連結部 Ｔ３３，Ｔ３４ テープ 1 chip 2 external pad L1 to L12 lead T1 to T12 tape T20, T21 connection part T22 to T25 tape T30, T31 tape T32 connection part T33, T34 tape
Claims (5)
号を扱う複数のパッド（２）が、一方向に延びるように
配置された半導体チップ（１）を樹脂封止体（１０）で
封止し、前記樹脂封止体（１０）の外側には信号を伝達
するための複数の外部リード（７）を設け、前記樹脂封
止体（１０）内において前記複数のパッド（２）と前記
複数のリード（７）とを複数の内部リード（Ｔ）で接続
した半導体装置において、 前記複数のパッド（２）のうち、同一の電気信号を扱う
複数のパッド（２）に対応する内部リード（Ｔ）を、他
の電気信号を扱うパッド（２）に対応する内部リード
（Ｔ）を迂回して形成し、その内部リード（Ｔ）を前記
同一の電気信号を扱う複数のパッド（２）に接続したこ
とを特徴とする半導体装置。1. A resin encapsulant (10) is a semiconductor chip (1) in which a plurality of pads (2) for handling various electric signals are arranged in the center of the upper surface of the chip (1) so as to extend in one direction. A plurality of external leads (7) for encapsulating and transmitting a signal are provided outside the resin encapsulation body (10), and the plurality of pads (2) are formed in the resin encapsulation body (10). A semiconductor device in which the plurality of leads (7) are connected to each other by a plurality of inner leads (T), the inner leads corresponding to the plurality of pads (2) handling the same electric signal among the plurality of pads (2). (T) is formed by bypassing the internal lead (T) corresponding to the pad (2) that handles another electric signal, and the internal lead (T) is formed by a plurality of pads (2) that handle the same electrical signal. A semiconductor device characterized by being connected to.
を打ち抜いて形成されていることを特徴とする請求項１
に記載の半導体装置。2. The inner lead (T) is formed by punching out a conductive tape.
The semiconductor device according to.
（７）と一体に形成されていることを特徴とする請求項
１に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the inner lead (T) is formed integrally with the outer lead (7).
ッド（２）が配置された方向と平行に形成された前記樹
脂封止体（１０）の辺のうち、一方にのみ形成されてい
ることを特徴とする請求項１〜３の何れか一項に記載の
半導体装置。4. The external lead (7) is formed on only one of the sides of the resin encapsulant (10) formed parallel to the direction in which the pads (2) are arranged. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
ッド（２）が配置された方向と平行に形成された前記樹
脂封止体（１０）の辺の両方に形成されていることを特
徴とする請求項１〜３の何れか一項に記載の半導体装
置。5. The outer lead (7) is formed on both sides of the resin encapsulant (10) formed in parallel with a direction in which the pads (2) are arranged. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25727693A JP3258782B2 (en) | 1993-10-14 | 1993-10-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25727693A JP3258782B2 (en) | 1993-10-14 | 1993-10-14 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07115107A true JPH07115107A (en) | 1995-05-02 |
| JP3258782B2 JP3258782B2 (en) | 2002-02-18 |
Family
ID=17304133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25727693A Expired - Lifetime JP3258782B2 (en) | 1993-10-14 | 1993-10-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3258782B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7449370B2 (en) | 2002-08-19 | 2008-11-11 | Nec Electronics Corporation | Production process for manufacturing such semiconductor package |
-
1993
- 1993-10-14 JP JP25727693A patent/JP3258782B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7449370B2 (en) | 2002-08-19 | 2008-11-11 | Nec Electronics Corporation | Production process for manufacturing such semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3258782B2 (en) | 2002-02-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5461255A (en) | Multi-layered lead frame assembly for integrated circuits | |
| JP3754221B2 (en) | Multi-chip type semiconductor device | |
| US6148509A (en) | Method for supporting an integrated circuit die | |
| US6008996A (en) | Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die | |
| US5428247A (en) | Down-bonded lead-on-chip type semiconductor device | |
| US6160307A (en) | Semiconductor packages having split die pad | |
| TW567602B (en) | Multi-chip module | |
| JP2560805B2 (en) | Semiconductor device | |
| US5276352A (en) | Resin sealed semiconductor device having power source by-pass connecting line | |
| JPH04116859A (en) | Semiconductor device | |
| US6052289A (en) | Interdigitated leads-over-chip lead frame for supporting an integrated circuit die | |
| JP3258782B2 (en) | Semiconductor device | |
| JPS6070755A (en) | Semiconductor device | |
| JP2896223B2 (en) | Resin-sealed semiconductor device | |
| JPH01243441A (en) | Semiconductor device and manufacture thereof | |
| JPS60150660A (en) | Semiconductor device | |
| KR100635386B1 (en) | Semiconductor chip package with high speed signal processing | |
| KR100235108B1 (en) | Semiconductor package | |
| JP3052633B2 (en) | Semiconductor device | |
| JPH10116963A (en) | Semiconductor device, electronic device and manufacturing method thereof | |
| JP2963548B2 (en) | Semiconductor device | |
| JPH046105B2 (en) | ||
| JPH10284633A (en) | Semiconductor integrated circuit device and manufacturing method therefor | |
| JPH0445566A (en) | Lead frame and semiconductor device wherein this is used | |
| JPH05136332A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20011127 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071207 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081207 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081207 Year of fee payment: 7 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313115 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081207 Year of fee payment: 7 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091207 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091207 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101207 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111207 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111207 Year of fee payment: 10 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111207 Year of fee payment: 10 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111207 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121207 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121207 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131207 Year of fee payment: 12 |
|
| EXPY | Cancellation because of completion of term |