JPH07112243B2 - Block division sequential reproduction coding method - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a high-efficiency coding system for grayscale images including halftones, and more particularly to a multi-gradation adaptive block coding system (hereinafter
"GBTC method") and sequential reproduction coding method (hereinafter,
The present invention relates to a block-division sequential reproduction coding system (hereinafter referred to as "BSPC system") modified by combining with "PCS system").

(Prior art and its problems) The demand for natural image transmission in telematic services is increasing not only in center-tended communication such as videotex but also in end-end communication such as facsimile. The GBTC method and the PCS method are typical encoding methods used for these communications.

First, the outline of the conventional GBTC method will be described.

FIG. 1 is a schematic diagram of a conventional GBTC, where 1 is an image data input terminal, 2 is a buffer memory, 3 is a maximum / minimum value detection circuit for image data in a block, and 4 is a maximum / minimum representative gradation. A decision circuit, 5 is a gradation level memory, 7 is a comparison circuit,
Reference numeral 8 is a resolution component memory, 9 is a reference level generating circuit, and 10 is a difference value generating circuit.

The Huffa memory 2 inputs an image signal of a pixel unit from the terminal 1, accumulates image data of one block line (one vertical column, one horizontal block column), and outputs pixel data block by block. . The pixel data stored in the buffer memory 2 is read out block by block and subjected to necessary processing.

The following description will be made assuming that image data is approximated with 256 gradations (0 to 255), block size is 4 × 4 pixels, and one block is approximated with maximum 4 gradations.

The coding information of each block is created as follows. First, the maximum / minimum value detection circuit 2 reads the pixel data for one block from the buffer memory 2, finds the maximum value (L _max ) and the minimum value (L _min ) in the block, and further calculates the level from these values. Find the difference D = L _max −L _min .

Further, as shown in FIG. 2, the level difference D is compared with the threshold values T ₁ and T _2, and the number of gradations for displaying the block is determined to be 1 to 4 depending on the magnitude of D. Subsequently, the maximum and minimum representative gradation determination circuit 4
Represents the maximum value and maximum value (hereinafter referred to as maximum representative gradation and minimum representative gradation, respectively) of the representative gradation for expressing the block by quantizing it into k gradations (k = 1,2,4). Value P ₀ , P
_{Find k} (k = 1,2) or Q _k (k = 1,4).

A method of obtaining these values will be described by taking a 4-gradation expression as an example.

(1) First, the average value of L _max and L _min is A = 1/2 (L _max + L
_min ) and divide the two values into four areas a ₁ , a ₂ , a ₃ , a ₄ as shown in FIG. ₃ , and calculate the average value of the pixel data belonging to the areas a ₁ and a _4. Use the initial values of Q ₁ and Q ₄ , respectively.

That is, The average of the above pixel data is Q ₁ Let Q ₄ be the average of the pixel data below.

If Q ₂ and Q ₃ are set at equal intervals between Q _{1 to} Q ₄ ,
As is clear from FIG. Given in. However, L _A = (Q ₁ + Q ₂ ) / 2 (reference value) L _D
= Q ₁ −Q ₄ (difference value). The quantization level in the first approximation when the block is expressed by 4 gradations, that is, the representative gradation is given by the above Q ₁ , Q ₂ , Q ₃ and Q ₄ .

(2) Next, considering that the pixel data X in the block is classified into clusters to be represented by the one having the shortest distance among these representative gradations, the cluster represented by Q ₁ (hereinafter referred to as the cluster Called 1 cluster) The cluster represented by Q ₄ (hereafter called the 4th cluster) Pixel data that satisfies the above condition belongs.

Therefore, the representative gradation Q ₁ of the first cluster is replaced with the average value of the pixel data of the first cluster. Similarly, the representative gradation Q ₄ of the fourth cluster is replaced with the average value of the pixel data of the fourth cluster. As a result, Q ₁ and Q ₄ are updated to new values with better approximation.

Here, L _D = Q ₁ −Q ₄ is obtained again, L _D is updated, and then Q ₂ and Q ₃ are obtained again by the equation, whereby a new representative gradation is determined.

(3) The process of (2) is repeated.

(4) When the values of Q _{1 to} Q ₄ hardly change even by the processing of (2), it is determined that they have converged, and the obtained Q ₁ , Q ₂ , Q ₃ , and Q ₄ are finally determined. The representative gradation is set.

(5) The processing of (2) does not necessarily have to be performed until convergence and can be arbitrarily terminated.

Particularly, even if the operation of (2) is not performed and the values of Q _{1 to} Q ₄ obtained by the processing of (1) are used as the representative gradation, a fairly good approximation can be obtained, which is practically sufficient.

The same applies to the case of expressing two gradations (FIG. 5 (a)). For example, the average of pixel data of A = 1/2 (L _max + L _min ) or more is P
_With the initial value of ₁ and the average of pixel data less than A as the initial value of P _2, a first approximation representative gradation is obtained. In classifying the clusters, representative gradations P ₁ and P ₂ (P ₁ > P ₂ ) can be obtained by updating the value of A by A = 1/2 (P ₁ + P ₂ ) and then repeating the above process.

In the case of one gradation expression, the representative gradation is the average value of the pixel data of all the pixels in the block regardless of the initial value.

The pixel data of each pixel in the block is cluster-classified according to the representative gradation in the block thus obtained, so that the comparison circuit 7 and the gradation level memory circuit 5 change the representative gradation value or the representative gradation value. It is provided for temporary storage of things.

For example, in the case of expressing four gradations, representative gradations Q ₁ , Q
₂ , Q ₃ and Q ₄ are temporarily stored in the gradation level memory circuit 5, the pixel data in the block are sequentially read from the buffer memory 2, and the comparator circuit 7 determines the closest representative gradation. The determination result is expressed as a resolution component φ by, for example, 2 bits, and is stored in the resolution component memory 8. Therefore, the value stored in the gradation level memory circuit 5 does not necessarily have to be the representative gradation. May be In this case, if the pixel data X is XTQ ₁ , the first cluster (representative gradation Q ₁ ) TQ ₁ > X ≧ TQ ₂ is the second cluster (representative gradation Q ₂ ) TQ ₂ > X ≧ TQ ₃ is the third cluster Cluster (representative gradation Q ₃ ) If TQ ₃ > X, it is classified as the fourth cluster (representative gradation Q ₄ ).

On the other hand, the reference level generating circuit 9, the maximum, and average value L _A look reference level of the maximum representative gray-scale and the lowest representative tone determined by the minimum representative tone decision circuit 4.

Further, the difference value generation circuit 10 similarly obtains the difference L _D between the maximum representative gradation and the minimum representative gradation. L in the case of 1, 2, 4 gradation expression
Table 1 shows how to obtain _A and L _D.

As described above, the original image data in the block is represented by the three types of components L _A , L _D , and φ. The value of each of these components may be individually compression-coded. As the compression encoding method, L _A and L _D use the DPCM method, and φ uses the MMR method.

Given the values of L _A , L _D , and φ in Table 1, the following equation can be used to restore the current image from them.

1 gradation: P ₀ = L _A 2 gradation _{expression: P 1 = L A + 1} / 2L D P 2 = L A -1 / 2L D 4 _{gradations: Q 1 = L A + 1} / 2L D Q 2 = L _A −1 / 6L _D Q ₃ ＝ L _A −1 / 6L _D Q ₄ ＝ L _A −1 / 2L _D For example, in the case of 4 gradation expression, the initial value of Q ₁ is in the area a ₁ . Instead of taking the average of the image data, the median of the area a ₁ , that is, A + 3 / 8D may be used. The influence of the way of obtaining the initial value only affects the approximation accuracy, and does not affect the basic condition of code decoding.

Further, in the above description, the case where each block is represented by 4 gradations or less has been described, but the present invention can also be applied to the case where many representative gradations such as 1, 2, 4, 8, 16 ... Are included. For example, when a block is represented by 8 gradations, if the representative gradation is R _k (k = 1,2,3 ... 8), the maximum representative gradation R ₁ and the minimum representative gradation are the same as described in the 4 gradation expression. Gradation R ₈ is calculated, and R _{2 to} R ₇ are calculated by dividing the gradation at equal intervals. When maximizing 2 ⁿ gray scales, the resolution component is represented by n bits.

Further, the difference value L _D does not necessarily have to be the difference between the maximum representative gradation and the minimum representative gradation, and the definition may be different between the two gradation expression and the four gradation expression. 5 and 2
The table is an example in which L _D = 2/3 (Q ₁ −Q ₂ ) in the case of 4-gradation expression.

FIG. 6 shows a process from forming the encoded signal from the image data. It is a block diagram of the conventional GBTC method. The process up to forming the reference level L _A and the differential signal L _D as shown in Table 2 has been described in FIG.

The reference level L _A is output from the reference level generating circuit 9 in the order of each block of one block line. The reference level coding circuit 11 generates a predetermined binary code (code consisting of 1 and 0) for each value of L _A.

In this way, L _A is sequentially converted into a binary code and stored in the buffer memory 13. The difference value L _D is converted into a predetermined binary code by the difference value encoding circuit 15 and sequentially stored in the buffer memory 16.

Incidentally, regardless of the value of L _D in the case of where the block is 1 gradation is controlled so that the same code is output in the case of the L _D = 0 from the difference value encoding circuit 15 .

Further, according to Table 3, the resolution component φ ₁ ,
φ ₂ is output and temporarily stored in the φ ₁ buffer 18 and the φ ₂ buffer 19, respectively, then encoded by the φ encoding circuit 12 to suppress the redundancy, and then stored in the φ ₁ memory 21 and the φ ₂ memory 22. It

When the processing for one screen is completed, the coded signals of L _A , L _D , φ ₁ , and φ ₂ are stored in the buffer memories 13, 16, φ ₁ memory 21, and φ ₂ memory 22, respectively. These signals are respectively taken out from terminals 14, 17, 23 and 24, combined by the signal combiner 20 and sent out from the terminal 25 in the order of L _A , L _D , φ ₁ and φ ₂ in the above description. This is coded by setting L _D = 0 in the tone expression block to obtain a coded signal. However, in all the 1 tone expression blocks, L _D = 0, this information is not always necessary and can be omitted. .

Next, the decoding method will be described by taking the case of using L _A and L _D in Table 2 as an example. FIG. 7 is a block diagram showing a configuration example of a conventional decoding circuit used in the GBTC system, in which 31 is a reference level decoding circuit, 32 is a difference value decoding circuit, 33 is a resolution component decoding circuit, and 34 is an image memory. circuit, 35 L _D memory, 36 is the arithmetic circuit, 37 a buffer memory, 40 is a signal distribution circuit. The signal input from the terminal 30 is distributed to each decoding circuit by the signal distribution circuit 40, and the encoded signal of L _A is decoded by the reference level decoding circuit 31 and the value of L _A is output. The image signal S ₁ S ₁ = L _A is given to all the pixels in the block and stored in the image memory circuit 34. When all L _{A of} one screen are decoded, S ₁ forms a schematic image.

Subsequently the coded signal of the difference value L _D is decodes thereby is input difference value decoding circuit 32, memory values of the decoded L _D to L _D memory 35.

Next, when the encoded signal of φ ₁ is input, φ ₁ is also decoded by the resolution component decoding circuit 33, the value of L _D of the corresponding block is referred from the L _D memory 35, and (1) L _D = 0 If so, S ₂ = S ₁ (block S ₁ is not changed) because it is a block with 1 gradation. (2) If L _D ≠ 0, it is a block with 2 gradations or 4 gradations. If φ ₁ = 0, then S ₂ = S ₁ +1 If / 2L _D φ ₁ = 0, the content of the image memory circuit 34 is rewritten from S ₁ to S ₂ with S ₂ = S ₁ −1 / 2L _D. Then, when a code signal of φ ₂ is input, φ ₂ is decoded by the resolution component decoding circuit 33, and (1) if φ ₂ = 0 in all the pixels in one block, one or two gradation representation Since it is a block, each pixel in the lock is S ₃ = S ₂ (S ₂ is not changed) (2) If there is at least one pixel φ ₂ = 1 pixel in one block, it is a 4-gradation expression φ ₂ = The pixel of 0 is S ₃ = S ₂ + 1 / 4L _D φ ₂ = 1 and the pixel of S ₃ = S ₂ −1 / 4L _D is set, and the contents of the image memory circuit 34 are rewritten from S ₂ to S ₃ .

S ₃ thus obtained represents the decoded image.

It should be noted that the above S ₂ is the representative gradation Q ₁
And Q ₂ at 1/2 (Q ₁ + Q ₂ ) and representative gradations Q ₃ and Q ₄ at 1/2 (Q ₃ +
Since it is approximated by Q ₄ ), it has an intermediate quality between S ₁ and S ₃ . Therefore, the approximate image content can be known even during the decoding process is performed stepwise.

Generally, when expressing with r gradations of R _{1 to} R _r (r> 2),
The difference value is If it is set to a value proportional to, then progressive decoding becomes possible.

The decoding method described the case where a coded signal exists even when L _D = 0, but as described above, φ ₁ is decoded when the L _D coded signal when L _D = 0 is omitted. After that, if there is a block in which φ ₁ is all “0” in the block, data of L _D = 0 may be created and inserted into the corresponding memory position of the L _D memory 35. Therefore, in this case, the encoded signal is L _A , φ ₁ , L _D ,
It is more convenient to send in φ ₂ order.

Next, an outline of the encoding / decoding method in the conventional PCS method (Japanese Patent Laid-Open No. 62-25575) will be described. In this explanation,
The gradation number of the target encoded image is 16 gradations (4 bits).

In the PCS encoding system, the image bit plane is decomposed into the following three types of encoding means for encoding.

Initial encoding: From the pixels forming each bit lane, pixels are extracted every ΔX pixels from the line for each ΔY line, and these pixels are encoded.

Mode 1 encoding: 4 located at the vertex of the smallest rectangle of encoded pixels
Pixels located at the center surrounded by these four reference pixels are encoded by referring to the pixels of each plane that have already been encoded at the same positions as the four pixels.

Mode 2 encoding: Among the pixels encoded by the initial encoding unit and the mode 1 encoding unit, four pixels located at the same position as the four pixels located at the apex of the smallest rhombus of each plane that has already been encoded. The pixel located at the center of the pixel is encoded with reference to the pixel.

FIG. 8 shows an example of an encoding circuit in the conventional PCS system. 51 and 52 are input terminals, 53 is a bit conversion circuit, 54 is an address control circuit (I), and 55 is an address control circuit (I
I), 56, 57, 58 and 59 are single-screen memories, 64 is an encoding order control unit, and 65 and 66 are sequential reproduction encoders (I).
And sequential reproduction encoder (II), 67 is a signal combining circuit, 68 is an output terminal, and 60, 61, 62 and 63 are gates.
The operation of the circuit shown in FIG. 8 will be described in detail below. Input terminal
From 51, the signal of the original image to be encoded is sequentially received from the upper left of the image as a starting point in the order of left to right and from top to bottom in a pixel unit, and transferred to the bit conversion circuit 53. Bit conversion circuit 53 is 4
Pixels expressed in bits are decomposed into 1-bit signals,
One-bit signals from MSB to LSB are transferred to one-screen memories 56, 57, 58 and 59, respectively. The original image is 4 by this processing
It is disassembled into one bit plane and stored in one-screen memories 56, 57, 58 and 59, respectively.

The address control circuit (I) 54 gives an instruction as to which coordinate of each one-screen memory 56, 57, 58, 59 the signal transferred from the bit conversion circuit 53 is stored. In each of the one-screen memories 56, 57, 58, 59, the same order as the order in which signals are read from the original image according to the instruction of the address control circuit (I) 54 (starting from the upper left of the image, left to right, top to bottom The information for one screen is accumulated in the order). When the transfer of information to each one-screen memory 56, 57, 58, 59 is completed, the address control circuit (I) 54 transfers a signal indicating the end of transfer to the encoding order control unit 64. When the coding order control unit 64 receives the signal, the gates 60 to 63 are opened to select the plane to be coded according to the previously stored coding order, and the address control circuit (II) 55 is set to code pixels, Instructing the selection of the reference pixel. The address control circuit (II) 55 extracts sequentially encoded pixels and reference pixels from each one-screen memory 56 to 59, and sequentially reproduces the encoded encoder (I) 65 and the sequentially reproduced encoder via the respective gates 60 to 63. (I
I) Transfer to one or both of 66. Sequential playback encoder 65,
Under the control of the encoding order control unit 64, the encoding unit 66 encodes the encoded pixel that passes through each gate. The encoded information output from the sequential reproduction encoding circuit (I) 65, (II) 66 is output to the sequential signal synthesizing circuit 67.

When encoding each plane, first 16 pixels (ΔX =
16, ΔY = 16) as a unit to perform initial encoding as an image with a resolution of 1/16, and then to divide ΔX and ΔY into two to extract the central pixel of the already-encoded pixels to obtain mode 1, A coding signal of resolution 1/8 is obtained by the coding means of mode 2. By repeating the same procedure, coded signals with high resolution of 1/4, 1/2 ... Table 3 shows an example of these encoding orders. Since the encoding is performed sequentially while increasing the resolution to 1/16, 1/8, 1/4 ..., the initial values of ΔX and ΔY are 2 ^w (w
= Integer). The signal synthesis circuit 67 includes an encoding order control unit 64.
The plane display code output from is output to the output terminal 68, the coded plane is determined by this code,
It is stored by the method of storing the coded information of the image shown in Table 4. For example, in the case of plane 1, the output signal of the sequential reproduction encoder (I) 65 is selected as the output signal of the sequential reproduction encoder (II) 66 in the case of planes 2, 3 and 4, and the plane display code is selected. And output to the output terminal 68.

Further, the above-mentioned encoding order is stored in advance in the memory provided in the encoding order control unit 64. Therefore, the encoding order can be arbitrarily set by changing the contents of this memory. This change of the memory contents may be performed on the transmitting side or the receiving side. The signal input terminal for this purpose is the input terminal 52 in the figure.

FIG. 9 shows an example of a conventional decoding circuit in the PCS system, where 301 is an input terminal, 311 is a plane display code extraction circuit, 312 is a decoding plane determination unit, 321 is a sequential reproduction decoding circuit, 331,332,333,334,335,336,337,338. Is a gate circuit, and 341, 342, 343, 344 are one-screen memory A, one-screen memory B for storing binarized planes,
One-screen memory C, one-screen memory D, 351 and 353 are address control circuits (I) and (II), 352 is a bit combining circuit, 361 is a gradation image one-screen memory for storing a gradation image, and 371 is The output terminals are shown.

In the initial state, “1” is stored in all memories of the four one-screen memories 341 to 344, and the gradation image one-screen memory 36
All the memory in 1 stores "15".

The encoded signal is received from the input terminal 301. The plane display code extraction circuit 311 extracts a plane display code from the signal received from the input terminal 301, transfers the code to the decoding plane determination unit 312, and transfers the other codes to the reproduction / decoding circuit 321 sequentially. The sequential reproduction decoding circuit 321 decodes the encoded signal transferred from the plane display code extraction circuit 311 according to the instruction of the decoding plane determination unit 312. Further, the address control circuit (I)) 353 reads out the reference pixel value from each of the one screen memories A to D and sequentially transfers it to the reproduction decoding circuit 321 via the gates 335 to 338. Decoding plane determination unit 312
Determines which plane the plane display code transferred from the plane display code extraction circuit 311 and the code transferred from the input terminal 301 after the plane display code from FIG. 9 relate to, and accordingly, from the gate 331. By opening one of the gates 334, the plane to be decoded is selected and the sequential reproduction decoding circuit 321 is controlled. For example, when receiving the plane display code “10” from the plane display code extraction circuit 311, the decoding plane determination unit 312 opens the gate 333 to combine the information of the plane C and decodes the information of the plane C. The sequential reproduction decoding circuit 321 is instructed. The minimum unit of decoding is each procedure unit at the time of encoding (refer to JP-A-62-25575, "Coding method of gradation facsimile image signal"), and when the decoding of that unit is completed, a sequential reproduction decoding circuit 321 transfers to the decoding plane determination unit 312 a signal instructing the end of decoding. Decoding plane decision unit
Upon receiving the signal, the 312 closes the gate that has been opened (one of the gates 331 to 334) and further transfers the decoding end signal to the plane display code extraction circuit 311. Further, when the plane display code extracting circuit 311 receives the decoding completion signal from the decoding plane determining unit 312, the plane display code extracting circuit 311 extracts the plane display code from the signal input from the input terminal 301 and repeats the above procedure.

The sequential reproduction decoding circuit 321 outputs the decoded image information signal to one screen memory (one of the one screen memory A341 to one screen memory D344) via the opened gate (one of the gates 331 to 334). 1) Transfer to a fixed address and store.

The address control circuit 351 indicates the same coordinates of the four one-screen memories 341 to 344 and the gradation image one-screen memory. The four one-screen memories 341 to 344 transfer the memory contents of the coordinates designated by the address control circuit to the bit synthesizing circuit 352. The bit synthesizing circuit 352 synthesizes the gradation image signal (4 bits) by a predetermined code assignment using the bit information transferred from the one-screen memories 341 to 344, and the memory of the coordinates indicated by the address control circuit 351. Remember. For example, when the signals transferred from the one-screen memories 341 to 344 are "1", "0", "1", and "0", respectively, the combined gradation image signal is "6".

After the decoding by the sequential reproduction decoding circuit 321 is completed, the address control circuit 351 performs the above procedure sequentially for all coordinates from left to right from top to bottom, starting from the upper left corner pixel of one screen. . As a result, the gradation image full screen memory 361
The decoded gradation image information is obtained.

By the way, the GBTC method, which is a conventional technique, has a drawback that it cannot finally completely reproduce the same image as the original image. Further, with regard to the function of sequential reproduction in which a rough entire image is reproduced at an early point and then the image quality is gradually improved, the number of image display stages of sequential reproduction is several, and the number of image display means cannot be increased so much.

On the other hand, in the PCS method, since the number of image display stages of the sequential reproduction can be increased for the sequential reproduction function, the image quality can be continuously improved. Further, finally, the same image as the original image can be reproduced. However, there is a drawback that the coding efficiency is not sufficient in the middle of the sequential reproduction.

(Object of the Invention) An object of the present invention is to be able to continuously improve the image quality of a reproduced image, obtain a high coding efficiency, and finally reproduce the same image as the original image. It is to provide a block-division sequential reproduction coding method.

(Structure of the invention) In order to achieve the object of the present invention, a PCS system is incorporated into the GBTC system, and a reproduced image reproduced by the reference level, the difference value, and the resolution component encoded by the GBTC system. An original image difference creating means for creating an original image difference value which is a difference for each pixel between the original image and the original image, the original image difference value is decomposed into bit planes, and each bit plane is subjected to the initial encoding means and the mode 1 It is configured to include an encoding unit and an encoding unit that performs encoding using the mode 2 encoding unit.

(Example) Hereinafter, the present invention will be described with reference to the drawings.

FIG. 10 shows a block diagram of an encoding device which achieves the object of the present invention. Only the points different from FIG. 6 will be described below. 11
a is a sequential reproduction encoding circuit that encodes the reference level,
Shows a sequential reproduction encoding circuit for encoding resolution components (φ ₁ , φ ₂ ). 26 is an image reproduction circuit, 27 is a difference image generation difference circuit, 28 is a _dij encoder, 29 is a buffer memory, and these circuits are included in the main configuration according to the present invention for achieving the object of the present invention. Be done.

The sequential reproduction encoding circuit 11a uses the upper n (n = n) of the reference level L _A.
(Natural number) bits are taken and quantized into 2 ⁿ gradations, then decomposed into n bit planes, and the above-mentioned PCS encoder performs the encoding processing. In addition, the sequential reproduction coding system circuit 12a
Encodes the resolution components (φ ₁ , φ ₂ ) by the PCS encoder described above.

In the conventional GBTC method, the reference level is encoded by the DPCM method, and the resolution components (φ ₁ , φ ₂ ) are encoded by the MMR method. Therefore, since the DPCM system and the MMR system do not have the characteristic of sequential reproduction, the image quality of image reproduction cannot be continuously improved.

However, according to the present invention, it is possible to increase the number of image display stages for sequential reproduction by incorporating a sequential reproduction encoding method (PCS method) instead of the DPCM method and MMR method.
The above drawbacks can be remedied.

Moreover, since the PCS method has higher coding efficiency than the DPCM method and the MMR method, the coding efficiency can be improved.

Next, the operation of this embodiment will be described.

The image reproduction circuit 26 includes a reference level generation circuit 9 and a difference value generation circuit.
Signals are received from the 10, φ ₁ buffer memory 18 and the φ ₂ buffer memory 19, and reproduced images are generated from them. The difference image generation circuit 27 calculates the difference for each pixel between the original image stored in the buffer memory 2 and the image reproduced by the image reproduction circuit 26, and generates a difference image _dij . It is represented by M bits of each pixel of the difference image _dij and 1 bit flag bit indicating the positive / negative of each pixel. If it is a positive value, the flag bit is "0", otherwise it is "1". The flag bit is MSB (Mos
t Significant Bit) and the difference image _dij is (M +
1) Considered as being composed of bit pixels.

The d _ij encoder 28 encodes the d _ij signal. The encoded information is transferred to the buffer memory 29. Buffer memory 29
The d _ij coded information accumulated in (1) is transferred to the signal combiner 20. The sequential reproduction encoding circuit 11a is the upper n of the reference level L _A.
(N = natural number) bits are taken and quantized into 2 ⁿ gradations, then decomposed into n bit planes, and the above-mentioned PCS encoder performs the encoding processing. The PCS encoder described above is used as the sequential reproduction encoding circuit 12a, the difference value encoding circuit 15, and the _dij encoder 28 for φ encoding.

As described above, the present invention makes the best use of the high-efficiency encoding by dividing each block into three components, which is an advantage of the GBTC method, and the sequential reproduction function, which is an advantage of the PCS method, and is identical to the original image. The image information of can also be encoded with high efficiency.

FIG. 11 shows a block diagram of a decoder according to the BSPC system of the present invention. Only the points different from FIG. 7 will be described below. 38 is d
_{An ij} decoding circuit, 39 is an arithmetic circuit II.

After the decoding of L _A , φ ₁ , L _D , φ ₂ , the _dij signal is reproduced by the _dij decoding circuit 38 and transferred to the arithmetic circuit II 39. Arithmetic circuit I
I 39 first calculates the following from the _dij signal.

Is represented by (M + 1) bits. (A _M , ... a ₀
Is a coefficient: 0 or 1) a _M of MSB is a flag bit, and if a _M = 0, d _ij ≡a _M-1 2 ^M-1 + ... + a ₁ 2 ¹ + a ₀ .

If a _M = 1 then d _ij =-(a _M-1 2 ^M-1 + ... + a ₁ 2 ¹ + a ₀ ). After performing this calculation, the calculation circuit II 39 reads each pixel value of the image memory circuit 34, adds the _dij value of the address corresponding to the pixel value, and writes it to the corresponding address of the image memory 34. When this process is completed, the image memory 34
In this case, an image exactly the same as the original image will be reproduced.

Reference level decoding circuit 31, resolution component φ decoding circuit 33, d
_{The ij} decoding circuit 38 uses the above-mentioned PCS coding method.

The present invention sets the reference level to 2 ⁿ from the viewpoint of facilitating ^{deviceization.}
Gradation (n is a natural number) is set, and this is decomposed into n bit planes. The resolution component is also represented by m bits independently of that, and is represented as m bit planes. 2 ^w as the initial value of ΔX or ΔY for further extracting pixels
It is clear that the use of (w is a natural number) provides a binary display, facilitating digital processing.

(Effects of the Invention) As described above, the present invention enables sequential reproduction by combining the advantages of the conventional GBTC system and the PCS system and providing an original image difference value creation circuit for an original image and a reproduced image. In addition, the original image can be reproduced with high efficiency, and the effect is extremely large.

[Brief description of drawings]

Figure 1, Figure 2, Figure 3, Figure 4, Figure 5 (a)
(B), FIGS. 6 and 7 are schematic diagrams for explaining the conventional GBTC system, FIGS. 8 and 9 are schematic diagrams for explaining the conventional PCS system, and FIG. 10 is the present invention. FIG. 11 is a block diagram of a BSPC encoder according to the present invention, and FIG. 11 is a block diagram of a BSPC decoder according to the present invention.

 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Toshiaki Endo 2-3-2 Nishishinjuku, Shinjuku-ku, Tokyo International Telegraph and Telephone Corporation (72) Inventor Yasuhiro Yamazaki 2-3-2 Nishishinjuku, Shinjuku-ku, Tokyo No. International Telegraph and Telephone Corporation (72) Inventor Hisaharu Kato 2-3-2 Nishishinjuku, Shinjuku-ku, Tokyo International Telegraph and Telephone Corporation (72) Inventor Hiroshi Ochi 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Kenji Ogura 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (72) Makoto Kobayashi 1-1-6 Uchiyuki-cho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (56) References JP-A-62-25575 (JP, A) JP-A-59-153378 (JP, A)

Claims (1)

[Claims] 1. A representative gradation level representing a gradation level of the plurality of pixels in the block is set for each block obtained by dividing an original image into a plurality of blocks each of which includes a plurality of pixels. A reference level encoding circuit that sequentially converts one reference level from the obtained plurality of representative gradation levels into a binary code for each value of each block of one block line; and the plurality of representatives of each of the plurality of blocks. A difference value encoding circuit that creates and encodes a difference value indicating a gradation level distribution range, and encodes a resolution component indicating which of the representative gradation levels each pixel in each of the blocks corresponds to. And a multi-gradation adaptive block coding by using a coding circuit for suppressing redundancy, and a replay reproduced by the reference level, the difference value and the resolution component. An original image difference creating means for creating an original image difference value which is a difference for each pixel between a raw image and the original image, an original image difference value is decomposed into bit planes, and each bit plane is initialized by an encoding means for mode 1 code. Means and mode 2
Further comprising an encoding means for encoding using the encoding means, and each of the reference level and the resolution component further has a multi-gradation facsimile image signal expressed in 2 ⁿ layers in n digits. A means for disassembling correspondingly to create n binary coded bit planes, a first bit plane corresponding to 2 ¹ layers of the n binary coded bit plates and a second bit plane corresponding to 2 ² levels. The bit plane designating means for sequentially designating up to the n-th bit plane corresponding to the 2 ⁿ layer and the bit planes of the designated bit planes for each ΔY line. Initial coding means for extracting every ΔX pixels on the line designated by, coding the extracted pixels, and extracting a coded output having a resolution corresponding to the coarsest extraction period; For one bit plane, a mode in which the pixel located at the center surrounded by the four reference pixels is coded by referring to the four pixels located at the vertices of the smallest rectangle among the initially coded extracted pixels. 1 and further, referring to the four reference pixels located at the apex of the smallest rhombus among the pixels coded by the initial coding and the coding of the mode 1, the pixel located at the center is selected. Encoding mode 2 encoding is performed to obtain an encoded output having a resolution twice the minimum resolution, and thereafter, the value of ΔX and the value of ΔY are each halved. Mode 1 coding and mode 2 coding are performed to obtain a coded output having a resolution four times the minimum resolution, and thereafter the extraction distances ΔX and ΔY are both 2 or less, and all images are coded. Until Ri returns configured block divided sequentially reproduced coding method as encoded by sequentially reproducing the encoding circuit and a coding means for coding.