JPH07111867B2 - Solid-state electron beam generator - Google Patents

Description

The present invention relates to a solid-state electron beam generator.

[Prior Art] One of the conventionally known solid-state electron beam generators is, for example, the device disclosed in US Pat. No. 4,259,678. The device disclosed in this US patent forms a pn junction on a Si semiconductor substrate and applies a reverse voltage to the pn junction.
The avalanche effect produces electrons with higher energy than the thermal equilibrium state (hereinafter referred to as hot electrons), and the kinetic energy of hot electrons is used to extract an electron beam into a vacuum.

However, in such a device, there is a problem that the amount of current taken out is small because the proportion of hot electrons generated by the avalanche effect that has energy higher than the vacuum level is small.

A second solid-state electron beam generator known in the prior art, as disclosed in Japanese Patent Publication No. 54-30274, has
p consisting of Al _x Ga _(1-x) P (0 ≦ x ≦ 1) on aP semiconductor substrate
An n-junction region is provided, and a forward voltage is applied to the pn-junction region to take out the electrons injected from the n-region to the p-region.

However, such a device has an advantage that the amount of carriers can be increased as compared with the case of the above-mentioned US patent, but on the other hand, since there is no region for forming hot electrons, electron emission into a vacuum is performed. Low efficiency, and
The GaP substrate has the defect that it has many crystal defects and cannot form a good pn junction region.

Further, US Pat. No. 3,119,947, which is known prior to the above-mentioned two prior arts, discloses a device in which an npn region is formed on a Si semiconductor substrate and a voltage is applied between both n-type regions to emit electrons. Is proposed. According to such an npn type device, the emission efficiency of the device described as the first prior art (device utilizing pn junction) is about 10 ^-6 , whereas the emission efficiency is improved to about 10 ^-4 . It is possible.

However, the p-type region and the n-type region on the electron emission surface side need to be as thin as 100Å and be evenly provided.
There was a problem that its fabrication was difficult and not realistic.

[Problems to be Solved by the Invention] Therefore, in view of the above points, an object of the present invention is to provide a solid-state electron beam generator which facilitates a manufacturing process with a simple structure and sufficiently enhances electron emission efficiency. To do.

[Means for Solving the Problems] In order to achieve such an object, in the present invention, a first region having a first band gap and a second region having a second band gap narrower than the first band gap are provided. When the heterojunction structure with the two regions is formed on the GaAs epitaxial film provided on the Si substrate, the graded layer in which the mixed crystal ratio of the predetermined material gradually changes in the thickness direction is defined as the first region. It is inserted between the second region and the first region to inject electrons into the second region, and at the same time, emits electrons from the electron emission surface of the second region.

[Operation] By growing an AlGaAs-based film on a Si substrate, electrons are injected from a first region having a wide bandgap into a second region having a narrow bandgap through a graded layer, and the electrons are injected into a second region. Emit directly from the edge of the area. Since the Si substrate has low thermal resistance, an electron beam generator with high current density can be realized. Further, it becomes easy to connect the Si integrated circuit and the electron beam generator.

[Examples] Hereinafter, the present invention will be described in detail based on Examples.

FIG. 1 is a sectional configuration diagram showing an embodiment of the present invention.

In this embodiment, MOCVD (Metalorganic Chem) is formed on the Si substrate 1.
AlP layer 2 and Al by using the ical vapor depositon method.
GaP layer 3 is grown, followed by GaP and GaAsP superlattice layer 4, GaA
A superlattice layer 5 of sP and GaAs is provided, and a GaAs layer 6 is grown thereon. Further, on the GaAs layer 6, an n ⁺ type GaAs layer 7, N type Al _x Ga
_(1-x) As layer 8 (0 <x ≦ 1) is grown. This N type Al _x
Oxygen is implanted into the Ga _(1-x) As layer 8 other than the electron beam generating region to form an inactive layer 9.

On the N-type Al _x Ga _(1-x) As layer 8, the mixed crystal ratio x of Al is gradually reduced and the grade (gradation) is continuously changed up to GaAs.
d) Form layer 20. Furthermore, on the gradient layer 20, p
A type GaAs layer 10 is provided. A work function lowering material 12 is diffused or attached to the surface of the p-type GaAs layer 10. p-type GaAs
An external acceleration electrode 15 is formed on the layer 10 via a SiO ₂ insulating layer 11. Further, electrodes 13 and 14 are formed on the n ⁺ type GaAs layer 7 and the p type GaAs layer 10, respectively.

The configuration described above will be described in more detail below.

Reference numeral 8 is an Al _x Ga _(1-x) As layer which acts as a carrier supply source. Here, x represents a mixed crystal ratio of Al, and has a value of 0 <x ≦ 1. Moreover, capital “N” represents an N-type region having a wide band gap. 9 is this N-type Al _x Ga _(1-x)
It is an inactive layer formed by implanting oxygen into the As layer.

10 is a p-type GaAs layer. Here, the lower case "p" represents a p-type region having a narrow band gap. In addition,
It is also possible to control the size of the band gap by adding Al instead of the p-type GaAs layer to form a p-type Al _z Ga _(1-z) As layer (0 ≦ z <x).

Further, 12 is a cesium oxide (Cs-O) layer adhered to or diffused on the surface of the layer 10, and acts as an electron emission surface. Instead of this Cs-O layer, an alkali metal such as Cs,
It is also possible to attach or diffuse a material containing at least one of Cu, Ag, Au, Sb, Bi, Se, As, Ag, P, Te, Si and O.

As the N-type semiconductor electrode 13, Au-Ge, Au-Ge-Ni, etc.,
As the p-type semiconductor electrode 14, Au-Sn, Ag-Zn, Au-Be, Au
-Zn or the like may be used. In FIG. 1, p-type GaAs layer 10
The electrode 14 of is directly formed on the surface of the p-type GaAs layer,
The electrode may be formed after the Be ⁺ ion is doped under the electrode formation portion to form the p ⁺ -type region. Alternatively, a p ⁺ -type GaAs layer may be grown on the surface of the p-type GaAs layer and an electrode may be formed thereon.

As described above, in the first embodiment of the present invention, Ga is formed on the Si substrate.
An epitaxial film of As-Al _x Ga _(1-x) As system is grown.

Next, the operating principle of this embodiment will be described with reference to the energy band diagram shown in FIG.

In Fig. 2, the solid line shows the energy level at thermal equilibrium [eV], and the broken line shows the energy level at bias application [eV].
V] is shown. In order to increase the carrier injection efficiency into the layer 10, the layer 8 is made of a wide bandgap material such as Al _x Ga _(1-x) As.
To use. In the present embodiment, the mixed crystal ratio x of Al is set to x = 0.3 in consideration of the effects of the L-band and the X-band in addition to obtaining a good heterojunction, but is limited to this value. It is not something that will be done.

Furthermore, the doping amount of the layer 8 is set to be high (5 × 10 ¹⁷ to 1 × 10 7
¹⁹ cm ^-3 ), so that it is injected into many carrier layers 8. With such a doping amount, a degenerate state occurs, and the Fermi level is located above the conduction band.

Since the graded layer 20 is inserted between the layers 8 and 10,
The mixed crystal ratio x of Al gradually decreases, and x = 0 at the boundary with the base layer 10. By inserting such a graded layer 20, spikes or the like do not occur at the hetero interface between the layers 8 and 10 as shown in FIG. As described above, since no barrier such as a spike is generated, many carriers are injected into the layer 10, and the injection efficiency is improved.

As the layer 10, a p-type GaAs layer which is a narrow band gap material is used. The doping amount of this layer 10 is 5 × to reduce the resistance.
The layer thickness is set to 10 ¹⁸ cm ⁻³ , and the film thickness of the layer is set to about 300 Å in order to reduce scattering in the region.

Since the cesium oxide Cs-O is diffused (or adhered) to the surface of the n-type GaAs layer 10, the work function of the surface of the layer 10 is as low as 1.4 eV. As mentioned earlier,
As this surface layer, {alkali metal such as Cs + (Sb, Bi,
Se, As, P, Te, Cu, Ag, Au, Si, O)} and the like can also be used.

A high quality and uniform film is formed on each of these layers by growing it using an MBE apparatus or a MOCVD apparatus.

Next, the state when a bias voltage is applied to this embodiment will be described (see the broken line in FIG. 2).

A forward bias voltage is applied between the electrodes 13 and 14,
Further, a positive bias voltage is applied to the external acceleration electrode 15 with respect to the electrode 14. Then, Cs-O diffused p-type GaAs
Has a work function of 1.4 eV, and p-type GaAs has an electron affinity of 4.0
Since it is 7 eV, the band of the p-type GaAs layer 10 bends downward near the surface as shown in FIG.

Since the p-type GaAs layer 10 is highly doped, the valence band and the Fermi level are almost the same. Moreover, the band gap of GaAs is 1.428 eV, which is larger than the work function of 1.4 eV of the Cs-O diffused layer. Therefore, N-type AlG
Low-energy carriers (electrons) injected from the aAs layer 8 into the p-type GaAs layer 10 fall into the valley V formed on the surface as shown in FIG.
The absolute amount of carriers injected into 10 becomes large, and the amount of current emitted becomes large.

When an external electric field is applied by the external accelerating electrode 15, the vacuum level bends as shown in FIG. 2, and the emitted electrons are further accelerated by this electric field.

FIG. 3 is a sectional configuration diagram showing a second embodiment using a Si substrate. In this second embodiment, an element similar to that of the first embodiment shown in FIG. 1 is manufactured by the ion implantation technique.

In FIG. 3, 30 is a Si substrate, 32 is an AlP layer, and 34 is AlGaP.
The layer, 36 is a GaP and GaAsP superlattice layer, 38 is a GaAsP and GaAs superlattice layer, and 40 is a GaAs layer. The layer structure of each of these layers is the same as the layer structure of the first embodiment shown in FIG.

42 is n ⁺ type GaAs for obtaining ohmic contact with the electrode 44
Layer, 46 is an N-type Al _x Ga _(1-x) As (0 <x ≦ 1) layer, 48 is a layer 46
The gradient layer in which the mixed crystal ratio of Al is gradually decreased with increasing distance from 50, 50 is a p-type GaAs layer, and 58 is for decreasing the work function.
It is a layer obtained by diffusing (or adhering) Cs-O or the like. Further, 66 is a bias voltage applying electrode, and 62 is an external accelerating electrode.

Furthermore, Be ⁺ was ion-implanted into the p-type GaAs electrode formation portion to form p ⁺
A region 68 in which B is ion-implanted is formed for insulation between the mold region 64 and the layers 46 and 50 and isolation between elements. Then Si
The O ₂ protective layer 60 is formed, and the external acceleration electrode 62 and the electrode 66 are manufactured. Regarding the electrode 44, a hole is dug to reach the n ⁺ type GaAs layer 42, and an electrode of Au-Ge / Au or the like is formed therein.

Finally, Cs-O is diffused (or attached) to form the layer 58, and the fabrication of this example is completed. The second embodiment differs from the first embodiment described above in that it does not require a difficult process such as etching and has the advantage that the element surface becomes flat.

The operation principle and the like of the second embodiment are the same as those of the first embodiment, and therefore the description thereof is omitted.

In this way, by adopting the planar type device configuration, it is possible to appropriately deal with so-called multi-processing in which a plurality of devices are arranged on the same plane.

Although the first and second embodiments described above use the buffer layer using the superlattice layer, the ultrathin buffer layer grown at low temperature on the Si substrate is used. (GaAs / GaAs buffer layer (<200Å)
/ Si type).

[Effects of the Invention] As described in detail above, according to the present invention, the effects listed below can be obtained.

Since the band gaps between the two compound semiconductors are different from each other and the graded layer is interposed between the two semiconductors, the amount of carriers injected from one compound semiconductor into the other compound semiconductor increases.

As a result, the electron emission amount is significantly improved.

Since the emitter region and the base region can be formed as an epitaxial film of about several tens of liters using an MBE device or a MOCVD device, a high quality and uniform layer structure can be easily formed.

Moreover, since the thickness of each layer can be reduced, the driving voltage can be reduced.

Since Si having low thermal resistance can be used as the substrate, the problem of heat generation can be reduced.

Since an electron beam generator (device) can be manufactured using a Si substrate, it is easy to arrange a plurality of electron beam generators on the same substrate and to combine them with devices having other functions. . As a result, it is possible to increase the degree of integration of semiconductor devices.

 Since the film structure is simple, it is easy to manufacture.

Further, according to the embodiments of the present invention, the following effects can be obtained in addition to the effects of the above invention.

When the present invention is implemented using the ion implantation technique,
It is possible to increase the degree of integration by eliminating processes such as etching, flattening the surface of the device, and forming other devices on the same substrate.

[Brief description of drawings]

FIG. 1 is a sectional configuration diagram showing a first embodiment of the present invention, FIG. 2 is an energy band diagram showing an energy state of the first embodiment, and FIG. 3 is a sectional configuration showing a second embodiment of the present invention. It is a figure. 1 ... Si substrate, 2 ... AlP layer 3 ... AlGaP layer, 4 ... GaP / GaAsP superlattice layer, 5 ... GaAsP / GaAs superlattice layer, 6 ... GaAs layer, 7 ... n ⁺ type GaAs Layer, 8 ... N-type Al _x Ga _(1-x) As layer, 9 ... N-type Al _x Ga _(1-x) As oxygen injection inactive layer, 10 ... p-type GaAs layer, 12 ... Cs -O diffusion layer, 20 ... Gradient layer.

Claims (5)

[Claims] 1. A GaAs epitaxial having a heterojunction structure of a first region having a first band gap and a second region having a second band gap narrower than the first band gap provided on a Si substrate. When formed on the film, a graded layer in which a mixed crystal ratio of a predetermined material gradually changes in the thickness direction is inserted between the first region and the second region, A solid-state electron beam generator characterized in that electrons are injected into the second region and the electrons are emitted from the electron emission surface of the second region. 2. An N-type Al _x Ga.sub. _(1-z) As layer (where 0 <x ≦ 1) having a first band gap is formed on a Si substrate to form the first region, and a second region is formed. The p-type Al _z Ga _(1-z) As layer (where 0 ≦ z <x) having a bandgap of 2 is formed as the second region. Solid-state electron beam generator. 3. The solid-state electron beam generator according to claim 1, wherein a material having an alkali metal component is diffused or attached to the electron emission surface of the second region. 4. The solid electron beam according to claim 2, wherein a layer in which the mixed crystal ratio x of Al _x Ga _(1-x) As is gradually changed is used as the gradient layer. Generator. 5. The N-type Al _x Ga.sub. _(1-x) As layer (where 0 <x
The solid-state electron beam generator according to claim 2, wherein oxygen is injected into a predetermined region of ≦ 1) to form an inactive region.