JPH07111177A - High density lamination type connector and manufacture thereof - Google Patents

Abstract

PURPOSE:To form electric connection parts such as bumps, and traces (electricity passages for mutual connection in a connector at high density for the connector for performing transmission of power or electric signals between multiple chip modules or printed circuit boards and its manufacturing method. CONSTITUTION:A specified number of trances 108, 110 are formed through a connector main body 114 comprising plural dielectric layers 115 laminated on each other in such a way that first and second terminal parts of the traces are exposed through a first and a second surfaces (those selected among 503-506)of the connector main body 114. In addition, bumps 512, 512' are formed on the first and the second terminal parts of the traces by plating conductive material on each terminal part.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention generally provides mutual transfer of power or electrical signals between a predetermined number of multi-chip modules (MCMs), a predetermined number of circuit boards (eg, printed circuit boards), and the like. It relates to the configuration of the interconnects used for the purpose.
In particular, the present invention relates to an electrical connector used to mutually transfer electrical signals between the predetermined number of multi-chip modules, the predetermined number of circuit boards, etc., and to form such an electrical connector. And various manufacturing methods thereof.

[0002]

2. Description of the Related Art A medium-sized and high-performance computer system is composed of hundreds to thousands of integrated circuit (IC) chips, and various forms are used for interconnecting the chips. To be done. These systems also have
For example, a predetermined number of circuit boards of various types to be interconnected with each other, such as a printed circuit board or a card on which a printed circuit is wired, and a multi-chip module composed of these are interconnected. And a circuit board for use.

The first interconnection (interconn)
ect approach), a predetermined number of ICs
The chips are packaged in individual carriers, and each IC package has a predetermined printed circuit board (PC).
B) distributed in a predetermined distribution on a large number (predetermined number) of cards, each of which interconnects between said respective card and a main printed circuit board to be interconnected. Through the connector, a so-called "plug connection" is made to the main printed circuit board (PCB). Each card having the above-mentioned printed circuit board (PCB) has a predetermined number of traces (electrical paths) or electric paths (lines) for interconnection, and each of the traces or electric paths passes through each of the IC chips. To transmit a predetermined electric power (or electric signal) to each IC chip on each card, or to transfer a predetermined electric signal between each IC chip and the main printed circuit board. To do. The connectors that interconnect between each of the cards and the main printed circuit board are conventional blade-like leaf-s.
a connector having a printing tab), a connector that does not require insertion force (zero insertion force (ZIF) connector), or a connector made of a conductive elastic body that is inserted between circuit elements in a compressed state. Can be configured. As an alternative, the connector may be omitted, in which case the traces provided on each of the cards with the PCBs described above would have corresponding counterparts formed on the main printed circuit board. Each trace is formed so that it can be directly soldered.

In the second interconnection form, each of the above I
C chips are distributed and arranged in a predetermined distribution state on a predetermined number of multi-chip modules, and each IC chip is directly mounted on each multi-chip module without packaging individual chips. . In this case, each such module is plugged onto the main printed circuit board to be interconnected to form a two-dimensional array with respect to another predetermined number of multi-chip modules. To do. Each said multi-chip module
A predetermined number of integrated circuits (I
C) is composed of an interconnection substrate having a chip. A number of interconnect traces are formed in the substrate of each module. There can be thousands or more of these interconnect traces within a module. A part of each of the traces transfers power to the IC chip mounted on the module, while another part of each of the traces has a predetermined inter-IC chip compatibility. Transfers electrical signals of. Further, each other of the traces transfers a predetermined electrical signal to a predetermined number of other modules, or an input signal to the computer system via the main interconnect printed circuit board. An output signal (that is, an I / O signal) or the like from the computer system is transferred (that is, the I / O signal is input / output). In general, such electrical signals are much greater in each of the multichip modules than in the main interconnect printed circuit board or each of the cards with the PCB used in the first interconnect configuration. Propagates at high speeds.

Furthermore, in the third interconnection form, a predetermined number of individually packaged IC chips are distributed in a predetermined distribution state on each card similar to a card having a predetermined number of the above-mentioned PCBs. Each of the placed and similar cards with the above PCBs are stacked on top of each other to form a three-dimensional chip array. Power is supplied through one side of the three-dimensional chip array, and the input / output signals (I / O signals) to / from the computer system are transferred through the other side of the chip array. To be done. Many inter-layer interconnects
the stacked PCBs
In order to perform mutual transfer of electric signals between a predetermined number of card groups constituting the card including the card, the card groups are provided so as to extend in the vertical direction with respect to the card groups which are adjacent to each other. At present, the focus is on investigating how such an interconnection configuration can be applied to the multi-chip module.

Compared to the case of a personal computer or a workstation, in the high performance computer system using the above-mentioned interconnection form, the above-mentioned PCB is used.
It is necessary to provide a relatively large number of signal connections between the card or multi-chip module with the main printed circuit board described above. For example, as a typical example, in the current products, there are approximately 1,800 or more signal connecting portions for one printed circuit board or multi-chip module.
In order to reduce the transfer time of electrical signals and further increase the calculation speed, the industry is currently increasing the number of signal connections mentioned above far from the current level, as well as the above mentioned cards and printed circuit boards and There is a tendency to reduce the size of the module. In order to satisfy all of these tendencies, the density of the signal connection is required to be increased much more than it is now. For the next generation high performance computer, the density of the signal connection for a two-dimensional multi-chip module, there are currently 30 to 60 signal connection per square centimeter at the interconnection surface of the module. It is considered that the density must be increased to 2 to 4 times the density at the technical level of. Of course, as the density of the signal connections increases, each signal connection itself must have more precise dimensions and also be properly aligned with the corresponding signal connection. In addition, the predetermined number of modules and cards and printed circuit boards described above must also be made to have more precise dimensions and be more properly aligned (aligned) with the mating circuit elements. There is a need. Due to economic considerations, the increased density of the signal connections must be achieved without substantially increasing manufacturing cost or manufacturing complexity. The reason is that increasing the manufacturing complexity may adversely affect the production value of the above-mentioned modules, cards, printed circuit boards, connectors and the like.

However, there are several obstacles that prevent the increased density of the signal connections, the greater accuracy of the dimensions of the signal connections, and the more correct alignment of the signal connections from being achieved. (Issue) Each trace (electrical path) formed through many multi-chip modules, cards, printed circuit boards and connectors now has a relatively narrow trace width relative to the length of the trace, and thus A high aspect ratio as the aspect ratio, referred to below, defined as the ratio of the length of a trace (in other words the height H of the trace) to the average value W of the trace width, ie H / W. have. In this case, each of the traces is, as a typical example, punching, drilling, or molding (mo).
Led), in each case,
A hole forming tool is used which has a relatively narrow width relative to its length. Here, in order to increase the density of the signal connection portion, it is required to reduce the trace width. However, even if the trace width is reduced, the length of the trace is reduced to the same extent as the reduction of the trace width. Only for those traces where the power is not reduced will a high aspect ratio be provided. However, in the conventional technique, in the above-described case, it is more difficult to form the traces so that the aspect ratio is increased, as compared with the normal case. The reason is that when the aspect ratio is increased by using the hole forming tool in the case as described above, the tool is not used during the formation process of the hole during the process of forming the hole as compared with the normal case. It is easier to deflect more from the forming path, and it is easy to cause misalignment such as dimensional error when aligning each trace, and for example, it is easy to melt together at the place where each trace is adjacent to each other. This is because the so-called merging easily occurs, and further, the tool is easily damaged in the card, the printed circuit board or the module. Therefore, in the case as described above, in the conventional connector obtained by the above-mentioned prior art, the aspect ratio obtained by the predetermined number of the formed traces is, as a typical example, approximately 20 or less. You will be limited to values.

Further, in the case where a predetermined number of connectors for interconnecting the card and the main printed circuit board are used to connect various circuit elements, the signal connection portion is As the density simply increases, it becomes more difficult to manufacture each connector with the correct dimensions and to connect each connector with a predetermined number of circuit elements corresponding to each connector. The reason is,
This is because the size of electrical connection parts (for example, various blade-shaped springs (various leaf springs) and various pins) forming the connector is reduced.
Furthermore, the above connectors are aligned with each other.
It is even more difficult to make it happen. The reason for this is that many of these connectors are not rigid enough and therefore have components for interconnections that could move easily (such as the tabs on the leaf springs or resilient connectors, etc.). Because it has. Such movement is caused by vibration, contact pressure, stress caused by thermal expansion or thermal contraction, etc. when aligning the other printed circuit board, especially in a rubber elastic connector, etc. Over time, this can result in incorrect placement. In this way, some connectors in the prior art are required to maintain, simply speaking, the sufficiently precise dimensional accuracy required to form the signal connections in high density. It lacks rigidity.

[0009]

Accordingly, various interconnect circuit boards such as those described above (eg, the interconnect substrates such as the cards, printed circuit boards, and circuit boards for the modules described above).
ate), each trace is exactly interconnected (in
to ensure that they are
It is necessary to provide a connector that has precise dimensions and that each trace is accurately located. for that reason,
There is a need for a connector that is formed without a complicated or costly manufacturing process and that has a predetermined number of traces to have a high aspect ratio.
Furthermore, a connector for interconnecting the card and the printed circuit board, a connector for interconnecting the plurality of printed circuit boards, and a printed circuit board for the main multi-chip module to be interconnected. It is extremely useful if, for example, a device that can be used in various circuit connection systems, especially a device that can easily change the circuit configuration is obtained.

[0010]

The present invention has been made in order to solve the various problems described above, and forms the predetermined number of traces in a high density so as to obtain a high aspect ratio. Solid array, which can be used as a connector to an interconnecting circuit board (for example, a card or board composed of a printed circuit board (PCB), or a circuit board for a multi-chip module). Form connector. The solid array type connector further has a predetermined number of rigid traces formed as a connector for interlayer connection in a three-dimensional array composed of a large number of IC chips, or has a very high aspect ratio, and It may be used for other predetermined applications where the end of each trace (eg, the contact for electrical connection) is required to be accurately positioned. The present invention further provides a method of manufacturing such a solid array type connector relatively easily and inexpensively.

Briefly, the connector of the present invention comprises a plurality of precisely formed dielectric layers of dielectric material that are integrally laminated to form a block for connection. In the connecting block, the exposed surfaces of the uppermost and lowermost dielectric layers of the laminated dielectric layers are the top surface and the bottom surface, respectively,
Each edge surface formed by the plurality of stacked dielectric layers serves as a predetermined number of side surfaces. In one embodiment, the block has four side surfaces and has a total of six surfaces including the top surface and the bottom surface, and has a so-called parallel pipe (parallelogram type pipe) shape. Has been done. A predetermined number of traces (electrical paths) are formed on the desired selected predetermined number of dielectric layers of the stacked dielectric layers. In one embodiment, one or more traces are formed on each dielectric layer. In a preferred embodiment of the present invention, a predetermined rigidity is provided to maintain accurate dimensional accuracy while at the same time minimizing tolerances and allowing accurate positioning of pressure contacts (such as bumps). A dielectric material having is used.

Each of the traces may be formed in different widths and in different directions. In one embodiment of the invention, each trace is accurately imaged on the laminated dielectric layer by performing silk screening with a metal paste.
In another embodiment of the invention, a predetermined number of channels are etched in each dielectric layer using photolithographic techniques, and then a predetermined conductor is sputtered in each channel. After the stack of dielectric layers is made, the block (connector block) is precisely cut along at least two different planes to expose each end of each trace. ) Will be done. Each of the traces should be interconnected, eg, main, using electrical contacts (eg, contacts such as bumps) made of gold (eg, soft gold), solder material, or some electrically conductive elastic material. Circuit board or other connector. Each of the contact portions is formed so as to be located on each of trace end portions (trace terminal portions) formed on a predetermined surface of the connector that is precisely cut, and as the surface, all the contact portions of the connector are formed. Surfaces (eg, 6 surfaces in the parallel pipe-shaped connector block) may be included. A predetermined number of traces and cross traces formed within the stacked dielectric layers (i.e., on a predetermined one stacking surface of the stacked dielectric layers) have predetermined side surfaces of the connector. To allow the electrical connection to be made, and for example, to interconnect each trace between the given side surfaces of the two connectors. In addition, a predetermined number of vias (electrical paths) formed so as to traverse the laminated dielectric layers (that is, extend between a plurality of dielectric layers adjacent to each other) are electrically connected at the top and bottom surfaces of the connector. To be done,
Further, for example, an electric path is formed between the top surface or the bottom surface of one connector and a predetermined side surface of the other connector, or a predetermined dielectric layer is formed on each surface of different dielectric layers forming one connector. Allows interconnections to be made between traces.

In still another embodiment of the present invention, the connector is provided on a predetermined surface of the connector at each end of each trace on which a pad (contact pad) for electrical contact is formed. A recess is formed to accommodate the pad. By providing such a recess, a mechanically strong connection is made between the connector and a circuit board to be interconnected with the connector (for example, a printed circuit board, a card, and a circuit board for the module). Guarantee that Since the dimensional tolerance of the joining surface formed on the connector can be reduced (that is, the joining surface can be formed with high accuracy),
With respect to the connector, it is possible to accurately position another circuit board to be interconnected adjacent to the connector. The aspect ratio can be substantially increased because a predetermined number of narrow traces can be formed on each of the individual dielectric layers in the desired manner as described above.

In the present invention, the end portions of each trace can be arranged and formed very close to each other, so that the size of each contact pad and each bump and / or each pad or The distance between the bumps can be made relatively small. However, the type using well-known photolithographic technology and pattern transfer technology, which is said to be capable of easily forming a fine contact pattern, is designed to perform processing on a thin wafer. It is not specifically designed to handle the solid array type connectors which may have very different shapes. Therefore, the present invention further provides a novel method for forming the contact pads and the bumps on the end portions of the traces without using such photolithographic or pattern transfer processing or equipment therefor. Will be provided.

A general description of such a method of the present invention will now be given, wherein each of the traces formed on two or more desired selected respective surfaces of the solid array connector. A conductive material is, for example, electrically plated on each end, thereby forming each conductive bump (contact bump) for electrical contact with high dimensional accuracy on each end. Then, in a preferred method of the present invention, one or more desired selected surfaces are deposited on each of the one or more desired surfaces, for example by electroplating or dipping in a bath in which a metallic material such as a soldering material is melted. A layer of a solder material or a flexible conductive material is formed over each contact bump formed.
If the layers here require different layer materials to be formed on different faces, a cover mask can be applied selectively on each of the faces. By the method as described above, desired contact pads and contact bumps are
The above photolithography technology and pattern transfer process,
Alternatively, it can be easily manufactured without requiring various steps that require precise alignment. Further, the method as described above can be applied not only to the solid array type connector according to the present invention as described above, but also to other types of connectors as well.

Accordingly, one object of the present invention is to
For example, multi-chip module, printed circuit board (P
For very high density electrical connections and very high density interconnections within a certain number of connectors to circuit boards to be interconnected with each other, such as a card made of CB) or a board made of PCB. It is to allow traces to be formed.

Another object of the present invention is to make it possible to form the traces so that a substantially unlimited high aspect ratio can be obtained. Yet another object of the present invention is to facilitate the formation of the electrical connection in each of the connectors, for example via orthogonally angled traces.

Still another object of the present invention is to provide a connector which can maintain its dimensional accuracy accurately even when various forces or stresses are applied. Still another object of the present invention is to provide each of the connectors, which can be easily removed from the circuit board interconnected with each of the connectors, whereby the circuit configuration and the like can be easily reconfigured. It is in.

Still another object of the present invention is to obtain various performances as described above without substantially increasing manufacturing complexity or manufacturing cost. Yet another object of the present invention is to provide a predetermined number of contact pads on each end of each trace formed in the connector without the use of photolithographic steps or various pattern transfer processing steps as described above. It is to provide a method for forming a bump.

Still another object of the present invention is to provide a method of forming contact pads and bumps as described above on a connector having a small size. Various objects of the present invention as described above and other objects will be easily understood by those skilled in the art by referring to the description of the specification and the accompanying drawings below, and the description of the claims. It is clear that

[0021]

1 is a partial plan view of a connector 100 configured as a stacked solid state array (i.e., when taken along line 7-7 of FIG. 5) according to one embodiment of the present invention. It is a partial plan view of one laminated surface). Referring to FIG. 1, as a typical example thereof, three circuit boards 102, 10 to be interconnected are provided so as to face the respective surfaces of the connector 100 shown.
4 and 106 are attached to the laminated connector 100. However, since the total length of the connector is not shown here, the right end portion of the laminated connector cannot be seen.

The laminated connector 100 is composed of multiple layers of rigid dielectric material including a predetermined number of traces (electrical paths) 108. In one embodiment, the dielectric material comprises a glass ceramic material. In another embodiment, borosilicate glass is used as the dielectric material. The relative dielectric constant with respect to the glass ceramic in the one embodiment of the present invention is, for example, less than 5.7,
The relative dielectric constant with respect to the above borosilicate glass is, for example, 5
Is less than. Thus, it is preferable to use a dielectric material having a relative dielectric constant of less than 7, for example.

As shown in FIG. 1, the traces (electrical paths) 108 are arranged in parallel with each other and have uniform dimensions. However, in other embodiments, the traces (electrical paths) may be located in different directions and each trace may have different dimensions. Further, as shown in FIG. 1, traces (electrical paths) 110 are provided at right angles to the respective traces 108, and a predetermined number of traces can be positioned at various positions in this way. It is shown. Thus, the present invention allows for straight line interconnections through the connector, as well as orthogonal interconnections through the connector.

Each of the above traces can be manufactured to a narrow width by utilizing the present invention. In one embodiment, the width of the traces is approximately 0.075 millimeters and this width is mechanically drilled.
The width is even narrower than that normally obtained by carrying out g). Thus, prior to stacking the plurality of dielectric layers, the predetermined number of traces are added on each individual dielectric layer to provide a high aspect ratio (length of the trace 108 (in other words, dielectric A value obtained by dividing the layer height H) by the trace width W, ie H / W), can be achieved. In one embodiment, an aspect ratio of, for example, 26 may be achieved. However, such aspect ratios should not be limited, and in practical embodiments, aspect ratios of, for example, 40 or more are feasible.

In each trace (electrical path) 108,
Contact pads (contact pads) 1 at each end
12 is formed. The contact pads 112, which are generally oval shaped and wider than the traces, connect the stacked connector 100 to the circuit boards 102, 104 and 106 to be interconnected. Intra-layer connections between multiple (eg, two) traces (ie, electrical connections between the traces on one stacking surface of the stacked connector) provide cross traces (in-layer connections above). Electrical path) 109 for 1, 3 and 4 (where FIG. 3 is a partial plan view similar to FIG. 1 above, while FIG. 4 shows the laminated connector 100 longitudinally cut in its laminating direction (ie FIG. 5). 6 is a partial vertical sectional view (longitudinal section taken along line 6-6 of FIG. 6), each contact pad is made of soft gold. In this case, pressure is applied to the circuit board and the circuit board is pressed against the connector 100 to complete electrical connection between the circuit board and the connector. In one embodiment of the present invention, the circuit board 104 is a screw 1
16 is used, the laminated connector 100
Is attached to. By removing the screw 116, the pressure applied on the circuit board 104 is removed. Making the circuit board easily removable is advantageous when the circuit board must be repositioned or removed for testing.

In another embodiment, the connector 10
The electrical connections on one or more sides of 0 are made of solder. The solder electrically connects the connector to one of the circuit boards. A mechanical or solder connection is used for the circuit board that is attached to yet another side of the connector. It is possible to use two different solder materials to attach another circuit board to the connector. In this way it is possible to remove only one circuit board using a single temperature in order to melt only one solder connection. Therefore, in these embodiments, in order to test the one circuit board or change the circuit configuration of the one circuit board while the attachment state of the connector to other circuit boards is maintained. Only one circuit board can be easily removed.

FIG. 2 is a perspective view showing the structure of the connector block 200 used in the present invention, from which one or more connectors 100 can be produced. The connector block 20
0 is made up of a plurality of planar layers of laminated rigid dielectric material 114. In one embodiment, the connector block 200 may be manufactured by laminating a plurality (ie, multiple layers) of ceramic green sheets. This green sheet should be wet-ground with a fine-grained reactive oxide in a ball mill filled with a deflocculant, binder, plasticizer, lubricant, grain growth inhibitor, and organic solvent. Formed by. The slurry formed in this way is spread on a carrier film of polyester or on cellulose acetate. The film and slurry move at a constant velocity under a metal knife so that a thin sheet of wet glass-ceramic is formed. The glass ceramic sheet is air dried to remove the solvent. The sheet is then cleaned to provide a smooth surface for printing purposes and to remove particles that would cause circuit interruptions.

The traces 108 are precisely formed by coating the green sheet with copper paste or ink and are converted to conductors after firing the green sheet. A resistor paste or other metal can also be applied to the dielectric layer before or after firing. Next, the green sheets are stacked on top of each other and the green sheets are attached to each other by a hot isostatic pressing press. Sufficient pressure is applied on the layers of greensheet to provide a single layered block. The laminated block is then placed in a sintering oven for firing at about 300 ° C to 600 ° C to remove organic binders, lubricants, plasticizers and peptizers.

Thereafter, the green sheets are co-fired at a higher temperature such as about 1000 ° C. in a nitrogen atmosphere. Thus, the sintering of the glass ceramic and the metallization of copper are simultaneously brought about. In other embodiments, the layer of dielectric in the connector block comprises sapphire, glass, silicon, gallium arsenide (GaAs) or quartz. The slab, such as sapphire or glass, that will make up the dielectric layer of the connector block is precision ground and lapped to achieve the desired tolerances for surface parallelism, flatness and finish. For each dielectric layer that will have the predetermined number of traces, photoresist material is applied (eg, coated) onto the finished surface of the dielectric layer. In one embodiment of the invention, only one surface of the dielectric layer is coated. However, in other embodiments of the invention, both surfaces of the dielectric layer may be coated and processed for additional signal density.

The photoresist is cured and the predetermined number of traces are delineated, and a pattern is created for etching the dielectric layer using the standard photolithographic technique to develop the photoresist. Produced. The grooves corresponding to the traces described above are then formed by etching the dielectric with a suitable etchant.

After performing the etch, the photoresist used in the trace delineation process is stripped to leave a clean surface on the dielectric layer. Then, a metal for forming the trace is plated or sputtered on the dielectric layer, and subsequently, the plated dielectric layer is subjected to a photolithography process (photolithographic process) and an etching process. Metal-filled trenches are created in the dielectric layer. Multiple dielectric layers are precisely centered and voided to form the connector block, as shown in FIG. In the preferred embodiment, the plurality of dielectric layers are composed of glass and diffusion bonded.
The application of heat and pressure to the stacked dielectric layers causes the dielectric layers to be bonded together. 500 ° C. to 600 ° C. by performing the desired diffusion bonding process on the silicon dielectric.
Conditioning of the surface of the laminated body is performed by using sulfuric acid sulfuric acid while heating the laminated body to the temperature of 0 ° C. and applying pressure. In other embodiments, standard adhesives can be used, but in this case there is poor dimensional control, which can result in thickness variations in the bonded layers.

The above connector is the laminated connector
It is cut with precise dimensions from the connector block by precisely sawing the block, and then each surface of the connector is polished.
g) and lapping.
The connector block is cut along the horizontal plane 204. In this case, the horizontal plane 204 is normally a plane perpendicular to the surfaces of the dielectric layer (both surfaces facing each other), and exposes the traces 108 provided in the laminated connector 100. Using a rigid dielectric material to cut and lap each individual layer of the dielectric material and the laminated connector 100 to extremely precise dimensions using various existing processes. You can That is, the tolerance can be about ¼ of the wavelength of light (eg, about 125 nanometers). In one embodiment, the height of the connector is about 2 millimeters. The thickness of each individual layer is, for example, about 0.16 mm.

FIG. 3 is a partial plan view of the connector according to another embodiment of the present invention. In this embodiment, each contact pad 112 has a recess (recess) formed in the dielectric material 114. Place). Each mating surface of the connector around each recess is precision machined to reduce tolerances in electrical connections. The dielectric material 114 has a cylindrical recess 3
14 are provided, and the contact pads 112 are arranged in the recesses 314. Although not shown in FIG.
The circuit board 104 to be interconnected is mounted on the connector with screws, whereby each contact pad 1
Force 12 to ensure that the circuit board is electrically connected to the connector. The screw extends through an opening formed in the circuit board into a threaded hole formed in the connector, as in the embodiment shown in FIG. 1 above. Other mechanical attachment means may also be utilized. By precisely controlling the depth of each recess, the amount of compression of each contact pad can be limited. Therefore, a strong mechanical connection can be maintained between the circuit board and the connector, whereby
Accurate dimensional accuracy can be maintained even when thermal stress occurs. By precisely machining each of the recesses, and the compression amount for each of the contact pads can be kept within its elastic limit, thereby making the contact pad more reliable and elastic. Is guaranteed.

FIG. 4 (the connector 100 as described above)
Is a partial vertical cross-sectional view taken along the stacking direction) in which a trace 108 provided on one layer of the plurality of dielectric layers is provided on another layer of the dielectric layer. A via (i.e., for making the interconnection) formed inside the connector to extend between adjacent layers of the connector for interconnection with another provided trace 108. (Electrical path) 402 is shown. The Figure 4 also extends from one trace 108 provided in the dielectric body (ie, the connector) to the top (or bottom) 404 of the connector 100 through the end layers of the dielectric layer. 2 shows a via (electrical path) 400 formed inside the connector. The via 400 has contact pads 412 for interfacing (electrically connecting) one of the circuit boards with the connector. To be joined. These vias 400 and 402 (ie each electrical path as described above)
Is formed so as to be generally orthogonal to the surfaces of the plurality of laminated dielectric layers, as shown in FIG. However, in the present invention, the orientation of the vias 400 and 402 is not necessarily limited to only the orthogonal directions as described above, and the vias 400 and 402 are preferably arranged with respect to the surface of each dielectric layer. Can be formed at any angle.
In one embodiment in which glass is used as the dielectric layer, the vias are formed by laser drilling holes in the dielectric layer and then plating metal in the holes. To be done. In another embodiment using a green sheet as the dielectric layer,
In each of the vias, a predetermined hole is formed in a predetermined dielectric layer by laser cutting (laser cutting), punching (punching), drilling, or the like, and then, during the laminating process performed in advance as described above, The conductive material is formed into a paste through the holes. Furthermore, other suitable processes, such as using photolithography techniques, may also be used as a means of forming the vias.

As shown in FIG. 3 above, the traces provided in each layer of the stacked connectors have electrical connections (ie, terminations of the traces) on predetermined surfaces of the connector. Can be formed. According to the present invention, as shown in FIG. 4 above, by providing each of the vias 400 and 402,
Providing interconnections between predetermined traces provided in adjacent dielectric layers of the connector and electrical connections on the top and bottom surfaces of the connector parallel to the laminated dielectric layers. Thus, the connector according to the present invention having such respective vias 400 and 402 is superior to the connector according to the prior art. Thus, in one embodiment according to the invention, a hexahedral connector can be used to interconnect up to six circuit boards.

FIG. 5 is a perspective view of a connector 500 as still another embodiment of the present invention. 6 and 7
5 is a longitudinal sectional view of the connector 500 taken along the line 6-6 in FIG. 5 in the stacking direction, and appears when the connector 500 is crossed along the line 7-7 in FIG. 5, respectively. FIG. 7 is a plan view of one stacking surface of the connector 500. The connector 500 comprises a body 114 made of a rigid dielectric material composed of a plurality of laminated dielectric layers 115. The connector 500 has a top surface 5
01, the bottom surface 502, and the four side surfaces 503 to 506.
Have. The terms top and bottom are referred to in FIG.
Irrespective of the orientation as shown in FIG. 2B, rather, it is named by the orientation of the dielectric layer 115 during the lamination process.

As shown in FIGS. 6 and 7, the connector 500 has a predetermined number of traces (electrical paths) arranged and formed between the plurality of dielectric layers 115, respectively.
108, a predetermined number of electrical connection bumps 512 formed on each end of a given trace 108 exposed on a side surface 505 of the connector 500, and a predetermined number exposed on another side surface 506 of the connector. A predetermined number of electrical connection bumps 512 ′ formed at each end of each trace 108 of
Etc. Each of the traces 108 is made of a conductive material, and in one specific example, each of the traces 1 is
08 is made of copper. Each of the bumps 512 and 51
Each 2'is comprised of an inner portion 513 and 513 'and an outer layer 514 and 514' formed to cover the respective inner portion. Each of the inner portions 513 and 5
Each of the traces 13 'is made of a conductive material having a relatively high rigidity, and the conductive material is used for the traces 108.
It is designed to adhere well to each end of the. In one embodiment of the connector 500, each inner portion 513 and 513 'is made of copper. In the preferred embodiment, each of the bumps 512 and 512 'is in the form of a fully spherical segment, the height to diameter ratio of the base of which is greater than 0.25. . Here, the above-mentioned sufficiently spherical segment means the base of the sphere when seen by the portion of the sphere enclosed by the first plane that intersects the sphere and the second plane that is parallel to the first plane. Is defined as the ratio of the height to the diameter of the tangent, that is, the tangent value (in summary, it can be regarded as a plano-convex volume or a hemispherical volume). In a preferred embodiment, each bump 51
2 and 512 'are formed in a substantially hemispherical shape, and the ratio of the height to the diameter of the base is approximately 0.5.
It is said that

Each outer layer 514 and 514 'is preferably constructed of a soldering material and / or a flexible conductive material (eg, soft gold). The flexible conductive material described above is used to make pressure connections to make electrical connections to bumps on a circuit board.
e contact), while the soldering material is such that each bump of soldering material corresponds to a corresponding pad on the circuit board or a soldering material on the circuit board. It is used when it is welded to a bump. In one embodiment, each outer layer 514 formed on the side surface 505 is composed of the flexible electrically conductive material to provide the pressure connection, while each outer layer 514 formed on the side surface 506. ′
Is composed of the above soldering material. In another example,
Both outer layers 514 and 514 'are comprised of the flexible conductive material, or both outer layers 514 are
And 514 'are composed of the soldering material.

As shown in FIG. 7, the connector 500 further includes a predetermined number of traces (electrical paths) 110 that are bent in a predetermined direction (for example, bent in a right angle direction). Also at each end of 110
Bumps (contact bumps) 512 for electrical connection are formed. The traces bent in such a predetermined direction allow the side surfaces 505 and 506 to be separated from the other side surfaces 503.
And electrical connections to 504 are enabled. The connector 500 is also shown in FIG.
It may be configured to have a via (electrical path) similar to that indicated by reference numeral 400 in FIG.

Multi-chip module (MCM), PC
A B card, a PCB board, or any combination thereof can be attached to the connector 500 so that the requirements of each application can be satisfied depending on what purpose the connector 500 is used. Can be connected). These components (ie, for example, the circuit board described above) are provided by means such as those described above (eg, the screw 1 described above).
16 and solder joints)
Can be attached to.

In one embodiment according to the present invention, the body 114 of dielectric material comprises a plurality of sheets of sapphire having a thickness of approximately 200 micrometers (ie, a plurality of dielectric layers 11 having the above thickness).
5). The traces 108 and 110 are formed on each dielectric layer 115 by etching a predetermined trench in each dielectric layer 115 using standard photolithography and etching techniques. Is formed. The above-mentioned groove (trench) is
As a typical example, the groove width is, for example, 10 micrometers, the depth is, for example, 10 micrometers, and the distance between the grooves is, for example, 150 micrometers. First, a seed layer for plating is sputtered, and then the seed layer is removed from all regions except each groove portion by standard photolithography and etching processes, and then a conductive material is filled in each groove, for example. By plating non-electrically,
A metal portion (ie corresponding to each trace) is formed in each groove. The plating metal is preferably comprised of copper, but may be comprised of other suitable materials such as platinum, molybdenum, or tungsten. Other standard metallization techniques, such as the formation of metallization (metallization lift-off) or electrolytic plating on the seed layer remaining due to the above etching steps. Metallization techniques can be used.

After metallizing the trenches, the sheets (that is, the dielectric layers 115) are deposited.
Is a chemical or mechanical lapping
Smoothed by. FIG. 8 shows one sheet (that is, one dielectric layer 1 after completion of the lapping process).
15) is a partial cross-sectional view of FIG. For example, if a plurality of sheets of sapphire are placed under reduced pressure in a hydrogen atmosphere,
Laminated together under high temperature such as 00 ° C., and then the laminated dielectric layers are diced along a plurality of planes substantially perpendicular to each surface of the dielectric layers. .

The thickness of one dielectric layer is approximately 200 micrometers, and the distance between the traces is approximately 150.
Micrometers, interconnects in the representative example above (ie equivalent to each trace above)
Has a density of approximately 3,800 per square centimeter
It can be made with high density. The distance between the traces may have a minimum value of about 50 micrometers, and in one embodiment of the present invention having such a distance, the density of the interconnects may be It is possible to improve the value to about 10,000 per square centimeter. The above-mentioned density value obtained by the present invention is much higher than the density of 30 to 60 per square centimeter as in the prior art.

As described above, as the size of each trace end (for example, trace width) is reduced and the trace end parts are spaced closer together, a standard photoresist and dry type are used. It is difficult to form the bumps 512 and 512 'by applying a well-known photolithographic exposure technique using a photosensitive film (for example, Riston). In order to establish a fine trace termination edge pattern, the layer of photoresist or the dry film approached the size of the finest edge pattern of the edge patterns established. It must be formed to have a uniform thickness. However, the photoresist processing equipment capable of forming a thin and uniform photoresist layer is designed for a thin wafer, and the solid state may be completely different in shape from the thin wafer. It is not designed for an array (solid array) type connector. Furthermore, existing dry films often have too large a thickness to establish a fine trace end (contact) pattern. Moreover,
In the case of aligning (aligning) the position of the exposure mask arranged on the photoresist layer or the dry film, when it is required to reduce the size of the contact portion, the position alignment of the exposure mask ( Alignment) must be done accurately. However, the photolithographic equipment capable of performing such positional alignment is designed for a thin wafer, not for the solid array type connector as described above.
Currently, alignment of the exposure mask with respect to the photoresist layer or dry film must be done by relatively simple manual means. Sputter deposit through the pattern mask
Other pattern transfer processes, such as the "positioning", still have a problem in performing the above-mentioned position alignment (in the above-mentioned alignment) similar to that described above.

Therefore, in the present invention, the pattern transfer as described above is performed.
Alternatively, a new method is provided for forming the bumps 512 and 512 ′ described above without using photolithographic techniques. That is, the inner portions 513 and 51
3'is formed by non-electrically plating a relatively rigid conductor material (copper is a preferred example), the conductor material being the inner portion 5 of each bump.
13 and 513 'are formed. Prior to the plating, each end of each trace is activated by any suitable means, such as adding a palladium (Pd) catalyst to the copper, as is well known in the plating art. Can be done. Based on the characteristics of the plating process, each of the inner portions 513 and 513 'is formed in all directions (i.e., in all directions) until it has a fully spherical segment shape as described above, in other words a hemispherical shape. Uniform growth (hemispherical) is achieved, which provides good adhesion between each inner portion 513 and 513 'and each trace termination. In one embodiment, each inner portion 513 and 513 'is typically formed to have a height of 5 micrometers and a diameter of 10 micrometers, and also all desired surfaces. (I.e., the desired surface on the body of dielectric material) on each of the inner portions 513 and 51.
3'can be formed at the same time.

After the inner portions have been formed, the outer layers 514 and 514 'are either non-electrically plated with a soft metal or soldering material or the metal material, such as a soldering material, melts. It is formed by performing dipping (dipping), for example, wave soldering. When the dipping is performed, the inner portions 513 and / or 51 are formed.
Each exposed surface of 3'is preferably first cleaned, for example by dipping in an acid solution, and then coated with a flux. If the same flexible metal or soldering material is used for each outer layer 514 and 514 ', then each outer layer can be formed simultaneously. A certain number of faces of the connector 500 may be masked to prevent the formation of an outer layer of material as described above on each trace termination appearing on these faces. In one example, soft gold
Are electroplated to form one or both of the outer layers 514 and 514 '. In another embodiment, the solder material is the outer layers 514 and 51.
4'is electroplated or wave soldered as described above to form one or both. Both the electroplating process and the dipping process serve to uniformly form the outer layers on the inner portions 513 and 513 ', thereby providing a sufficiently spherical segment shape and / or hemisphere. The bumps 512 and 512 'having a shape are provided in an ideal form.

When the outer layers 514 and 514 'are made of different materials, a covering mask (blanket mask) is provided to protect each of the other surfaces while one side is plated or dipped. ) May be selectively attached to each said surface. For example, if a different material needs to be electroplated to the outer layers 514 and 514 ', the first side (the side 505 or 5 above).
06) is covered with a first mask and the second surface (eg a surface other than the first surface) is electroplated. Then, the first mask is removed and a second mask is formed on the second surface. The first surface is then electroplated, after which the second mask is removed. These steps also apply when each surface is dipped in a different material and a dipping process is performed instead of the plating process.
The same can be applied. Furthermore, the masking step (masking step) can also be used in the case where one side is dipped while the other side is electroplated. For example, the first surface is masked, and then the second surface is dip or electroplated. The mask is then removed from the first surface and a second
Is formed on the second surface. The first surface is then electroplated or dipped, after which the second mask is removed. The first mask and the second
The mask of (1) is composed of a mask of an appropriate bonding agent, a resist including a photoresist, or a wax, and the selection of these mask materials is determined according to the process of protecting a predetermined surface by the mask.

In one embodiment, the soft gold outer layer comprises:
Typically, it is plated to a thickness of approximately 20 micrometers, so that the overall height of the bumps is approximately 25 micrometers in that typical case, or the sagging layer is approximately 1 to 2 micrometers thick. The dip processing is performed so that Further, as an alternative means, when the circuit board is attached to a predetermined surface of the connector, by a bump made of a solder material provided on the circuit board facing the connector side,
The solder material may be provided.

The bumps formed on the other surfaces of the connector 500 should be formed simultaneously with the bump forming process on the side surfaces 505 and 506, if the same material may be used. Or, again,
It may be formed by another masking step and a plating or dipping step. In this regard, if desired, it may also be useful to use a plurality of solders having different melting temperatures, as described above, to facilitate removal of the circuit board from the connector 500.

After forming each of the outer layers 514 and 514 ', the circuit board (eg, circuit board 1 described below) is formed.
0) is the connection by pressure contact (pressure co
ntacting) or soldering
g) can be attached to the connector 500. FIG. 9 shows two pressure contact bumps formed on the surface of the circuit board 10.
FIG. 4 is a partial cross-sectional view of the connector 500 facing the circuit board 10 having two bumps 512 aligned in a corresponding relationship with the connector 500, the circuit board 10 contacting the connector 500 with the contact pressure. (Contact p
It shows a state before being attached by the (pressure). In this embodiment, both the pressure contact bumps 15 and the outer layer 514 are made of a flexible conductive material such as soft gold. Figure 10
FIG. 6 is a partial cross-sectional view of the connector 500, the circuit board 10, the bumps 512, and the pressure contact bumps 15 after the circuit board 10 is attached to the connector 500. As mentioned above, the predetermined screws or other attachment means connect the circuit board 10 to the connector 500.
Can be used to press against. Based on the pressure applied in this case, each bump 1 for pressure contact
5 and the shapes of the outer layers 514 of the bumps 512 are both partially deformed. Here, depending on the strength of the applied pressure and the type of material used for each of the bumps 15 and each of the outer layers 514, when the circuit board 10 is removed, the deformation partially occurs. Or almost entirely remains.

FIG. 11 shows a connector 500 facing the circuit board 20 having two bumps 512 aligned with the two bumps 25 made of solder material formed on the circuit board 20. 3 is a partial cross-sectional view of the circuit board 20 before the circuit board 20 is attached to the connector 500. FIG. Each bump 25 made of the solder material
Are formed on the pads 22 corresponding to the bumps 25 arranged on the surface of the circuit board 20. In this example, each outer layer 514 is composed of a solder material. FIG. 12 shows the circuit board 20 with the connector 5
No. 00, each of the bumps 25 (made of a solder material) is integrally attached to each corresponding outer layer 514 (made of a solder material) by reflow bonding, and the connector 500, the circuit FIG. 6 is a partial cross-sectional view of the substrate 20 and each bump 512 (formed by the reflow bonding).

The above-described embodiments of the present invention are merely examples, and the present invention should not be limited thereto. That is, the scope of the present invention should not be particularly limited to the description of each of the above-described embodiments, but should be construed based on the description of the above claims. Thus, many other different embodiments and variations may be included in the practice of the present invention. For example, a predetermined number of additionally provided spacing layers may be applied to the surface of the body of dielectric material, such as by silk screening or gluing, to accurately mount the circuit board adjacent the connector. It can be attached (for example, by gluing). Obviously, all modifications considered to be within the spirit and scope of the description of the above claims should be taken as being included in the scope of the present invention.

[0053]

According to the present invention, it is possible to form the predetermined number of electrical connection portions (for example, bumps) and the predetermined number of traces in a very high density, thereby having the extremely high aspect ratio. The connector can be obtained. Further, according to the connector of the present invention, the dimensional accuracy can be accurately maintained even when various forces or stresses are applied, and the connector can be easily removed from the circuit board on the other side to reconfigure its circuit configuration. In addition, the manufacturing process is simplified, and the manufacturing cost is low. In particular, when a bump or the like is formed on each electrical connection portion of the above connector, so-called photolithographic technique and various pattern transfer processes are not required, and a predetermined number of connectors can be formed on a connector having a small size. Electrical connections (ie the bumps, etc.) can be formed.

[Brief description of drawings]

FIG. 1 is a partial plan view of a connector 100 according to an embodiment of the present invention (that is, a partial plan view of one stacking surface that appears when crossed along line 7-7 in FIG. 5),
It is a figure showing the state where three circuit boards are attached to the connector.

FIG. 2 is a perspective view showing a configuration of a connector block 200 before being cut into a predetermined number of individual connectors 100.

FIG. 3 is a partial plan view similar to FIG. 1 for a connector as another embodiment of the present invention, in which a connector body made of a dielectric material having a stop surface portion (for example, a recess) is used. It is a figure which shows the state in which the circuit board adjacent to it is connected to the connector main body.

4 is a partial vertical cross-sectional view of the connector 100 taken along its stacking direction (ie, taken along line 6-6 of FIG. 5) showing a predetermined number of vias (ie, one of the connectors). A via 402 formed inside the connector so as to extend between a plurality of adjacent layers, and a dielectric that constitutes the connector body from a trace provided in the connector to a top surface (or bottom surface) of the connector. FIG. 8 shows a via 400) formed inside the connector so as to extend through an end layer of the layers.

FIG. 5 is a connector 50 as still another embodiment of the present invention.
It is a perspective view of 0.

6 is a vertical cross-sectional view in the stacking direction of the connector 500, which is taken along line 6-6 in FIG.

7 is a view showing the connector 5 along line 7-7 in FIG.
FIG. 10 is a plan view of one stacking surface of the connector 500, which appears when crossing 00.

FIG. 8 shows one dielectric layer 1 as one embodiment of the present invention.
15 is a partial cross-sectional view of 15 showing a predetermined number of traces (electrical paths) within a predetermined number of trenches formed on the surface of the dielectric layer (shown as before being laminated). It is a figure showing the state where it was arranged and formed.

FIG. 9 is a partial cross-sectional view of the connector 500 facing the circuit board 10 before the circuit board 10 is attached to the connector 500 by the contact pressure.

FIG. 10 shows the connector 5 after the circuit board 10 is attached to the connector 500 by the contact pressure.
00 and a circuit board 10.

FIG. 11 shows the circuit board 2 before the circuit board 20 is attached to the connector 500 by soldering.
It is a fragmentary sectional view of the connector 500 which faces 0.

FIG. 12 is a partial cross-sectional view of the connector 500 and the circuit board 20 after the circuit board 20 is attached to the connector 500 by the soldering.

[Explanation of reference numerals] 10, 20, 102, 104, 106 ... Circuit board 15 ... Pressure contact bumps 22 formed on the circuit board side 22 ... Pads formed on the circuit board side 25 ... Solder formed on the circuit board side Material bump 100,500 ... Connector 200 ... Connector block 108, 110 ... Trace (electrical t)
Race 109 ... Cross-trace 400 ... Outer vias 402 ... Inner vias for interconnection
l via) 112, 412 ... Pads formed at the trace end portion on the connector side 512, 512 '... Bumps 513, 513' ... Inner portions of the bumps 514, 514 '... Outer layer 114 of the bumps ... Dielectric material Connector body 115 ... consisting of one dielectric layer to be laminated to form the connector body 116 ... screw 314 ... recess (recess)

Claims (35)

[Claims] 1. A connector body made of an electrically insulating dielectric material having a first surface and a second surface, the connector body having a predetermined number of conductive traces formed therethrough, Producing each trace having a first end that appears on the first side and a second end that appears on the second side; and each of the first and second ends. Plating a conductive material on each trace end on each of the first and second surfaces so that a predetermined number of bumps are formed on each trace end. And method for manufacturing connector. 2. The connector body is configured as a laminated multilayer block, and each of the plurality of dielectric layers forming the block forms a predetermined number of the traces in each dielectric layer. The manufacturing method according to claim 1, wherein a predetermined number of trenches filled with a conductive material for forming are formed. 3. The manufacturing method according to claim 1, wherein each of the bumps is formed such that a ratio of a height to a diameter of a base is greater than 0.25. 4. The manufacturing method according to claim 1, wherein each of the bumps is formed in a substantially hemispherical shape. 5. The connector body comprises the steps of forming a predetermined number of traces on each of a plurality of dielectric layers of rigid dielectric material, and stacking the plurality of dielectric layers into a block. 2. The manufacturing method according to claim 1, wherein the manufacturing method is formed by a process including a step of stacking and laminating, and a step of exposing each end portion of each trace. 6. A first layer made of a conductor material different from a conductive material forming each bump formed on the first surface on each bump formed on the first surface. The manufacturing method according to claim 1, further comprising a step of plating. 7. A conductor material different from the conductor material layer plated on the bumps formed on the second surface and on the bumps formed on the first surface. Second
The method of claim 6, further comprising the step of plating a layer of. 8. A step of forming a mask over the first surface before plating the second layer of the conductive material on each bump formed on the second surface. The manufacturing method according to claim 7, further comprising: 9. The method of claim 7, wherein one of the first and second layers is made of a conductive material that is more flexible than the conductive material of the other layer. Method. 10. The manufacturing method according to claim 7, wherein one of the first and second layers is made of gold and the other layer is made of a solder material. 11. Before plating the first layer of conductive material on each bump formed on the first surface,
The manufacturing method according to claim 6, further comprising forming a mask over the second surface. 12. The method further comprises the step of forming a second layer of the solder material on each bump formed on the second surface by dipping the solder material in a molten bath. The manufacturing method according to claim 6. 13. The first layer is composed of gold, while
8. The second layer is composed of a solder material.
The manufacturing method described in. 14. The method further comprises the step of forming a first layer of the solder material on each bump formed on the first surface by immersing the solder material in a bath in which the solder material is dissolved. The manufacturing method according to claim 1. 15. The manufacturing method according to claim 14, further comprising the step of plating a second layer made of a conductive material on each bump formed on the second surface. 16. The manufacturing method according to claim 15, wherein the first layer is made of a solder material, while the second layer is made of gold. 17. A step of plating a layer of flexible conductive material on each bump formed on the first and second surfaces, the conductive material forming each bump of solder material. The method of claim 1, further comprising the step of being made softer than the conductive material. 18. The method of claim 17, wherein the flexible conductor material comprises gold. 19. The method further comprising the step of forming a layer of a solder material on each bump formed on the first and second surfaces by immersing the solder material in a bath in which the solder material is melted. Item 2. The manufacturing method according to Item 1. 20. A connector body made of an electrically insulating dielectric material having a plurality of laminated dielectric layers, a first surface and a second surface, the connector body being formed through the connector body. A predetermined number of conductive traces, each trace being formed on a predetermined layer of the plurality of dielectric layers, the first terminal end appearing on the first surface and the second end. Having a second end that appears on the surface of the first trace and a first number of bumps formed on each of the first and second trace ends. And a step of plating a conductive material on each of the trace terminations on each of the second surfaces, the method of making a connector. 21. The method further comprising forming a layer of flexible conductive material on a predetermined number of bumps formed on each of the first and second sides, the conductive material forming each of the bump configurations. 21. A material that is more flexible than the material.
The manufacturing method described in. 22. The manufacturing method according to claim 20, wherein each layer made of the flexible conductor material is formed by plating. 23. The manufacturing method according to claim 20, further comprising forming a layer made of a solder material on each bump formed on the first and second surfaces. 24. At least one of the layers of solder material is formed by immersing the solder material in a molten bath.
The manufacturing method described in. 25. A step of forming a layer made of a flexible conductive material on each bump formed on one surface side of the first and second surfaces, wherein the conductive material is A material softer than the material forming the bumps, and a step of forming a layer of a solder material on each bump formed on the other surface side of the first and second surfaces. The manufacturing method according to claim 20, further comprising: 26. A solid array connector having a first surface and a second surface, the connector having a predetermined number of conductive traces formed therethrough, each trace being the first of the first and second conductive traces. A method for producing a predetermined number of bumps for electrical connection on a connector having a first end portion on the surface side of the and a second end portion on the second surface side, each of the bumps being Plating a first conductor material on each of the trace terminations that appears on the first and second surfaces so as to be formed over each of the trace terminations; A step of plating a second conductive material layer on each of the formed bumps, the second conductive material layer being different from the first conductive material material. A method for manufacturing the above bump. 27. A step of plating a layer of a third conductive material on each of the bumps formed on the second surface side, wherein the third conductive material is the second conductive material. 27. The manufacturing method according to claim 26, further comprising the step of being a material different from the material. 28. The manufacturing method according to claim 27, wherein one of the second and third conductor materials is a softer material than the other conductor material. 29. The manufacturing method according to claim 27, wherein one of the second and third conductor materials is made of gold and the other is made of a solder material. 30. An electrically insulative connector body having a first side and a second side, comprising a predetermined number of conductive traces formed through the connector body, each trace being defined as above. What has a 1st terminal part which appears on a 1st surface, and a 2nd terminal part which appears on the said 2nd surface, and the 1st predetermined number of electroconductivity formed on this 1st surface. Conductive bumps, each bump being attached to the first end portion side of the corresponding trace and having a conductive inner portion and an outer layer of a first conductive material. A second predetermined number of conductive bumps disposed on the second surface, each bump being attached to a second terminal end side of a corresponding trace and having a conductive inner portion. A second conductor material and an outer layer made of a second conductor material. Connector type of Ddoarei. 31. The connector of claim 30, wherein the second conductive material is a softer material than the first conductive material. 32. The connector of claim 30, wherein the first conductor material has a lower melting point than the second conductor material. 33. The connector of claim 32, wherein the first conductor material comprises a solder material and the second conductor material comprises gold. 34. Each said trace being composed of copper,
The connector according to claim 33. 35. The electrically insulative connector body is composed of a plurality of plane layers made of a dielectric material, and the plane layers are laminated so as to form a block, and the predetermined number of conductive layers are formed. 31. The connector of claim 30, wherein traces are formed on one or more of the plurality of planar layers of dielectric material.