JPH07109824B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH07109824B2 JPH07109824B2 JP18117587A JP18117587A JPH07109824B2 JP H07109824 B2 JPH07109824 B2 JP H07109824B2 JP 18117587 A JP18117587 A JP 18117587A JP 18117587 A JP18117587 A JP 18117587A JP H07109824 B2 JPH07109824 B2 JP H07109824B2
- Authority
- JP
- Japan
- Prior art keywords
- titanium
- seconds
- drain
- source
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 239000010936 titanium Substances 0.000 claims description 31
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 21
- 230000004888 barrier function Effects 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 claims description 16
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 15
- 229910052719 titanium Inorganic materials 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 10
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 claims description 5
- 229910021352 titanium disilicide Inorganic materials 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 239000007864 aqueous solution Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 239000012159 carrier gas Substances 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000000605 extraction Methods 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 239000012300 argon atmosphere Substances 0.000 claims 2
- 229910001069 Ti alloy Inorganic materials 0.000 claims 1
- 229910001873 dinitrogen Inorganic materials 0.000 claims 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000005121 nitriding Methods 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、配線用バリヤメタルとしてチタンナイトライ
ドを用いるMOS電界効果型トランジスタからこれを集積
化した超LSIの製造方法に関するものである。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a VLSI in which a MOS field effect transistor using titanium nitride as a barrier metal for wiring is integrated.
（従来の技術） 最近、コンタクトホールにバリヤメタルのチタンナイト
ライド（TiN）を利用する技術が研究されている。(Prior Art) Recently, a technique of utilizing barrier metal titanium nitride (TiN) for a contact hole has been studied.
第２図は従来のTiNを利用したMOS電界効果型トランジス
タ（以下、MOSFETと略す）の配線用コンタクト部分であ
る。同図において、21はバリヤメタルのTiN、22はシリ
コン（Si）基板23上に被着したチタンを700℃ないし900
℃のランプアニールで合金化したチタンダイシリサイド
（TiSi2）（以下、チタンシリサイドと略す）である。2
4はPSGであり、25はAl−Siによる配線である。FIG. 2 shows a wiring contact portion of a conventional MOS field effect transistor (hereinafter abbreviated as MOSFET) using TiN. In the figure, 21 is TiN, which is a barrier metal, 22 is titanium deposited on a silicon (Si) substrate 23, which is 700 ° C to 900 ° C.
Titanium disilicide (TiSi 2 ) alloyed by lamp annealing at ℃ (hereinafter abbreviated as titanium silicide). 2
Reference numeral 4 is a PSG, and 25 is an Al-Si wiring.
（発明が解決しようとする問題点） 上記従来の構成では、バリヤメタルのTiNを形成する際
には、最表面の合金中のチタン（Ti）を窒素（Ｎ）雰囲
気下で700℃ないし900℃で30秒ないし60秒間のランプア
ニールで行うため、プロセスが高温化する。さらに、Ti
Nに酸素が全く混入しないため、形成されるTiNが粒状構
造とならず、応力を生じ、クラック，ヒロックが発生
し、バリヤ効果が低下する欠点があった。(Problems to be Solved by the Invention) In the above conventional structure, when forming TiN of the barrier metal, titanium (Ti) in the alloy on the outermost surface is kept at 700 ° C to 900 ° C in a nitrogen (N) atmosphere. Since the lamp anneal is performed for 30 to 60 seconds, the process becomes hot. Furthermore, Ti
Since oxygen is not mixed into N at all, the formed TiN does not have a granular structure, stress is generated, cracks and hillocks are generated, and the barrier effect is deteriorated.
本発明の目的は、従来の欠点を解消し、自己整合バリヤ
メタル形成のプロセスの低温化をはかり、バリヤメタル
であるTiNのバリヤ効果を高めたMOSFETを提供すること
である。It is an object of the present invention to solve the conventional drawbacks, to provide a MOSFET in which the barrier effect of TiN, which is a barrier metal, is enhanced by lowering the temperature of the process for forming a self-aligned barrier metal.
（問題点を解決するための手段） 本発明の半導体装置の製造方法は、ポリシリコンゲート
を有するMOSFETの製造過程において、ソースドレイン形
成後、Tiをスパッタリング法で全面に被着し、600℃で6
0秒間のアルゴン（Ar）雰囲気下のランプアニールでチ
タンモノシリサイドを形成し、酸化シリコン膜上の未反
応のTiをH2O2/NH4OH水溶液で除去し、700℃ないし900℃
で90秒間Ar雰囲気下のランプアニールにより、Siが露出
していたソース・ドレイン拡散層およびポリシリコンゲ
ート上に、チタンシリサイドを形成したシリサイド構造
のMOSFETにおけるソース・ゲート・ドレインの電極とし
てのチタンシリサイド電極と外部引き出し用金属とのコ
ンタクトバリヤメタルを形成する際に、チタンシリサイ
ドの最表面の合金中のTiをCVD法で形成した誘電体分離
膜の開孔部である窓を通し、この最表面の合金中のTiを
窒素（N2）ガスをキャリヤガスとしてヒドラジンをバブ
ルしたガスを導入した500℃ないし600℃で30秒ないし90
秒間のランプアニールにより、チタンシリサイドの最表
面の合金中のTiをTiN化して、自己整合的にコンタクト
バリヤメタルとなすものである。(Means for Solving Problems) In the method for manufacturing a semiconductor device of the present invention, in the process of manufacturing a MOSFET having a polysilicon gate, Ti is deposited on the entire surface by a sputtering method after forming the source / drain, and the temperature is 600 ° C. 6
Titanium monosilicide is formed by lamp annealing in an argon (Ar) atmosphere for 0 seconds, and unreacted Ti on the silicon oxide film is removed with a H 2 O 2 / NH 4 OH aqueous solution, and the temperature is 700 ° C to 900 ° C.
Titanium silicide as a source / gate / drain electrode in a MOSFET having a silicide structure in which titanium silicide is formed on the source / drain diffusion layer and the polysilicon gate where Si was exposed by lamp annealing in an Ar atmosphere for 90 seconds. When forming a contact barrier metal between the electrode and the metal for external extraction, Ti in the alloy on the outermost surface of titanium silicide is passed through a window that is an opening of the dielectric isolation film formed by the CVD method In the alloy of Ti, nitrogen (N 2 ) gas was used as a carrier gas and a gas in which hydrazine was bubbled was introduced.
By lamp annealing for a second, Ti in the alloy on the outermost surface of titanium silicide is converted to TiN to form a contact barrier metal in a self-aligned manner.
（作 用） 上記構成により、N2ガスにキャリヤされたヒドラジンを
ランプアニール炉へ導入することにより、TiN形成条件
は500℃ないし600℃で30秒ないし90秒間となる。すなわ
ち、500℃ないし600℃の低温で合金中のTiが窒化反応を
受け、自己整合でバリヤメタルのTiNを形成する。さら
に導入されるヒドラジンは、極めて微量の水や酸素が混
入しているため、形成されるTiNの膜に酸素が取り込ま
れる。そのため、TiNの結晶が柱状となり、応力圧縮は
ほぼゼロとなるため、クラックやヒロックが入らなくな
る。(Operation) With the above configuration, by introducing hydrazine, which is carried by N 2 gas, into the lamp annealing furnace, the TiN forming condition is 500 to 600 ° C. for 30 to 90 seconds. That is, Ti in the alloy undergoes a nitriding reaction at a low temperature of 500 ° C. to 600 ° C. to form barrier metal TiN in a self-aligned manner. Further, the introduced hydrazine contains a very small amount of water and oxygen, so that oxygen is taken into the formed TiN film. Therefore, the TiN crystal becomes columnar, and the stress compression becomes almost zero, so cracks and hillocks do not enter.
（実施例） 本発明の一実施例を第１図に基づいて説明する。第１図
は、本発明のN2ガスでキャリアされたヒドラジンによる
TiのTiNバリヤメタルの自己整合法を示すものである。(Example) An example of the present invention will be described with reference to FIG. FIG. 1 shows hydrazine carried by N 2 gas of the present invention.
It shows the self-alignment method of TiN barrier metal of Ti.
第１図（ａ）において、１は厚さ300nmのポリシリコン
ゲートである。２は厚さ30nmのゲート酸化膜である。3,
4はLDD構造のソース・ドレインである。５はLDDのスペ
ーサ、６は素子分離のLOCOS酸化膜であり、７はSi基板
である。In FIG. 1 (a), 1 is a polysilicon gate having a thickness of 300 nm. Reference numeral 2 is a gate oxide film having a thickness of 30 nm. 3,
Reference numeral 4 is the source / drain of the LDD structure. Reference numeral 5 is an LDD spacer, 6 is a LOCOS oxide film for element isolation, and 7 is a Si substrate.
同図（ｂ）は、全面にTiガススパッタリング法で厚さ70
nmに被着されたTi8の状況を示す。In the same figure (b), the thickness is 70
The situation of Ti8 deposited on nm is shown.
同図（ｃ）は、600℃で60秒間のAr雰囲気下のランプア
ニールによりチタンモノシリサイドが形成され、続くH2
O2/NH4OH水溶液によるチタンモノシリサイドが生成され
ていない未反応Tiの除去、そして、700℃ないし900℃で
90秒間のAr雰囲気下のランプアニールにより、Siが露出
されていたゲート・ソース・ドレイン上にチタンシリサ
イドが形成された状態を示す。同図において、９はゲー
ト上、10はソース上、11はドレイン上に被着したTiで、
ゲート上ではTiSi2/Poly/Si、ソース・ドレイン上ではT
iSi2/Si構造となっている。In FIG. 6C, titanium monosilicide is formed by lamp annealing in an Ar atmosphere at 600 ° C. for 60 seconds, followed by H 2
Removal of unreacted Ti without formation of titanium monosilicide by O 2 / NH 4 OH aqueous solution, and at 700 ℃ to 900 ℃
It shows a state in which titanium silicide is formed on the gate, source and drain where Si was exposed by lamp annealing in an Ar atmosphere for 90 seconds. In the figure, 9 is Ti deposited on the gate, 10 is on the source, and 11 is on the drain.
TiSi 2 / Poly / Si on the gate, T on the source / drain
It has an iSi 2 / Si structure.
同図（ｄ）では、PSGを厚さ600nmに被着し、コンタクト
窓12を開孔した状態を示す。In the same figure (d), PSG is deposited to a thickness of 600 nm and the contact window 12 is opened.
同図（ｅ）は、Ｎガスでキャリアされたヒドラジン導入
により、500℃ないし600℃で30秒ないし90秒間のランプ
アニールにより、自己整合で形成された厚さ30nm弱のTi
Nを示す。13はPSGから露出された最表面の合金中のTiが
窒化反応を受けて形成したTiNである。In the same figure (e), the Ti gas with a thickness of less than 30 nm is formed in a self-aligned manner by the lamp anneal at 500 ° C to 600 ° C for 30 seconds to 90 seconds by introducing hydrazine carried by N gas.
Indicates N. 13 is TiN formed by the nitriding reaction of Ti in the outermost alloy exposed from PSG.
上記のように形成されたTiNから、FETの特性に影響を与
えないバリヤメタルが形成される。A barrier metal that does not affect the characteristics of the FET is formed from the TiN formed as described above.
（発明の効果） 本発明によれば、窒化反応によるTiNのバリヤメタル形
成法を自己整合で行っているめ、クォーターミクロンレ
ベルでTiNバリヤメタル形成が可能であり、ヒドラジン
を窒化反応種として使用するため、プロセスを低温化す
ることができる。(Effect of the invention) According to the present invention, since the barrier metal forming method of TiN by the nitriding reaction is performed in a self-aligned manner, it is possible to form the TiN barrier metal at the quarter micron level, and since hydrazine is used as the nitriding reaction seed, The process can be cooled down.
また、ヒドラジンに混入する微量の水と酸素をTiNへ入
れているため、柱状結晶となり、圧縮応力をゼロにする
ことができ、クラックやヒロックが入らず、その実用上
の効果は大である。Moreover, since a small amount of water and oxygen mixed in hydrazine are put into TiN, it becomes a columnar crystal, the compressive stress can be made zero, cracks and hillocks do not enter, and its practical effect is great.
第１図は本発明の一実施例における半導体装置の製造方
法を示す断面図、第２図は従来のTiNを利用したMOSFET
の配線用コンタクト部分の断面図である。 １……ポリシリコン、２……酸化膜、3,4……LDD構造の
ソース，ドレイン、５……LDDのスペーサ、６……素子
分離のLOCOS酸化膜、７……シリコン基板、８……チタ
ン（Ti）、９……ゲート上のチタン（Ti）、10……ソー
ス上のチタン（Ti）、11……ドレイン上のチタン（T
i）、12……コンタクト窓、13……チタンナイトライド
（TiN）。FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a conventional MOSFET using TiN.
3 is a cross-sectional view of a wiring contact portion of FIG. 1 ... Polysilicon, 2 ... Oxide film, 3,4 ... Source / drain of LDD structure, 5 ... LDD spacer, 6 ... LOCOS oxide film for element isolation, 7 ... Silicon substrate, 8 ... Titanium (Ti), 9 …… Titanium (Ti) on the gate, 10 …… Titanium (Ti) on the source, 11 …… Titanium (T) on the drain
i), 12 ... Contact window, 13 ... Titanium nitride (TiN).
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/43 29/78 Ｈ０１Ｌ 29/62 Ｇ Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI Technical display location H01L 29/43 29/78 H01L 29/62 G
Claims (1)
型トランジスタの製造方法において、ソース・ドレイン
形成後、チタンをスパッタリング法で全面に被着し、60
0℃で60秒間アルゴン雰囲気下のランプアニールでチタ
ンモノシリサイドを形成し、酸化シリコン膜上の未反応
チタンをH2O2/NH4OH水溶液で除去し、700℃ないし900℃
で90秒間アルゴン雰囲気下のランプアニールにより、シ
リコンが露出していたソース・ドレイン拡散層およびポ
リシリコンゲート上に、チタンダイシリサイドを形成し
たシリサイド構造のMOS電界効果型トランジスタにおけ
るソース・ゲート・ドレイン上のチタンダイシリサイド
電極と外部引き出し用金属とのコンタクトバリヤメタル
を形成する際に、チタンダイシリサイドの最表面の合金
中のチタンをCVD法で形成した誘電体分離膜の開孔部で
ある窓を通し、この最表面の合金中のチタンを窒素ガス
をキャリアガスとしてヒドラジンをバブルしたガスを導
入した500℃ないし600℃で30秒ないし90秒間のランプア
ニールにより、前記チタンダイシリサイドの最表面の合
金中のチタンをチタンナイトライド化して自己整合的に
コンタクトバリヤメタルとなすことを特徴とする半導体
装置の製造方法。1. A method for manufacturing a MOS field effect transistor having a polysilicon gate, wherein titanium is deposited on the entire surface by sputtering after forming the source / drain.
Titanium monosilicide is formed by lamp annealing in an argon atmosphere at 0 ° C for 60 seconds, and the unreacted titanium on the silicon oxide film is removed with an H 2 O 2 / NH 4 OH aqueous solution.
On the source / drain / drain of the silicide structure MOS field-effect transistor in which titanium disilicide was formed on the source / drain diffusion layer and the polysilicon gate where silicon was exposed by lamp annealing in argon atmosphere for 90 seconds. When forming the contact barrier metal between the titanium disilicide electrode and the metal for external extraction, a window that is an opening of the dielectric isolation film formed by CVD of titanium in the alloy on the outermost surface of titanium disilicide is formed. The titanium alloy in the outermost surface of the titanium disilicide is subjected to lamp annealing at 500 ° C. to 600 ° C. for 30 seconds to 90 seconds in which a gas in which hydrazine is bubbled with nitrogen gas as a carrier gas is introduced into titanium in the outermost surface alloy. The titanium in the inside is converted into titanium nitride and used as a contact barrier metal in a self-aligning manner. The method of manufacturing a semiconductor device according to claim Succoth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18117587A JPH07109824B2 (en) | 1987-07-22 | 1987-07-22 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18117587A JPH07109824B2 (en) | 1987-07-22 | 1987-07-22 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6425571A JPS6425571A (en) | 1989-01-27 |
| JPH07109824B2 true JPH07109824B2 (en) | 1995-11-22 |
Family
ID=16096195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18117587A Expired - Lifetime JPH07109824B2 (en) | 1987-07-22 | 1987-07-22 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07109824B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR920005242A (en) * | 1990-08-20 | 1992-03-28 | 김광호 | Method of manufacturing transistor having structure of gate-insulator-semiconductor |
| KR100294637B1 (en) | 1998-06-29 | 2001-10-19 | 박종섭 | Method for forming polycide gate in MOSFET |
-
1987
- 1987-07-22 JP JP18117587A patent/JPH07109824B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6425571A (en) | 1989-01-27 |
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