JPH07108117B2 - Spindle motor speed controller for recording / reproducing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing device, and more particularly to a rotation speed control device for a spindle motor of a floppy disk drive device.

(Prior Art) Recently, as the price of a Proppy disk drive device (hereinafter referred to as an FDD device) has decreased, its application field has expanded. As the range of application increases, the types of user requirement specifications for FDD devices also increase, and along with this, there are increasing examples of adopting gate array ICs in the device control unit of FDD devices. When using a gate array IC, it is essential to use an oscillator that serves as a reference clock in order to have a timer function. On the other hand, there is a demand for performance improvement in terms of long-term rotation stability of the spindle motor, and there is also an effort to reduce the long-term rotation fluctuation by using an oscillator in the motor speed control circuit (Fig. 5). reference).

As described above, recently, the case where two reference oscillators are used is increasing. Furthermore, since the frequency of the reference oscillator and the frequency of the rotation speed signal are very different, it is necessary to divide the reference frequency to a frequency close to the rotation speed signal. It has a divider circuit to make it. That is, the reference oscillator and the frequency dividing circuit are provided in an overlapping manner, which increases the cost.

On the other hand, there is a ready generation circuit that detects that the spindle has rotated at a constant speed and recording / playback is possible.In the past, a counter circuit etc. was used to measure when the index cycle reached a predetermined time, and then the index The signal was received twice, and the ready was detected. Normally, the spindle motor has a predetermined number of revolutions within one revolution, but since the number of revolutions is detected by the index signal, this can be measured only every one revolution,
Measurement will be delayed.

(Problems to be Solved by the Invention) As described above, in the conventional configuration, the reference oscillator and the frequency dividing circuit are provided in an overlapping manner, and there is a problem in terms of cost and reliability.

In addition, a complicated index period measurement counter circuit is required for ready detection, which is problematic in terms of reliability, cost, and response speed.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention is configured in an IC in the same package as an apparatus control circuit section for controlling a recording / reproducing apparatus, and provides a reference clock for the apparatus circuit section. R / S to synchronize
If the flip-flop type phase comparator and the reference clock pulse and the rotation speed signal pulse from the spindle motor index sensor are alternately input, the output is turned off in a synchronous state, and if the reference clock continues twice, the output accelerates. The synchronous pull-in circuit is such that the output is decelerated when the rotation speed signal continues twice. The adder is provided outside the IC package and adds the average value of the phase comparator signal and the synchronous pull-in circuit output. It The ready signal is also obtained from the rotation speed control unit.

According to the above configuration, highly stable rotation speed control can be performed with a simple circuit configuration, a complicated counter circuit is not required, and a ready response circuit with fast response and high reliability can be obtained at low cost. .

(Embodiment) FIG. 1 shows an embodiment of the present invention, in which a portion 7 indicated by a dotted line is converted into a digital IC and housed in the same package. Reference numeral 8 denotes a device control unit which outputs a motor ON / OFF signal C in response to a signal from the host system. Further, it divides the signal of the reference oscillator 2 and outputs the reference frequency signal D. Reference numeral 9 denotes a phase comparator, which is a rotation speed signal A of the rotation speed sensor 6.
And the phase of the reference frequency signal D are compared to obtain the signal E. Ten
Is a synchronous pull-in circuit that detects three states of whether signals A and D are alternately input or one of them is input two or more times in succession.
Is output. The signal F has tristates of "HIGH", "LOW", and "Hi-Z". The signals E and F are combined by the adder 11 to obtain the motor control signal B. The adder 11 includes a lead compensation circuit and a motor constant current drive circuit.

FIG. 2 is a timing chart at the time of starting the motor. Signals C and F become "HIGH" by the motor ON signal from the host system, and motor rotation starts. The motor is controlled by the signal B, but acceleration is started at the start of rotation. As the rotation increases, the cycle of the signal A becomes shorter, and when the signal A continues twice in one cycle of the signal D in FIG. 2A, the signal F changes to “Hi-Z” and the signal B changes. The phase control information of the signal A is output to. Since the acceleration at the time of start-up is rapid, the signal A is input twice in succession even at the position b, so that the signal F changes to "LOW" and the signal B is stopped. At this point, the acceleration at the start is stopped, and the cycle of the signal A goes in the direction of becoming longer. Next, in c, when the signal D is input twice in succession during one cycle of the signal A, the signal F becomes "Hi-Z" again, and the phase information of the signal A is output to the signal B. In a and b, the acceleration was so rapid that the phase synchronization was not reached, but at this time, the period change of the signal A is gentle, so that the phase synchronization is achieved at d. Since the signals A and D alternately enter at d, the signal F maintains "Hi-Z", the signal E rises at the signal D, the signal E falls at the signal A, and is proportional to the duty of the signal E. Signal B will control the motor. When the rotation speed is small and the signal A lags behind the signal D, the duty becomes large and the rotation speed becomes large. On the contrary, when the rotation speed is high, the duty becomes small and the rotation speed becomes small. By repeating this, the rotation is stabilized by the duty corresponding to the amount of the motor load, that is, the phase difference between the signals D and A. Note that e in FIG. 2 shows a case where the load is light, and f shows a case where the load is heavy.

The present invention controls the rotation speed based on the above principle,
FIG. 3 shows a more specific embodiment of the sync pull-in circuit 10 for producing the signal F, and the phase comparator is also implemented in this circuit. 13,15 are R / S flip-flops, 14a, 14b, 16a,
16b and 19 and 20 are edge-triggered D flip-flops, 17 is
AND gate, 18 is a tri-state gate.

FIG. 4 is a detailed timing diagram of the specific circuit of FIG. When the motor ON signal C is "LOW", each flip-flop is initialized when two pulses of the reference signal D are input as shown in FIG. After this, the motor ON signal C changes to "HIG
When it becomes "H", the whole circuit becomes operable and the output F becomes "HIG
At "H", the motor starts rotating under acceleration.

Next, when the pulse of the rotation speed signal A enters as shown in FIG. 4A, E becomes "HIGH" and the output of Q of the D flip-flop 14b becomes "LOW". The signal E is reset to "LOW" by the next pulse of the signal D as shown in (c), and this operation is the function of the phase comparator.

When the cycle of the rotation speed signal A becomes shorter than the cycle of the reference signal D, the acceleration state of a changes. When the flip-flop 13 is set in D of FIG. 4 and then the pulse of the signal A is input before the signal D in E, the Q output (signal E) of the flip-flop 13 is latched by the flip-flop 14a, and the flip-flop is further flipped. Flip 15 is set, flip-flop 16b
Is reset. At this time, the output of the AND gate 17 of both "HIGH" of the flip-flops 16a and 16b becomes "HIGH", and the tristate gate 18 becomes "Hi-Z".

The Q output of the flip-flop 14a is reset by the next signal D like a signal and becomes a pulsed signal. Here, the state is as shown in FIG. 4b, but since the motor is rotating too fast, the signal A has two pulses between the signals D. A pulse is output to the Q signal of the flip-flop 14a by the pulse of the signal A, as shown in Fig. 4C.
The Q output of the flip-flop 15 is latched by the flip-flop 16a. At this time, the output of AND gate 17 is "LOW"
Then, the Q output of the flip-flop 16b passes through the tri-state gate 18, and the signal F becomes "LOW". That is, the motor shifts to deceleration. From this time, the motor starts decelerating, and the cycle of the rotation speed signal A spreads and approaches the cycle of the reference signal D.

In FIG. 4C, when two pulses of the signal D are input in one cycle of the signal A, a pulse is output to the Q output of the flip-flop 14b and the flip-flop 15 is reset. Then, the Q output of the flip-flop 15 becomes "LOW", so the flip-flop 16a is reset and the AND gate
The output of 17 becomes “HIGH” again, and tristate gate 1
8 becomes "Hi-Z".

In this state of d, the number of rotations of the motor is controlled by the average value of the signal E, but the signals D and A rotate while maintaining a certain phase relationship as shown in FIG. . That is, the synchronization pull-in succeeds and the phase control state is entered.

In the phase control state, the input of the flip-flop 19 is "HIGH", during which the index signal is 2
When a pulse is input, the Q output of the flip-flop 20 becomes "HIGH" and the ready state is set.

(Effect of the invention) As an effect of the present invention, since the device control unit and the rotation speed control unit are ICs in the same package, the configuration is such that the reference oscillator and the reference clock frequency divider are shared, which is advantageous in terms of cost. is there. Further, the connection between the control units is also eliminated, which leads to improvement in reliability.

Another effect is the PLL with the phase comparator and the synchronous pull-in circuit.
Since this is a speed control system, it is possible to obtain a highly stable rotation speed that allows long-term rotation fluctuations to be ignored, despite the simple circuit configuration.

As another effect, since the condition of the ready signal is that the phase is pulled in, the complicated counter circuit that counts the index period is not required, and the response is fast,
A highly reliable and low cost ready generation circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is
FIG. 3 is a timing diagram showing the operation of FIG. 1, FIG. 3 is a specific circuit diagram including a sync pull-in circuit, a phase comparator and a ready detection circuit of the present invention, and FIG. 4 is a timing diagram of the circuit of FIG. FIG. 5 is a block diagram of a conventional example in which the device control unit and the rotation speed control unit are separated. 2 ... Reference oscillator, 5 ... Spindle motor, 6 ... Rotation speed sensor, 7 ... Digital IC, 8 ... Device control unit,
9 ... Phase comparator, 10 ... Sync pull-in circuit, 11 ... Adder (including motor drive circuit).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 56-3588 (JP, A) JP 60-47515 (JP, A) JP 60-299672 (JP, A) JP 61- 98178 (JP, A) JP 62-100183 (JP, A) JP 62-247781 (JP, A)

Claims (1)

[Claims] 1. An R / S flip-flop type phase comparator configured in an IC in the same package as a device control circuit unit for controlling a recording / reproducing device and synchronized with a reference clock of the device circuit unit, and a reference clock pulse. If the rotation speed signal pulses from the index sensor of the spindle motor and the spindle motor are alternately input, the output is turned off in a synchronized state. If the reference clock continues twice, the output accelerates. If the rotation speed signal continues twice, the output slows down. Such a synchronous pull-in circuit, and provided outside the IC package, consisting of an adder for adding the average value of the phase comparator signal and the synchronous pull-in circuit output, the phase comparator and the synchronous pull-in circuit, A first detection circuit for detecting the rising edge of several signal pulses, a second detection circuit for detecting the rising edge of a reference clock pulse, and a second detection circuit set by the output signal of the first detection circuit, A first R / S flip-flop reset by an output signal of the detection circuit, and a Q output of the first R / S flip-flop latched by the output signal of the first detection circuit as a trigger, and the second R / S flip-flop The first D flip-flop reset by the output signal of the first detection circuit and the output signal of the first R / S flip-flop triggered by the output signal of the second detection circuit to perform the first detection A second D flip-flop reset by the output signal of the circuit and a second R / S flip-flop set by the Q output of the first D flip-flop and reset by the Q output of the second D flip-flop. And the Q output of the second R / S flip-flop is “H
The outputs of the third D flip-flop and the second R / S flip-flop which are latched at the rising edge of the Q output of the first D flip-flop at the time of "IGH" and reset at the time of "LOW" Is "HIGH", the output is latched at the rising edge of the Q output of the second D flip-flop,
A fourth D flip-flop reset when "LOW", an output of the third D flip-flop and a fourth D flip-flop
When both outputs of the flip-flops are "HIGH", the impedance becomes high impedance and the Q of the fourth D flip-flop is increased.
A tristate gate that does not pass an output and otherwise passes a Q output of the fourth D flip-flop, wherein the Q output of the first R / S flip-flop is a phase comparison output, and the tristate gate The output of is set as the synchronous pull-in circuit output, and after becoming the synchronous state, the index sensor signal becomes 2
A spindle motor rotation speed control device for a recording / reproducing apparatus, comprising a ready detection circuit for detecting a ready-for-recording state when a pulse or more is input and outputting a ready signal.