JPH07192357A - Phase servo circuit for control single - Google Patents

Abstract

PURPOSE:To shorten the lock-in time of a phase servo and eliminate its variance. CONSTITUTION:When a motor 17 is stopped, the speed begins to be reduced with the leading edge of a reference signal SA. when the number of pulses of an FG signal in the speed reduction period reaches a specific value N1, the motor 17 stops. When the motor 17 is actuated next time, it is predicted that the leading edge of a CTL signal comes when the number of pulses of the FG signal reaches the value obtained by subtracting the specific value N1 from the number N0 of pulses at a stationary speed. When the motor 17 is actuated, the speed begins to be increased with the leading edge of the reference signal SA and acceleration is so set that the number of pulses of the FG signal in (n) cycles of the reference signal SA satisfies Dn=(nXN0-N1), thereby putting the CTL signal and reference signal SA in phase with each other when the reference signal SA is inputted by (n) cycles. Here, a phase servo is actuated to shorten the lock-in time and the variance is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control signal phase servo circuit suitable for use in a data recorder, a VTR or the like in which control signals are recorded.

[0002]

2. Description of the Related Art In a data recorder or VTR, a continuous control signal (CTL signal) is recorded at the lower end of a magnetic tape in order to control the transfer speed of the magnetic tape. By controlling the capstan motor so that the frequency of the CTL signal becomes constant, the speed of the magnetic tape transferred by the capstan motor can be made constant.

FIG. 6 shows the configuration of a conventional control signal phase servo circuit 1 applied to, for example, a VTR. V
In the TR reproduction mode, the CTL signal recorded on the magnetic tape 10 is reproduced by the magnetic head 11. The reproduced CTL signal is amplified by the amplifier 12 and supplied to the phase difference detection circuit 13. A vertical synchronizing signal or the like is supplied to the phase difference detecting circuit 13 as the reference signal SA. Then, the phase difference between the reference signal SA and the CTL signal is detected here, and this phase difference signal SB is sent to the phase compensation circuit (delay compensation circuit) 14.

In the phase compensation circuit 14, a control signal SC for adjusting the phase of the CTL signal to the phase of the reference signal SA is generated based on the phase difference signal SB, which is passed through the terminal a of the changeover switch 15 and the speed detector 22. With motor FG2
The speed data detected from 0 is added to the amplifier 16
Is supplied to the capstan motor 17 via. As a result, the speed of the capstan motor 17 is controlled to control the feeding speed of the magnetic tape 10, and the phases of the CTL signal and the reference signal SA are matched.

Further, when the capstan motor 17 is started or stopped, the changeover switch 15 is changed over to the terminal b side, for example, the operation key 18 for reproducing or stopping the VTR is operated, and the acceleration / deceleration signal SD is sent from the CPU 19. To be done. The acceleration / deceleration signal SD is supplied to the capstan motor 17, whereby the capstan motor 17 is decelerated and stopped when the stop mode is set, and the capstan motor 17 is accelerated when the start mode is set. The speed becomes steady.

[0006]

By the way, since the frequency of the CTL signal corresponds to the transfer speed of the magnetic tape 10, that is, the rotation speed of the capstan motor 17, during acceleration in the start mode or in the stop mode. CT during deceleration of
The frequency of the L signal becomes unstable. Further, when stopped, the CTL signal is not reproduced.

Therefore, the conventional phase servo circuit 1 cannot accurately control the stop position of the CTL signal in the stop mode, and the stop position of the CTL signal changes each time. Therefore, since the stop position of the CTL signal cannot be predicted even at the time of start-up, the phase of the CTL signal when the capstan motor 17 is accelerated to reach the steady speed is different each time, and the initial phase of the CTL signal and the reference signal SA is different. Uncertain. Therefore, as described below, the lock-in time of the phase servo may vary and it may take a long time.

FIG. 7 shows the relationship between the speed of the capstan motor 17 at startup and the reference signals SA and CTL signals. As shown in FIG. 7A, when the capstan motor 17 is turned on and then accelerated to reach a steady speed, the phase servo is turned on. Then, after that, the phase of the CTL signal is controlled so as to match the phase of the reference signal SA.

On the other hand, the reference signal SA is generated in synchronism with the capstan motor 17, as shown in FIG. 1B, so that its phase is fixed. On the other hand, the CTL signal has different phases at the time of startup as shown in FIG.
The initial phase difference P0 between the reference signal SA and the CTL signal is 0 ° to
It changes between 180 °. That is, in the best case, the phases of the CTL signal and the reference signal SA match when the phase servo is activated, and in the worst case, the phases are opposite as shown in FIG.

The time (lock-in time) from the start of the phase servo to the lock-in (convergence) of the servo is
It greatly changes depending on the initial phase difference P0. That is, the lock-in time is the shortest when the initial phases of both are the same, and the lock-in time is the longest when the initial phases are the opposite phases.

As described above, in the conventional phase servo circuit 1,
Since the initial phase difference P0 is different each time, the lock-in time varies, and when the initial phase of the CTL signal is opposite to the reference signal SA, the lock-in time takes a long time. It was

Therefore, the present invention solves the above-mentioned problems and provides a control signal phase servo circuit capable of eliminating the lock-in time variation of the phase servo and shortening the lock-in time. It is a proposal.

[0013]

In order to solve the above problems, according to the present invention, a phase difference detecting circuit for detecting a phase difference between a reproduced control signal and a reference signal, and a phase for correcting a phase delay of a control signal. With a compensation circuit,
In the phase servo circuit of the control signal that controls the capstan motor based on the control signal corrected by the phase compensation circuit, the start operation and the stop operation of the capstan motor are started at the timing of the edge of the reference signal, Set the capstan motor so that the pulse number of the FG signal generated corresponding to the rotation speed of the capstan motor becomes a predetermined value during the acceleration period after the start operation of the capstan motor or during the deceleration period after the start operation of the capstan motor. It is characterized by controlling.

[0014]

When the capstan motor 17 of FIG. 1 is stopped,
Deceleration is started at the rising timing of the reference signal SA (Fig. 2 (B)) immediately after the stop command (Fig. 2 (A)) is input. Then, the pulse number N1 of the FG signal (FIG. 2D) during the deceleration period until the capstan motor 17 is stopped is counted by the counter 21. Accordingly, when the capstan motor 17 is activated next time, it can be predicted that the CTL signal will rise when the pulse number of the FG signal becomes D1 = (N0-N1).

Therefore, next, the capstan motor 17
When activating the reference signal S as shown in FIG.
If the acceleration is started at the timing of the rising edge of A and the acceleration is set so that the pulse number of the FG signal in the n cycle of the reference signal SA becomes Dn = (nN0-N1), the acceleration of the reference signal SA after the acceleration starts. In n cycles, the CTL signal and the reference signal SA come into phase with each other. Therefore, if the phase servo is activated here, the lock-in time is shortened and the variation is eliminated.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a control signal phase servo circuit according to the present invention will now be described in detail with reference to the drawings. The same parts as those described above are designated by the same reference numerals and detailed description thereof is omitted.

FIG. 1 shows a configuration in which the phase servo circuit 1 for a control signal according to the present invention is applied to a VTR. In this phase servo circuit 1, the capstan motor 1
An FG (frequency generator) 20 mounted on the No. 7 sends an FG signal corresponding to the rotation speed of the capstan motor 17, and this is supplied to a counter 21 to count the number of pulses. The count signal SE is supplied to the CPU 19, where the number of pulses of the FG signal in one cycle of the reference signal SA such as a vertical synchronizing signal is detected. The counter 21 is reset at the edge timing of the reference signal SA.

Further, in this phase servo circuit 1,
When the stop mode is set by the operation key 18 during the reproduction mode, the capstan motor 17 is decelerated and stopped at the edge timing immediately after the reference signal SA, for example, the rising edge timing. On the contrary, when the reproduction mode is set from the stop mode, the capstan motor 17 is activated and accelerated at the timing of the rising edge immediately after the reference signal SA.

FIG. 2 shows the relationship between the speed of the capstan motor 17 and each signal when the reproduction mode is changed to the stop mode. As shown in FIG. 9A, when the stop mode is set at the point X1 where the capstan motor 17 is at the steady speed, the stop command is input. After that, the phase servo operates up to the point Y1 which is the timing of the rising edge of the reference signal SA shown in FIG.

Then, when the point Y1 is reached, a reset pulse SF is generated as shown in FIG. 6 (E), whereby the counter 21 is reset. At this time, the deceleration of the capstan motor 17 is started and stopped at the Z1 point.

The counter 21 counts the pulse number N0 of the FG signal for one cycle of the control signal (CTL signal) when the capstan motor 17 is at a steady speed as shown in FIG. CPU1
9 and is stored in its memory. Further, the pulse number N1 of the FG signal from the Y1 point where the capstan motor 17 starts decelerating to the Z1 point where the deceleration is stopped is counted and supplied to the CPU 19. And CPU
At 19, the difference D1 = (N0−N1) between the pulse number N0 at the steady speed and the pulse number N1 during the deceleration period is calculated.

After the capstan motor 17 is stopped, C
Since the TL signal is not reproduced, the position of the next rising edge of the CTL signal is unknown. However, if the capstan motor 17 that is stopped is rotated, it can be seen that the rising edge of the CTL signal comes when the FG signal is output and the number of pulses becomes the same as the above-mentioned difference D1. This is because the number of pulses of the FG signal in one cycle of the CTL signal is the constant value N0.

As described above, in the conventional method, the stop position of the CTL signal when the capstan motor 17 is stopped cannot be detected, but in this example, the CTL signal and the FG signal when the capstan motor 17 is stopped are detected. By measuring the relationship with the pulse number, it is possible to accurately predict the position of the rising edge of the CTL signal immediately after the capstan motor 17 is stopped.

Further, when the capstan motor 17 is sufficiently decelerated, the capstan motor 17 is controlled so that the pulse number of the FG signal becomes a predetermined value N1 after the deceleration is started.
It is easy to stop. By controlling in this way, it becomes possible to shorten the lock-in time of the phase servo of the CTL signal and to eliminate the variation as described below.

FIG. 3 shows the speed of the capstan motor 17 and the waveform of each signal when the VTR is set to the reproduction mode. Here, it is assumed that the capstan motor 17 is in the state described with reference to FIG. 2, that is, the CTL signal has stopped before the rising edge by the above-mentioned difference D1 = (N0-N1).

When the reproduction mode is set in this stopped state, as shown in FIG. 3 (A), the capstan motor 1
A play command is input at the X2 point where 7 is stopped. Then, similarly to when the stop mode is set, the acceleration of the capstan motor 17 is started at the timing of the rising edge of the reference signal SA shown in FIG.
As a result, the CTL signal shown in FIG. 7C is reproduced and the FG signal shown in FIG.

At the same time, the counter 21 counts the number of pulses of the FG signal for one cycle of the CTL signal, as shown in FIG. And the capstan motor 17
When the count value of the counter 21 becomes equal to the above-mentioned difference D1 = (N0-N1) after starting, the first rising edge S1 of the CTL signal is output. Further, when the count value becomes D2 = (2 × N0−N1), the second rising edge S2 of the CTL signal is output, and when the count value becomes D3 = (3 × N0−N1), the third rising edge S3. Is output.

Now, as shown in FIG. 3, the capstan motor 1
7 starts acceleration at the Y2 point, reaches a steady speed at the Z2 point, and controls to activate the phase servo of the CTL signal at the Z2 point, the time T from the Y2 point to the Z2 point
In this example, the pulse number of the FG signal becomes D2 = (2 × N0−N1) in the period of two cycles of the reference signal SA, and at the same time, the capstan motor 17 is controlled so as to reach the steady speed within the time T. Good.

Here, the number of pulses of the FG signal is set to be D2 in the period of two cycles of the reference signal SA,
This is because the case where (N0 / 2) <N1 is illustrated, and (N
If 0/2) ≧ N1, the pulse number of the FG signal becomes D2 in the period of one cycle of the reference signal SA, and it is also possible to control so that the steady speed is reached within this period.

When the steady speed is controlled to reach the steady speed in the period of 2 cycles as described above, the second rising edge S2 of the CTL signal is generated at the Z2 point where the phase servo is activated.
And the rising edge of the reference signal SA match,
The lock-in time of the phase servo is shortened and high-speed phase servo is realized. In addition, there is no variation in lock-in time.

FIG. 4 shows the stop processing 30 of the phase servo circuit 1.
The procedure of is shown. In this stop processing 30, first, when the stop mode is set (step 31), it is then determined whether or not a stop command is input (step 3).
2). If it is determined that this has been input, then it is determined whether or not the rising edge of the reference signal SA has been input (step 33). When the rising edge of the reference signal SA is input, the counter 21 is next reset (step 34), and then the capstan motor 17 is decelerated (step 35).

Next, it is judged whether or not the count value of the counter 21 reaches the predetermined value N1 (step 36). It should be noted that the predetermined value N1 is measured when the tape loading and the initial setting are performed at the time of inserting the magnetic tape, and this is the criterion for determination in step 36. When it is determined in step 36 that the count value has not reached the predetermined value N1,
In step 35, the deceleration process is continued. Then, at the same time when the counter value reaches the predetermined value N1, the capstan motor 1
7 is stopped (step 37), and this stop processing 30 ends.

FIG. 5 shows the start processing 40 of the phase servo circuit 1.
The procedure of is shown. In the activation process 40, for example, when the VTR reproduction mode is set (step 41), it is determined whether or not a start command is input next (step 42). Here, when the start command is input, it is next determined whether or not the rising edge of the reference signal SA is input (step 43). When the rising edge is input, the counter 21 is reset (step 44), and subsequently the acceleration of the capstan motor 17 is set (step 45).

Next, the capstan motor 17 is accelerated (step 46), and subsequently it is judged whether or not the reference signal SA has become two cycles (step 47). And
Simultaneously with the two cycles, the phase servo of the CTL signal is activated (step 48), and this activation processing 40 ends.

In the above example, the count value of the counter 21 is D2 = (2 × during the period of two cycles of the reference signal SA.
N0-N1) has been described, and the case where the capstan motor 17 is controlled so as to have a steady speed within this time has been described. However, the count value of the counter 21 is n cycles of the reference signal SA (n is a positive integer). Is Dn = (n × N0−
N1), and if the capstan motor 17 is controlled to have a steady speed within this period, high-speed phase servo becomes possible. n can be set as appropriate according to the characteristics of the capstan motor 17.

Further, in the above-described embodiment, when the capstan motor 17 is stopped, when the pulse number of the FG signal during the deceleration period reaches the predetermined value N1, the capstan motor 1
7 is stopped and the capstan motor 17 is activated, the capstan motor 1 is activated within n cycles of the reference signal SA.
7 becomes steady speed and F in n cycle period
The number of pulses of the G signal is n of the number of pulses N0 at the steady speed
A value obtained by subtracting the predetermined value N1 from the multiple Dn = (n × N0−N1)
The case where the capstan motor 17 is accelerated has been described above. However, when the capstan motor 17 is stopped, when the pulse number of the FG signal during the deceleration period becomes equal to the pulse number N0 at the steady speed, the capstan motor 17 When the capstan motor 17 is started, the capstan motor 17 may be accelerated so that the steady speed is reached during the n cycle period of the reference signal SA.

[0037]

As described above, according to the present invention, the start and stop operations of the capstan motor are started at the edge timing of the reference signal, and the capstan motor is accelerated or decelerated. The capstan motor is controlled so that the number of pulses of the FG signal generated corresponding to the number of revolutions becomes a predetermined value.

Therefore, according to the present invention, since the stop position of the control signal related to the pulse number of the FG signal can be predicted, it becomes possible to control the time when the phases of the control signal and the reference signal match. . Then, by activating the phase servo when the phases of both agree with each other, it is possible to shorten the lock-in time, and it is possible to eliminate the variation.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a phase servo circuit 1 for a control signal according to the present invention.

FIG. 2 is a signal waveform diagram when a stop mode is set.

FIG. 3 is a signal waveform diagram when a reproduction mode is set.

FIG. 4 is a diagram illustrating a procedure for stopping the capstan motor 17.

FIG. 5 is a diagram illustrating a procedure for starting the capstan motor 17.

FIG. 6 is a configuration diagram of a conventional phase servo circuit 1 for a control signal.

FIG. 7 is a signal waveform diagram when a conventional reproduction mode is set.

[Explanation of symbols]

 1 Phase Servo Circuit of Control Signal 11 Magnetic Head 13 Phase Difference Detection Circuit 14 Phase Compensation Circuit 17 Capstan Motor 19 CPU 20 FG 21 Counter

Claims (3)

[Claims] 1. A phase difference detection circuit for detecting a phase difference between a reproduced control signal and a reference signal, and a phase compensation circuit for correcting a phase delay of the control signal. In a phase servo circuit of a control signal adapted to control the capstan motor based on the control signal, a start operation and a stop operation of the capstan motor are started at the timing of the edge of the reference signal, and the capstan motor of the capstan motor is controlled. The capstan motor is controlled so that the pulse number of the FG signal generated corresponding to the rotation speed of the capstan motor becomes a predetermined value during the acceleration period after the start operation is started or the deceleration period after the stop operation is started. A phase servo circuit for control signals, which is characterized in that 2. When the capstan motor is stopped,
When the number of pulses of the FG signal in the deceleration period reaches a predetermined value N1, the capstan motor is stopped, and when the capstan motor is started, the capstan motor is operated at a constant speed within n cycles of the reference signal. In addition, the pulse number of the FG signal in the n cycle period is a value obtained by subtracting the predetermined value N1 from n times the pulse number N0 at the steady speed, Dn = (n × N0−N1).
2. The phase servo circuit for control signals according to claim 1, wherein the capstan motor is accelerated so that 3. When the capstan motor is stopped,
When the number of pulses of the FG signal in the deceleration period becomes equal to the number of pulses N0 in the steady speed, the capstan motor is stopped, and when the capstan motor is started, the steady speed is reached in the n cycle period of the reference signal. 2. The phase servo circuit for control signals according to claim 1, wherein the capstan motor is accelerated so as to reach it.