JPH07107795B2 - Semiconductor device - Google Patents

Description

The present invention relates to improvement of characteristics of a semiconductor device, and more particularly to speeding up charge / discharge operation of various parasitic capacitances in a semiconductor circuit or reduction of excessive current accompanying charge / discharge.

[Conventional technology]

FIG. 2 (a) shows an example in which a conventional signal line charging / discharging circuit is applied to charging / discharging a data line of a dynamic memory. Here, the case where the data line is precharged to half the power supply voltage V _CC is shown. In the figure SA ₀ ~ SA _n
Is a data line D corresponding to the stored information of the memory cell MC,
(D _{0 0} to D _n, general term for _n, same below) in the sense amplifier circuit to be charged and discharged, p-channel transistor Q _SP1 Q _SP2
Amplifier circuit consisting of N-channel transistor
It consists of an NMOS amplifier circuit consisting of Q _SN1 and Q _SN2 . 1 and 2 the sense amplifier circuit driving signal CPS, composed of the charge-discharge circuit of the CSN in the p-channel transistor Q _P and N-channel transistor Q _N. As an example of such a conventional circuit, Japanese Patent Application No. 59-102
There is 530. The operation of such a circuit is shown in FIG.
(B ") will be described with reference to main part operation waveforms. When the word line W rises (e.g. 7V) data lines D corresponding to the information stored in the memory cell MC, and weak signal on are read out. Pulse _P1 , Φ _N Charged to (eg 5V) and drive line CSN When it is discharged from 0V to 0V, the sense amplifier operates and the minute signal on the data line D is amplified to V _CC , 0V. At this time, the current i flowing in the CSP is first observed as a transient current because the parasitic capacitance CP of the CSP is charged. After that, the sense amplifier circuit operates to start charging the load capacitance C _D of the data line. As the voltage of the data line rises, the potential difference from the power supply voltage Vcc becomes smaller. Consequently Q _P of g _m (conductance) is reduced, the current i gradually decreases. As described above, in the conventional circuit, the current waveform at the time of charging / discharging the load capacitance takes a peak value at the start of the operation as shown in FIG. Since the integrated value of is the amount of charge given to the load capacitance, the efficiency is extremely low, the peak current becomes large, or the operation time becomes long.

The problem is that the memory LSI has a large capacity and the drive line CS
This becomes more remarkable when the number of data lines connected to P and CSN increases and the load capacity increases, or when the charge / discharge time is shortened.

[Problems to be solved by the invention]

The prior art described above does not consider the peak current when the memory LSI has a large capacity or has a high speed, and has a problem that the peak current becomes large when the memory LSI has a large capacity and a high speed.

An object of the present invention is to reduce the peak current by increasing the charging / discharging time or maintaining the charging / discharging time constant without increasing the peak current accompanying the charging / discharging of the load capacity.

Especially in the output circuit, it is necessary to reduce the peak current. Regarding the output buffer circuit in which the load capacitance is driven by a plurality of output transistors, Japanese Patent Application Laid-Open No.
There is a publication of 61-109320.

[Means for solving problems]

The above object is a semiconductor device having an output circuit to which a load circuit having a load capacitance is connected, the output circuit comprising a charge control circuit for charging the load capacitance of the load circuit to a predetermined potential. The charge control circuit detects a terminal voltage or a charging current of the load capacitance of the load circuit, and a voltage generating circuit that generates a first voltage and a second voltage different from the first voltage. A circuit, a first comparison circuit that compares the first voltage with a signal voltage output by the detection circuit, and generates a first control signal according to the comparison result, the second voltage, and the first comparison circuit. A second comparison circuit that compares the signal voltage output from the detection circuit and generates a second control signal according to the comparison result, and the load capacitance of the load circuit according to the first control signal. A first drive circuit for charging the Object is achieved in accordance with the control signal by a semiconductor device and a second driving circuit for charging the load capacitance of the load circuit.

[Action]

The detection circuit detects the magnitude of the terminal voltage or the charging current of the load capacitance of the load circuit, and outputs a signal voltage according to the magnitude of the terminal voltage or the charging current. The first and second comparison circuits compare the first and second voltages generated by the voltage generation circuit with the signal voltage, respectively, and according to the comparison result, the first control signal and the second control signal, respectively. Generate a control signal. The first and second drive circuits that charge the load capacitance of the load circuit are driven according to the first and second control signals, respectively. By driving the first and second drive circuits according to the magnitude of the terminal voltage or the charging current of the load capacitance of the load circuit, it is possible to suppress the peak current when charging the load capacitance. Since the driving capabilities of the first and second driving circuits change depending on the terminal voltage or the charging current of the load capacitance of the load circuit, variations in manufacturing conditions of semiconductor devices, usage conditions, etc. As a result, even if the charging characteristic of the load capacitance changes, it is possible to obtain a desired charging characteristic, and the setting of the first and second voltages generated by the voltage generating circuit and the first and second It is possible to obtain an arbitrary charging characteristic by combining the driving capabilities of the second driving circuits.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. The difference from the conventional circuit of FIG. 2 (a) is that one charging circuit is conventionally composed of one transistor, whereas in the present embodiment it is composed of a plurality of transistors Q _P1 to Q _pn. It is that.

The operation of this embodiment will be described with reference to the waveforms of the main parts shown in FIGS. As in the conventional case, when the word line W rises, a minute signal is read onto the data line D. This minute signal is amplified by the sense amplifier circuits SA _{0 to} SA _n . This amplification applies the sense amplifier circuit drive signal CSP by applying _{P 1} to _Pn and φ _N. To V _CC from the charging circuit 1 to CSN The discharge circuit 2 discharges from 0 V to 0 V.
Since the PMOS amplifier circuit composed of Q _SP1 and Q _SP2 and the NMOS amplifier circuit composed of Q _SN1 and Q _SN2 have the same basic operations except for charging and discharging, the PMOS amplifier circuit will be described below. The charging operation by will be described. When a minute signal appears on the data line D, the first pulse φ _P1 is applied to start amplification as shown in (c) of FIG. When (V _th : threshold voltage of PMOS amplifier circuit Q _SP1 ) is charged, Q _SP1 is turned on and charging of the data line capacitance C _D is started. At this time, the capacitance of all data lines D _{0 to} D _n is
Charging becomes extremely slow because it becomes the load of Q _P1 . The drive capability of the drive transistor Q _P1 is determined by the sensitivity of the sense amplifier circuit and the charging peak current of the drive line CSP parasitic capacitance C _P. Next, _P2 , _P3 , and _P4 to _Pn are sequentially applied to charge the data line. At this time, the drive capability of the transistor is Q _P2 ,
Q _P3 …… _Increase in order of Q _Pn , that is, the channel width is W ₂
<By keeping the _{W 3 <W 4 ...... W m} , the charging current i of the data lines, it is possible to speed up the data line charging time without increasing the averaged peak current at each timing. Alternatively, if the charging speed is the same, the peak current can be reduced. The details will be described below.

FIGS. 3 (a), (a ') to (d), (d') are views for more concretely explaining the effect of speeding up or lowering the peak current. In this example, the transistor gate length is 1.5μ, the gate oxide film is 250Å, the data line capacitance is 0.3pF, and the data pair line is 1024. FIGS. 3 (a) and 3 (a ') show the case where the data line is charged by one driving transistor Q _P1 (gate width 1600 μm), and the peak value of the charging current at this time is the parasitic capacitance C _P. It is determined by the charging current. After that, the PMOS amplifier circuit operates and the current gradually decreases as the voltage of the data line increases. Fig. 3 (b) (b ')
Shows the case where the driving is performed by two driving transistors Q _P1 and Q _P2 (gate width 400 μm). Q _P1 and Q _P2 are sequentially turned on and driven, but when _P2 is applied, the charging current due to φ _P1 is large, so the current i ₂ flowing through Q _P2 is made small as shown by the dotted line in the figure, and the peak current It is necessary to prevent the increase of That is, the driving capacity of Q _P2 (channel width W ₂ ) is Q
_It needs to be smaller than _P1 . Fig. 3 (c)
(C ') shows the case of further driving by the driving transistors Q _P1 , Q _P2 , and Q _P3 (gate width 1600 μm). The driving capability of Q _P3 is that when _P3 is applied, the data line potential rises due to the charging operation by Q _P1 and Q _P2 , the potential difference from the power supply becomes smaller, and the charging current becomes extremely small.
Even if it is larger than the drive capacity of _P2 , the peak current does not increase as shown in the figure. 3 (d) and (d ') are
Drive transistor Q _P1 , Q _P2 , Q _P3 , Q _P4 (gate width 2400 μ
(c) and (c ') in the same figure.
Similarly, if the driving capacity of Q _P4 is made larger than that of Q _P3, the speed can be increased without increasing the peak current as shown in the figure.

That is, the charging current to the load capacitance generally has a peak value first when a pulse is applied, and the current value decreases as the voltage increases. In this embodiment, the next pulse is applied when the current value decreases, so that the entire charging circuit operates as if it were a constant current source circuit.

Also, when a pulse is applied, the peak value first appears, and the current value decreases as the voltage rises, but this current i is expressed as i = I ₀ e ^{−t / CR} .

I ₀ : Peak current value R: On-resistance of transistor C: Load capacitance Therefore, by providing a plurality of transistors and sequentially turning them on, the resistance of the entire charging circuit becomes smaller and the current decreasing speed becomes faster. This is also clear from the fact that the rate of decrease of i increases as the number of transistors increases, as shown in FIGS. 3 (a) to 3 (d). As a result, more ideal constant current driving becomes possible.

Thus Q _P1, Q _P2 drivability of ...... Q _Pm and when charging a plurality of transistors Q _P2 i.e., than its channel width W _2, to increase the channel width W ₃ of the channel width W ₃ of the Q _P3. That is, by maintaining the relationship of W ₂ <W ₃ <W ₄ ... W _m , the speed can be increased without increasing the peak current. Alternatively, the peak current can be reduced by setting the charging time to be the same as in the case of using one transistor. In the description, charging is described, but discharging can be similarly speeded up or reduced in peak current.

Although the embodiments for efficiently charging and discharging the load capacity have been described above, the efficiency is further improved by detecting the load capacity terminal voltage or the charging / discharging current during charging / discharging operation and controlling the operation accordingly. It is possible to perform a desired charging / discharging operation such as. FIG. 4 shows one of the embodiments.

In the figure, C _L is the load capacity that is the target of charge / discharge operation, and corresponds to the drive capacity C _P , the data line capacity C _D, etc. in FIG. OB
S is a detection circuit of the terminal voltage V _L of C _L or the charging / discharging current i _L , and outputs a signal V _OBS corresponding to V _L and i _L. Here, i _L can be detected by inserting a minute resistor in the current path and detecting the voltage across it. CMP compares the output V _R1 ~ V _Rm of the function voltage generator GEN with V _OBS , and V _OBS is V _R1 ~
Signals φ _Cm to φ _Cm are output when a predetermined condition is satisfied such that V _Rm is equal to or more than V _Rm or less. Here,
The signal form of V _OBS , V _R1 and V _Rm may be DC or AC voltage or current. DRV ₁ ~ DRV _m is φ _{C 1} ~
This is a drive circuit that operates according to the φ _Cm instruction. The load capacitance C _L is driven by the output of the drive circuit, but in addition to the direct drive as shown in the same figure, an arbitrary circuit as shown in FIGS.
A form in which _CL is driven via ABC is also conceivable. phi _S is a signal for controlling the operation, here illustrated as charging and discharging operation start signal C _L. Although the control signal is input only to the CMP, it goes without saying that a predetermined signal is also input to other circuits if necessary. It is omitted here for simplification of the drawing.

Figure 4 (b), and (c) shows the configuration of the above, voltage when charging the C _L desirable positive voltage from OV, for example, to the power source voltage V _CC, the current waveform. Note that when OBS is configured so that V _OBS is equal to V _L (for example, C _L end and C _L
MP input end is directly connected) is illustrated. Also, V _R1
~ V _Rm is set as V _R1 = 0 V _R2 ...... <V _Rm <V _CC , and CMP _{1 to} CMP _m are φ _C1 to φ _Cm when V _OBS becomes the corresponding V _R or more. Is output.

Now, when φ _S is input at time t ₁ , the CMP starts operating. Since V _R1 = 0V is set now, immediately φ
_C1 is output and DRV ₁ starts operating. This starts charging C _L , and V _L and V _OBS rise in the positive direction. The current i _L also increases rapidly. As V _L rises, V
_Since the potential difference between _CC and _CC is small, the drive capability of DRV ₁ is generally small. This is because DRV ₁ is like 1 in Figure 1.
It is easily inferred when considering the case of being composed of a MOS transistor or a combination of a resistor and a switch. As a result, i _L gradually decreases, and the rate of increase of V _L also decreases. However, when the V _L ie V _OBS is greater than V _R2, the phi _C2 is outputted by CMP _2, DRV ₂ is operated. This gives C _L
Is driven by DRV ₁ and DRV ₂ , i _L becomes large again, and the increase rate of V _L also becomes large. After that, the same operation is repeated, and when V _L reaches V _CC , i _L becomes 0 and the charging operation ends.

According to the above-described embodiment, the driving condition is controlled according to the terminal voltage of the load capacitance C _L , so that extremely accurate charging / discharging operation can be performed. That is, in the embodiment shown in FIG. 1, the method of predicting the charge / discharge characteristics of the load capacity and reinforcing or increasing the drive capacity at every predetermined time interval is adopted. to control the drive capability in accordance with the terminal voltage of C _L, for example variations in the manufacturing conditions of the semiconductor device, such as by the use conditions change, also the charge-discharge characteristics are changed, it is possible to obtain the desired charge and discharge characteristics become. This will reduce transient current in a short time.
It becomes possible to perform charging and discharging operation of the C _L. Further, it becomes possible to realize an arbitrary charge / discharge characteristic by combining the outputs V _{R1 to} V _Rm of the function voltage generating circuit and the driving capabilities of DRV ₁ to DRV _m .

In the figure, DRV can be constituted by MOS transistors as shown in 1 of FIG. 1, and GFN and CMP are shown in FIGS. 5 to 14 of Japanese Patent Application No. 58-153308. It can be used as is. Also, It OBS may be directly connected to the input pin of the CMP of C _L, MOS optionally
A transistor source follower circuit, a bipolar transistor emitter follower circuit, or a well-known multiplication amplifier may be used.

In addition, in order to operate the first DRV ₁ in this example,
Although V _R1 = 0V is set, it goes without saying that the value should be set according to the initial voltage at the start of operation. However, in such a method, there is a mismatch between the initial value and V _R1 such as CMP. If the initial value and V _R1 deviate to the extent that does not operate, it is expected that the operation will not start forever. In that case, there is also a method in which a drive circuit DRV ₀ dedicated to the initial operation is separately provided without adding CMP as shown by a broken line and is directly activated by φ _S. According to this method, there is no problem such as malfunction.

FIG. 5 shows another embodiment for controlling the operation by detecting the operating state of the load, and FIG. 4 shows a conversion circuit CON ₁ between OBS and CMP.
The difference is that ~ CON _m is added. CON _{1 to} CON _m are for inputting to CMP after performing arithmetic processing such as reduction / increment / decrement or differentiation / integration on V _OBS according to the purpose, and realize more arbitrary and highly accurate charge / discharge operation compared to Fig. 4. it can. In this embodiment, CON is provided for each CMP, but it is also possible to collectively provide only one or for each group.

FIG. 6 shows the CMP of FIGS. 4 and 5 as a CMOS transistor,
That is, p-channel MOS transistor (Q _{26 etc.} ), and N
This is a specific example configured by using a channel MOS transistor (Q _{21, etc.} ). Bias circuit for the first stage differential amplifier with Q _{21 to} Q ₂₇ , first stage differential amplifier with Q _{28 to} Q ₃₉ , second stage differential amplifier with Q _{41 to} Q ₄₉ , and third stage differential amplifier with Q _{50 to} Q ₅₄ Are configured.
Control signal φ ₃ is high voltage (V _CC ), _C is low voltage (0 V)
The starts operating, V _OBS to outgoing phi _C <V _R at low V oltage, V
And outputs a high voltage in the _OBS> V _R. It is needless to say that the input connection should be made in consideration of the phase relationship of the entire circuit using this circuit. According to this configuration, since differential amplifiers using CMOS are connected in multiple stages, it is possible to realize CMP with low power consumption and high sensitivity (high discrimination ratio), and it is possible to improve the accuracy of charge / discharge operation.

FIG. 7 is an example in which the embodiment of FIG. 4 is applied to the data line charging / discharging operation of the memory LSI as shown in FIG. The structure and method of the memory array section are the same as those in FIG. According to the present embodiment, as explained in FIGS. 1 and 4, the potential of CSP rises and V _OBS rises, and CMP ₁ rises accordingly.
~ CMP _m operates to generate φ _C1 ~ φ _Cm . by this
Q _{P1 to} Q _Pm (each corresponding to drive circuits DRV _{0 to} DRV _m in FIG. 4) are turned on sequentially, and the same operation as in FIG. 1 (b) is performed with higher accuracy. Here, φ _C1 ~ φ
_{Since Cm} is a p-channel MOS transistor from Q _{P1 to} Q _Pm , CM should be set to a low voltage (0V) when V _OBS exceeds V _R.
Not to mention configuring P1. Also in this embodiment, a drive circuit dedicated to the initial operation, such as DRV ₀ shown in FIG. 4, can be provided. Also, here, the first
In order to clarify the correspondence with the figure, Q _P1 as DRV ₀ to DRV _m
The whole ~ Q _Pm is collectively shown as the charging / discharging circuit 1 in FIG. The channel widths of Q _{P1 to} Q _Pm may be determined by the same idea as in FIG. 1 in order to obtain the same characteristics as in FIG.

Each of the embodiments described above is a system in which a plurality of CMPs, DRVs, etc. are provided and the charging / discharging characteristics are controlled discretely (digitally) by turning them on and off, but this is continuous (analog). There is also a method to control. FIG. 8 shows the embodiment. In the figure, each circuit has the same function as each of the above-described embodiments, but the subscript a indicates that it has an analog operation function. ABC is an arbitrary circuit inserted in the route from DRV _a to C _L according to the application in the figure, and the sense amplifier SA shown in FIG. 1 corresponds to this, for example.
In the present embodiment, the charging / discharging operation of C _L is started at the same time as the input of φ _S , and thereafter, the charging / discharging operation is performed according to the closed-loop characteristics composed of CMP _a , DRV _a , ABC, OSB _a , and CON _a. Is performed.
By arbitrarily setting the characteristics of this closed loop, for example, the operation characteristics shown in FIG. 4 can be realized. According to the present embodiment, since the control can be performed by one set of circuits, the charging / discharging operation can be arbitrarily controlled without lowering the integration degree of the semiconductor device. Further, since the control is continuously and smoothly performed, problems such as noise generation can be eliminated.

FIG. 9 is one of the more preferable embodiments of the above-mentioned embodiment, in which a pseudo load capacitance C _LM is added to the circuit ABC _M in order to detect the load end voltage or the drive current at the time of charge / discharge operation. It differs from FIG. 8 in points. According to the present embodiment, there is an advantage that the operating state can be detected without disturbing the actual charging / discharging operation of the load capacitance C _L. Further, by changing the response of the pseudo circuit to that of the actual circuit section, the degree of freedom in controlling the charging / discharging operation can be further increased.

FIG. 10 shows an embodiment in which a drive circuit DRV _aM dedicated for driving the above pseudo load capacitance C _LM is added. In this embodiment, the degree of freedom in control can be increased more than that shown in FIG. 9 and, at the same time, the disturbance to the actual circuit can be further reduced. Also, as shown by the broken line in the figure, it is of course possible to add CON _aM and CMP _aM dedicated to the pseudo load, further increasing the degree of freedom of control,
The disturbance to the actual circuit can be reduced.

The method of adding the pseudo load capacity as described above can be applied to the various embodiments described above.

FIG. 11 shows an example in which the above-described continuous control method is applied to the data line charging operation of the memory LSI as shown in FIG. The structure and method of the memory array section are the same as those in FIG. In the figure, D _M , _M , and SA _M are pseudo data lines and pseudo sense amplifiers for detecting the operating state of the load.
Corresponds to C _LM and ABC _M. In addition, when amplifying a small signal by the sense amplifier described above, D _M is always low voltage, _M
Is designed to have a high voltage. This can be achieved by writing predetermined information in the memory cell MC in advance, or by designing the transistor constants constituting the SA _M , the data line capacitance C _D, etc. in an unbalanced manner. MOS transistor Q
_P and Q _PC correspond to CON _a CMP _a and DRV _a in Fig. 8, here D _M
Is supplied as V _OBS directly to the gate of Q _PC . Further, the circuits of Q _P and Q _PC also correspond to the charging circuit 1 of FIG. Here, g _m (conductance) of Q _P is g of Q _PC
It is designed to be much larger than _m .

FIGS. 7B and 7D show the voltage and current waveforms of the above embodiment. When φ _N becomes a high voltage and _P becomes a low voltage almost at time t ₁ , Q _P and Q _N turn on. This allows D _M , _M
Respectively Then, it starts descending and rising toward 0V and V _CC . At this time, the other data lines and drive lines operate similarly as described above. The voltage of the drive line CPS, the data line that should have a high potential according to the memory cell information, and the voltage of _M rise with the time constant determined by g _m of Q _PC and load capacitances C _P and C _D. since the potential difference between the V _CC decreases and, Q _PC of g _m
Tries to get smaller. However, at this time, the voltage of D _M , which is the gate voltage of Q _PC , drops toward 0 V, so Q
The gate voltage of _PC gradually increases to compensate for the decrease in g _m described above. Therefore, g _m is kept almost constant. As a result, the current i is kept constant, and the data line charging operation can be performed efficiently as in the case described with reference to FIG. Data line voltage at time t ₂
When it reaches V _CC , the current i becomes zero. Note that here Q _P and Q _PC
May be rearranged and connected to the Q _PC and V _CC sides.

As described above, according to the present embodiment, efficient charging operation can be performed with a simple circuit configuration. Although the charging characteristic in this embodiment can be controlled by the operating characteristic of D _{M and} the characteristic of Q _PC , the degree of freedom of control can be further increased by providing an appropriate conversion circuit as shown in FIG. Also, D _M
Since the gate of Q _PC is connected to, but there is a possibility that the operating characteristics vary significantly with the other data line, in which case the OB
This can be solved by inserting S between D _M and Q _PC , or by designing the SA _M transistor constant to be larger than the others. When adding D _M , _M , and SA _M to disturb the operation of the actual circuit, a circuit similar to 1 may be separately provided as a pseudo drive circuit as shown in FIG. .

According to the embodiments of FIGS. 8 to 11 described above, the charge / discharge operation can be continuously controlled with a small number of circuits. In these embodiments, the comparison circuit CMP _a operates as a simple amplification circuit or a signal conversion circuit, but by inputting a comparison signal separately, a higher degree of operation control becomes possible.

FIG. 12 shows an embodiment thereof, in which GEN _a generates a comparison signal V _Ra . In this embodiment, the charging / discharging operation of C _L is V _Ra
It can be controlled by the characteristics of. That is, in such a circuit form, the total gain (amplification factor) of CMP _a DRV _a is sufficiently large, and assuming that the transfer coefficient of OBS _a and CON _a is β, the relationship between V _Ra and V _L is Can be expressed as Note that here V _Ra to CMP _a , CON _a
The output input must be connected so that the closed loop feedback of CMP _a , DRV _a OBS _a , and CON _a is negative feedback. For example, if DRV _a OBS _a and CON _a both have a positive transfer coefficient, the output of CON _a is the negative input terminal of CMP _a (when the input increases in the positive direction, the output becomes negative as shown in Fig. 12). V _Ra must be input to the positive input terminal (the input terminal where the output increases in the positive direction when the input increases in the positive direction), DRV _a , OBS _a , or CON _a If one or all of them have a negative transfer coefficient, the input may be reversed. For more information on this, see Electronic Circuits Digital and Analog by CHARLES A.HOLT.
gital and Analog) John Williman Sands (JOHN W
ILEY & SONS) company issue. Therefore, FIGS. 12 (b) and 12 (c), in which V _L can be arbitrarily controlled by V _RA , are operating waveforms of large voltage and current for explaining an example of the operation. Here, β is assumed to be a constant positive real number, and when φ _S is applied at time t ₁ , GEN _a starts operating, and V _RAM is the maximum value, and is proportional to the solid line that is directly proportional to time or the square of time. It shows an example of emitting V _Ra like the broken line. Since β is a constant real number, a waveform similar to V _Ra (1 / β times) is output to V _L , as is clear from equation (2). Since V _L is the terminal voltage of the capacitance C _L , the current
i _L is obtained as the differential value of V _L, the current waveform shown in FIG. Therefore, by controlling V _Ra , V
_{The L} or i _L waveform can be set arbitrarily. That is, V _Ra should be generated according to the desired V _L or i _L. At this time, if β is set to a value smaller than 1, V _Ra can be set to a voltage value smaller than V _L , and this can be easily generated. For the generation, an arbitrary V _Ra can be generated by adding a differential circuit by resistance and capacitance, an integrating circuit, and an operational amplifier. An example of these is given in the previous article, Electronic Circuits Digital and Analog. Although the method of constructing CMP _a is also described in this book, the circuit shown in FIG. 6 can be used as it is. At this time, it is needless to say that it is desirable to use the operating range in the linear region as much as possible.

As described above, according to this embodiment, it occurs in CEN _a .
And more precisely arbitrarily set the charge and discharge characteristics of the C _L by V _Ra. In addition, charging and discharging of a larger load capacity can be performed at high speed with low transient current.

Although the details of the present invention have been described with reference to the embodiments, the scope of application of the present invention is not limited to these. For example, although the case where the precharge level of the data line is V _CC / 2 is shown here as an example, the principle of the present invention can be applied even when the precharge level is any other value. Further, the target of the charging / discharging operation is not limited to the data line, but can be applied as it is to the charging / discharging operation of other general load capacitances. For example, it can be used for controlling charge / discharge operation of a signal line connected to a large load capacitance such as an output of an address buffer circuit of a memory LSI or a microcomputer LSI.

In addition to this, the load capacitance may be provided outside the chip of the semiconductor device instead of inside the chip. Also, as the main component of semiconductor devices
Although the CMOS example has been described, the present invention is also applicable to the case where it is configured only by n-channel MOS transistors or p-channel MOS transistors, or other bipolar transistors, and devices configured using semiconductors other than silicon, such as GaAs. it can. Also, the memory LS mentioned above
It is obvious that it can be applied to general LSIs other than I and microcomputer LSIs. Further, the main object of the present invention is to
As described in the description of each embodiment, the charging / discharging operation of a large load capacity is performed at a high speed with a low transient current, but another application is possible. For example, in a memory LSI with a multi-bit configuration that has multiple data input / output terminals, in order to reduce transient current noise that occurs when charging / discharging the external load capacitance added to the data output terminals, To reduce the charging / discharging speed collectively, control using the embodiment shown in Fig. 12 to reduce the transient current, or control the charging / discharging speed for each data output terminal as needed. Thus, the total transient current can be reduced. Such a method can be used not only for controlling memory LSIs but also for controlling charge / discharge characteristics of output terminals of logic LSIs such as microcomputer LSIs.

〔The invention's effect〕

According to the present invention, there is an effect that the peak current can be reduced by increasing the charging / discharging time or increasing the charging / discharging time without increasing the charging / discharging peak current.

[Brief description of drawings]

FIG. 1 (a) is one embodiment of the present invention, and FIG. 1 (b)-
(D) is a main part operation waveform of FIG. 1 (a), FIG. 2 (a) ~
(D) is a conventional example and its operation waveform, FIGS. 3 (a) to (d1).
FIG. 4 is a diagram for explaining the effect of the present invention. 4 to 12 show another embodiment of the present invention. 1 ...... charging circuit, CSP, CSN ...... sense amplifier drive line, C _P C
_N ... drive line capacitance, Q ... transistor, D ₀ , ₀ ... D _n ,
_n …… Data line, C _D …… Data line capacity, W …… Word line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun Eto 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Katsutaka Kimura 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Hitachi Ltd. (56) Reference JP-A-52-147934 (JP, A) JP-A-61-109320 (JP, A)

Claims (3)

[Claims] 1. A semiconductor device having an output circuit connected to a load circuit having a load capacitance, the output circuit comprising a charge control circuit for charging the load capacitance of the load circuit to a predetermined potential. The charge control circuit detects a terminal voltage or a charging current of the load capacitance of the load circuit, and a voltage that generates a first voltage and a second voltage different from the first voltage. A generation circuit, a first comparison circuit that compares the first voltage with a signal voltage output from the detection circuit, and generates a first control signal according to the comparison result, and the second voltage. A second comparison circuit that compares the signal voltage output by the detection circuit and generates a second control signal according to the comparison result, and the load of the load circuit according to the first control signal. A first drive circuit for charging a capacity; Wherein a and a second drive circuit for charging the load capacitance of the load circuit in response to the second control signal. 2. The first and second drive circuits respectively include first and second transistors having a source / drain path provided between the predetermined potential and the load circuit. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the load circuit is located outside the semiconductor device.