DE2719726A1 - Semiconductor data store with MOS switching transistors - has matrix of storage cells in rows and columns and read amplifier arranged in centre of each column - Google Patents

Abstract

Semiconductor storage arrangement has matrix of storage cells in rows and columns and read amplifier with two driver transistors. The read amplifier is arranged in the centre of each column. The two driver transistors are transversely coupled. Several switch components are connected to the terminals of the driver transistors, which are opposite to the terminals connected to the column. The switch components are connected in such a way that in the activated stage they apply the driver transistors to a reference potential. At a given point in time only two 1K blocks are selected by means of a decoder (28).

Description

Storage arrangement

The invention relates to semiconductor memory devices, and in particular a sense amplifier for an N-channel MOS memory with memory cells, in which a transistor is used.

In the production of digital arrangements, especially small computers, MOS random access memories (RAM) are widely used. D # capabilities and the cost benefits of such memory arrays have continued to grow in recent years increased. The cost per memory bit increases with MOS random access memories in the same way as the number of bits or memory cells per unit increases. Increasingly large random access memories are standard building blocks in the industry become, for example, 256 bit memory, 512 bit memory, 1024 bit memory and now 4096 bit memory. For example, a direct code processor with 4096 bits is in U.S. Patent 3,940,747. It is currently used by manufacturers of semiconductor components tries to produce random access memory with 16,584 bits, so-called 16K RAM's len; d.lZU to the magazine "Electronics" from February 1976 pages 11 1 1 referenced When the number of bits in a semiconductor chip increases, the cell size decreases, and inevitably the size of the storage capacitor also increases smaller in each cell.

Also the number of cells on a point line in the cell matrix increases so that the capacity of this line increases. These factors set the Decreases the size of the data signal present on a point line. A full digital one Level, i.e. the difference between the signal value 1 and the signal value "O" in one of these structural units, for example, be 10 or 12 volts. The voltage difference between a signal value ~ 1 "and a signal value" O "for the at one point iteration in the memory matrix from the selected cell coupled with a transistor However, data can only be one or two tenths of a volt. To read this Various circuits have been proposed for low level signals. For example, sense amplifiers are disclosed in the aforementioned US Pat. No. 3,940,747, US Pat U.S. Patent 3,838,404, Electronics magazine, Sep. 13, 1973, Volume 46, No. 19, pages 116 to 121 and in "IEEE" journal of Solid State Circuits ", October 1972, Page 336.

When applied to storage devices that have a high packing density, require high operating speed and low power dissipation, such as as required in the 16K random access memory are those proposed above Sense amplifier associated with disadvantages.

Some have a high power loss and excessively long charging times for the managerial staff. Others require a high instantaneous current and a critical one Cycle time control.

With the aid of the invention, a sense amplifier for a MOS random access memory is thus intended be created that have a low power dissipation and a high operating speed and has high sensitivity.

The sense amplifier constructed according to the invention makes two Cross-coupled driver transistors use that as a bistable circuit are connected and arranged in the middle of each column line in the memory matrix are. Load transistors for the two driver transistors are only used during one Clocked part of the work cycle; during this time the cells are addressed. The driver transistors are connected to ground via two different paths, the are formed by two transistors clocked at different times. While an initial read period, the current through the driver transistors is on is kept at a low value, and it can then later be higher, so that an output signal is generated with the size of the full digital level.

The invention will now be explained by way of example with reference to the drawing. 1 shows a block diagram of a semiconductor memory device in which the invention can be applied, Fig.2 is a perspective view of the Device of Figure 1 in a housing, Figure 3 is an electrical circuit diagram of a Memory cell array used for the system of Figure 1 the sense amplifier according to the invention, Fig.4a to Fig.4f graphic representations of the tensions appearing at various points of the system according to the invention as a function of time, Fig. 5 is a graphical representation of various voltages and power loss factors in the circuit according to the invention as a function from the component shape, Figure 6 shows an accurate graphic representation of the voltage the control lines of the circuit. of Fig.3 as a function of time and Fig.7 a greatly enlarged photograph of a semiconductor chip with the invention System.

In Figure 1, a MOS memory device is shown in which the Invention can be applied. The storage device may be various Have sizes, but the invention is suitable for application to a memory with very high packing density with 16 384 memory cells on a silicon chip with a Area of 0.32 cm2 (1/20 inch2) determined by means of the N-channel silicon gate MOS process manufactured with self-alignment that resulted in the production of 4096 bit storage devices according to Electronics magazine dated September 13, 1973, as above has been mentioned. The storage device consists of a matrix 10 of 16,384 Memory cells commonly used in 128 rows and 128 columns divided are; each cell is a so-called single transistor cell, as described in US Pat 940 747 or in the magazine Electroics of September 13, 1973. In this embodiment, the matrix 10 is divided into 16 1K blocks marked with 10-1 to 10-16 are designated. Two blocks each, for example blocks 10-1 and 10-2 act as a reading unit. A row decoder 11 selects one of the 128 Row lines determined by a row or X address specified in a 7-bit line address buffer 12 is included; a column decoder 13 selects one of 128 column lines separated by a column or Y address in a 7-bit column address buffer 14 is included. These addresses are about seven Address lines 15 applied to the semiconductor chip in the time division method. A line address scan input 16 (RAs) enables the line address buffer 12 so that it accepts a line address, contains address bits A0 through A6; in the same way there is a column address scan input 17 (CAS) frees the column address buffer so that it can extract a column address from the Bits A7 through A13 from lines 15 assumes. For the unambiguous definition of a bit out of 16 384 cells 14 16 384) 14 address bits are required; an input / output control circuit 18 is via the column decoder 13 and intermediate output buffer 19 to the matrix 10 connected; it works so that from a data entry pen 20 data to the Column lines are applied or that data is detected on the column lines and to a data output pin 21 under the control of a read / write input 22 (rad) and under the control of various internally generated Clock and logic voltages are applied. The assembly requires several pins 23 different supply voltages; they are the supply voltages Vbb, Vcc and Vdd and ground Vss. Of course, some circuits are also designed so that they with one or two supply voltages instead of the three mentioned supply voltages work. Typical voltage values are: Vdd = + 12V, Vbb = -5V and Vcc = + 5V. As can be seen in Figure 2, the unit of Figure 1 has the shape of a silicon chip 24, which is in a housing 25 with 16 connection pins 26 corresponding to those mentioned above 16 input and output lines is housed.

Thin gold wires connect contact areas on the silicon chip 24 with internal connections of pins 26.

A cover, not shown, seals the structural unit. The case 25 is about 18 mm (3/4 inch) in length, making a large number of these housings can be mounted on a standard size printed circuit board. For example, a small computer can be a whole on a small circuit board 32K or 64K word memory (16 bits per word) included.

In the memory device of Fig. 1 are at a given point in time only two of the 1K blocks 1-10 to 1-16 selected. This selection is made with the help of a Decoder 28 achieved, depending on the address bits A6, A12 and A13 one of the selects eight lines 29 (29-1 to 29-8).

The decoder 28 receives these three address bits as inputs, where the address bit A6 from the row address memory circuit 12 and the address bits A12 and A13 from the column address storage circuit 13 come.

It is important that the row decoder 11 is in the middle of the Matrix rather than at one end. The traditionally designed decoder 11 causes the selection of one of 128 row lines; a row line is one Line formed from polycrystalline silicon, which extends over about half the width of the silicon chip and the gate electrodes of 128 MOS transistors in controls the 128 memory cells assigned to this row. thirty-two Lines 11-1 thus lead to the quadrant containing block 10-1, thirty-two Lines 11-2 lead to blocks 10-2 etc., thirty-two lines 11-3 lead to the quadrant with the block 10-15 and thirty-two lines 11-4 lead to the quadrant with the block 10-16.

The RC delay of a line 11-1 that is up to half the width of the Matrix ranges is obviously less than when it extends over the whole Matrix width would extend. The seven address bits A0 to A6 in the row decoder 11 select a row line so that the signal applied to it has a high value accepts. The address bit A6 selects the left or the right side, i.e. it allows the activation of lines 11-1, 11-2 or lines 11-3, 11-4.

The address bit AS selects even or odd; It means that when the lines 11-1, 11-2 are selected by the address bit A6, the address bit AS makes a choice between lines 11-1 and 11-2.

The address bits A0 through A4 then select one of the thirty-two lines in the selected quadrant. The address bit AS definitely too the activation of dummy cells in the unselected side via dummy cell addressing lines 27, as will be explained.

According to the invention, the memory device of Figure 1 includes in the Middle of each column line sense amplifiers 30, which detect the low signal value, which is generated when addressing a cell on the column lines, and these convert low signal value into a full digital level.

A sense amplifier 30 designed according to the invention is shown in FIG shown in matrix 10. The sense amplifier 30 basically consists of one bistable circuit, namely a flip-flop, with two cross-coupled driver transistors 31 and 32 with assigned load transistors 33 and 34. Two circuit points 35 and 36 are connected to the respective booklets 37 and 38 of the column line. These nodes 35 and 36 are connected to the gate electrodes of the other respectively Transistors 31 and 32 connected so that the circuitry with the cross-wise Coupling arises.

With line 37, which is one half of a column line, are thirty-two cells 40 connected; the same applies to line 38. Each cell consists of a transistor 41 and a capacitor 42. The gate electrode of the Transistor 41 is controlled by a row line 43, which is also called the word line or X-line is designated; Each row line is made up of 128 gate electrodes Transistors 41 connected.

In the entire matrix 10 there are 64 row lines 43, from each of which is 32 on one side of each sense amplifier; it is natural 256 sense amplifiers 30 are available, so that only a very small part of the matrix in FIG 10 can be seen. Each sense amplifier has two dummy cells 44, of which one on each side of the amplifier and with the column lines 37 and 38 is connected. The dummy cells are designed in the same way as the memory cells 40; they contain transistors 45 and capacitors 46. Via lines 47, the Transistor 45 in the dummy cell row on the opposite of the selected cell 40 Side of the sense amplifier switched on, the address bit AS of the row address what is determined simultaneously with the addressing of the selected memory cell 40 takes place. The column lines 37 and 38 are connected through a transistor 49 to one Reference voltage line 48 applied; the gate electrodes of these transistors 49 become driven by the clock signal 7. This causes the lines 37 to be charged equally and 38 to a voltage value which is selected to be approximately Vdd - 2Vt. The load transistors 33 and 34 are applied to the voltage Vdd, and they are activated by a clock signal # 4 controlled, which is shown in the timing diagram of Fig.4. The flip-flop with the transistors 31 and 32 can operate when clock # 4 goes positive and the transistors 33 and 34 makes conductive and if one is connected to the drain electrodes of the transistors Circuit point 50 is connected to ground.

According to the invention, the circuit point 50 is separated.

th paths to ground, in this case the three transistors 51, 52 and 53 controlled by clock signals # 1, # 2 and # 3. the Transistors 51, 52 and 53 have different dimensions, so that the through the current flowing from node 50 to ground is different, so that the voltage at node 50 is also dependent on it changes which of the transistors 51, 52 and 53 is turned on. With these three Transistors, the transistor 51 has the smallest dimensions, while the transistor 53 has the largest dimensions.

The advantages of this arrangement will be demonstrated when examining the sensitivity and power loss relationships for the sense amplifier of FIG. 3 can be seen.

When the clock signal # 4 becomes positive, a read operation is triggered and the flip-flop goes into a stable state in which the transistor 31 is conductive and the transistor 32 is blocked or vice versa. The direction of switching depends on the voltage difference on lines 37 and 38, which in turn depends on whether the value "1" or "O" was stored in the selected memory cell Voltage value than is applied to the other, a slightly higher voltage value is present at the gate electrode of one of the transistors 31, 32, so that when the clock signal 4 changes to a positive value, one transistor conducts more current than the other. A sensitivity figure of merit S of the sense amplifier 3 can be expressed with the currents Id and Id 'through the transistors 31 and 32 as follows: which merely means that the sensitivity of the sense amplifier is greater, the greater the difference in the currents. At a given point in time t = to this can be expanded as follows: this is roughly the same where applies K = K '(W / L) Vt: threshold voltage of transistors 31 and 32, Vd: drain voltage of transistors 31 and 32 at connection points 35 and 36 Vo: voltage at connection point 50 W: channel width of transistors 31 and 32 L: Channel length of transistors 31 and 32.

It can be seen from this that the sensitivity S at a fixed voltage Vd improves with an increase in voltage Vo.

In Fig.5 it is shown how the value of the tension changes with the width / length ratio of transistor 51 changes. As expected, the voltage drop across transistor 51 is high when its channel width is small compared to the channel length.

Assuming that Vd - Vt = 5 volts, then the sensitivity figure of merit S can be improved by 50% if the width / length ratio of the transistor 51 is decreased from 0.1 to 0.05. In the case of a memory with a high packing density, an increase of 5096 is of great importance since the storage capacitor 42 is in the Cells 40 can be enlarged proportionally, resulting in a higher packing density the silicon chip results.

The circuit of Fig. 3 also results in an improvement in the operating speed Due to a high voltage Vo, the precharge voltage tries on lines 37, 38 or the nodes 35, 36 for the signal value Pi to remain high. In contrast The sense amplifier of FIG. 3 results in a minimum compared to the sense amplifiers which have been customary up to now Charging time for lines 37, 38 to refresh a signal value ~ 1 ", since the Node of the sense amplifier that should remain at the value n1 n while is not discharged to a low voltage during the reading process.

In Figure 6, the voltage on the lines 37, 38 is dependent represented by the time when clock signals # 1 and p2 are turned on. While the Time period 54, the voltages on lines 37, 38 are before the highs of the Clock signals 91 are balanced to about Vdd-2Vt as determined by the charge on the line 48 is established. At time 55, the clock signal # 1 assumes a high value, and one of the lines 37, 38 begins to discharge towards the signal value O, while the other line is only slightly discharged, like lines 56 and 57 reveal. In the course of the time interval 58 before the switch-on time 59 of the clock signal # 2, the node 35 or the node is discharged 36, which should be at the value ~ 1 ", not very far below the value Vdd-2Vt, and he soon begins to turn on the transistor 33 or the transistor 34 again Charge value 1 as long as clock signal # 4 is high. The value ~ 1 " is at a voltage of about Vdd-Vt, and there is some level 60 that is an acceptable level at which the chip enable signal can be disabled. Since curve 56 does not go far down, level 60 is compared to that Reached the case very quickly, which would occur if the "1" side of the sense amplifier as with previously used circuits could have discharged to a low value.

With regard to the power loss, the sense amplifier of FIG an improvement, since the power dissipation Ps per sense amplifier is given by the relationship Ps = Vdd ~ Id = Vdd. K '(Vd - Vo - Vt) 2 (W / L) expresses; FIG. 5 gives the values for the power loss Ps with a change in the width / length ratio at. For a low width / length ratio, the power dissipation Ps a low value.

The use of a small width / length ratio for the transistor 51 would have the consequence that the reinforcement of the #O "-side due to the fact that that the voltage Vo is high would be insufficient. Because of this, the transistor is 52 is provided so that further reinforcement is achieved. The transistor 52 becomes at a later time than transistor 51 is activated by clock signal # 2, which the conductive state of the load transistors 33 and 34 through for the refreshing process Termination of clock signal # 4 ended. In this way is on line 37, 38, which should have a low value, give a good "O" value.

During a read or write process, the transistor 53 is with Activated by means of clock signal # 3; this transistor is much bigger than that Transistors 51 and 52. During the # 2 and # 3 periods, clock signal # 4 remains high for the read / write operation so that load transistors 33 and 34 are turned on will. Noise signals from other circuits occur during the read or write processes on, so that the load transistors must remain switched on, so that a reliable Operation is guaranteed. For the selected column line 37, will also a Transmission element 65 made conductive, so that this line with a collecting line 66 is connected to an input buffer 67 or an output buffer 68 of the Input / output control circuit 18 leads. This manifold 66 has accumulated Capacities and interference signals. The high digital provided by the large transistor 53 Level is therefore of great advantage.

As explained above, the matrix is organized into two 8K matrices, which are shown in Figure 1; one of these matrices contains blocks 10-1 through 10-8, while the other contains blocks 10-9 through 10-16. The row decoder 11 is placed between the two 8K matrices, so the length and thus the RC delay of the row select lines made of polycrystalline silicon to a minimum is decreased. Each 8K matrix contains 128 balanced sense amplifiers 30 in the Center of the respective matrix, with each side of the sense amplifier thirty-two Cells 40 are connected. During operation, the address bit A6 is only used an 8K matrix selected so that only 128 sense amps are active; this means, that the decoder 28 a clock signal # 4 during the initial period 70 of Figure 4b generated only on four of the lines 29, so that the load transistors 33, 34 only at the sense amplifiers on one side of the row decoder 11 are turned on. To improve the signal sampling for the cells formed by a transistor Each 8K matrix is in four 2K matrices (10-1 with 10-2 etc.) or in pairs of 1K blocks further subdivided, each block pair containing thirty-two sense amplifiers 30 and together with another Block pair an intermediate output buffer 19 shared.

The intermediate output buffer 19-1 operates on the pair of blocks, for example 10-1, 10-2 and the block pair 10-3, 10-4 together. Select address bits A12 and A13 one of the four 2K matrices in a column decoder 13 for output via the Line 19-5 and the input / output control circuit 18 off. The decoders 13 in the left half are duplicates of the decoders in the right half as there are two There are groups of 128 column lines; the spatial arrangement (lay-out) is designed in such a way that this doubling is necessary.

At the beginning of a read cycle, four pairs of blocks 10-1, 10-2, etc. switched on by means of the clock signals # 1 and # 4 according to FIG. this makes 128 bits refreshed, for example the bits on one of the row lines 11-1.

Since the transistor 51 is quite small, the power dissipation is at this refresh operation is limited to a useful value. The duration of this Refresh operation is short because the "1" #voltage value 56 on the row line is not drops to a low voltage value, as can be seen in Fig. 6. For the All clock signals # 4 are switched off, as in Figure 4b during the refresh cycle Time interval 72 can be seen, and the clock signal # 2 takes a high value as Fig.4d shows.

In the special embodiment, the input of the signal takes place CAS across terminal 17. The additional current through transistor 52 during the duration of the clock signal # 2 ensures a good "O" value in a short time of the row line 37, 38. When the row line 38 with the large capacitance of the Input / output manifold 66 is connected by means of of Y selector 65 is precharged to Vdd-Vt, then the "1" voltage value would be on on line 37 due to the high transition voltage on line 38 to descend; this could degrade or completely degrade a stored "1" voltage fail. To avoid this, generated for the selected block, in which the selected Y selector 65 is turned on for a read / write operation is, the signal CAS is a clock signal # 3, which assumes a high value according to Figure 4e. This turns on the large transistor 53, so that a good level too is then guaranteed if the load transistors 33, 34 to maintain a good "l" level are switched on.

Fig. 4 is a greatly enlarged photograph of the semiconductor chip 24, which contains the arrangement according to the invention; here are the subdivision of the Matrix 10 and the locations of the row and column decoders and the sense amplifiers shown. The actual size of the chip is 1/4 inch x 1/6 inch).

The shape and division is partly determined by the size of the case determined, as can be seen in Fig.2.

The invention is here in connection with a specific embodiment has been described.

However, those skilled in the art can recognize that within the scope of the invention without further modifications and changes can also be carried out.

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Claims (12)

Patent claim S memory arrangement with a matrix of rows and memory cells arranged in columns and one arranged in the middle of each column Read amplifier with two cross-coupled driver transistors, characterized in that that several switch components are provided which are connected to the driver transistors that are opposite the terminals connected to the column, that the switch components are connected so that they are in the activated state apply the driver transistors to a reference potential, and that clock signal devices are provided on the control electrodes of the switch components on different Apply activation voltages at the times. 2. Arrangement according to claim 1, characterized in that the driver transistors and the switch devices are MOS transistors used as the source-drain current path have a channel and are provided with a gate control electrode. 3. Arrangement according to claim 2, characterized in that the ratio from the channel width and channel length of one of the switch transistors is very small in comparison to the corresponding ratio of the driver transistors. 4. Arrangement according to claim 3, characterized in that the one Switch transistor during a given period of time in the course of an operating cycle is switched on before another switch transistor. 5. Arrangement according to claim 4, characterized in that each sense amplifier Has load transistors, which during an operating cycle in the course of a certain Time period after the given time period can be operated selectively. 6. Semiconductor memory device with a large number of memory cells, which are arranged in an ordered matrix of rows and columns divided into several Cell block pairs is divided, with pairs of opposite columns in each Block pairs are separated from one of several bistable sense amplifiers, thereby characterized in that each sense amplifier has two driver transistors and two load transistors contains that row and column decoders are provided which are dependent on one Address select a cell for reading or writing data, and that one Another decoder is provided which selects a block depending on the address selects the block pairs and the load transistors of the sense amplifiers of this block operated during a selected period of time in a cycle of operation. 7. Arrangement according to claim 6, characterized in that the block pairs are equally divided on both sides of a row decoder. 8. Arrangement according to claim 7, characterized in that the row decoder selects only one line on a page at a given address. 9. Arrangement according to claim 8, characterized in that each sense amplifier for its driver transistors at least two connection paths leading to ground of which the first can carry a little current and the second a lot of current, The second connection path is only used for read and write operations, but not is actuated during a refresh operation. 10. The arrangement according to claim 9, characterized in that only when the sense amplifiers on one side of the row decoder are the first connection path is operated at a given address. 11. The arrangement according to claim 10, characterized in that the load transistor pairs during one cycle of operation for the selected period of time through the other Decoders are made conductive to carry out a read or write operation, and that these load transistor pairs are activated by a clock signal from the further decoder for a refresh process for all blocks lying on one side of the row decoder to be made conductive. 12. The arrangement according to claim 11, characterized in that another Connection path leading to ground is provided for the driver transistors and that this further connection path, with the exception of the actuation of the first connection path operated in all operations.