JPH07107681B2 - Multi-processor system with broadcast loading mechanism - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to a mechanism for loading a program in a multiprocessor system.

[Conventional technology]

In a multi-processor system, if all processors have the same address space and the same address range is assigned to the same program, each program
Broadcasting allows all processors to be loaded at once. However, even if the same address range is assigned to the same program, if the address space differs depending on the processor, in the conventional system, the address space part that is not common to all processors will be individually loaded to each processor. Processing was necessary. For example, if the first processor has first and second line controllers, and the second processor has only the first line controller, the program for the second line controller will be the program for the first processor. Must be loaded by the loading procedure specified only for the target. If the program loading to the second line controller is also done by broadcasting,
In the second processor, an attempt is made to transfer data to the non-existent second line controller, and there should be no response from that, and as a result, it is considered that a time-out error has occurred.

Examples of conventional program loading processing can be found in Japanese Patent Laid-Open Nos. 58-112118 and 58-54424.

[Problems to be solved by the invention]

The individual program loading as described above is extremely inefficient and takes a long time. Further, in order to perform such individual loading, it is necessary to hold and manage the information indicating the address space of each of all the processors. These problems are exacerbated as the number of processors that make up the system increases. Moreover, the loading program (loader) must be complicated and long.

INDUSTRIAL APPLICABILITY The present invention makes it possible to apply a batch loading procedure by broadcast communication even for non-common address space parts,
This is intended to solve the above problems.

[Means for solving problems]

According to the present invention, in addition to the conventional timeout detection mechanism, in each processing module where a program should be loaded, at the time of program loading by broadcast communication, it is equivalent to response information within a fixed time shorter than the timeout limit. Self-responding means is provided for generating normal self-responding information to create a normal end state.

[Action]

According to the above configuration, the program rotation to the address range not implemented is instructed by the broadcast communication, and even if no response occurs, the normal end is guaranteed by the self-response information, and the timeout error state occurs. Falling is prevented. Therefore, even if the address spaces of various processing modules are different, the required program can be loaded into each module only by the broadcast loading procedure.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a system configuration diagram of this embodiment. This system has three processing modules 1,2,3 and upper bus 4
And a group of lines connecting the disk 5 and the relay line or terminal
It is composed of 6, 7 and 8. Each module 1,2,3 is respectively
It has CPUs 12, 22, 32, a common memory (MS) 13, 23, 33, a bus controller (BC) 14, 24, 34 for controlling data transmission / reception between modules, and lower buses 11, 21, 31. Furthermore,
In the module 1, there is a disk controller (DKC) 15 that controls the input / output of data to / from the disk 5.
In the modules 2 and 3, there are line controllers (LC) 25, 26 and 35 for controlling data input / output via the line groups 6, 7 and 8.

FIG. 2 is a configuration diagram of the processing module 3 representing the processing modules 1 to 3. Modules 1 and 2 also have a configuration according to this. In the module 3, the CPU 32, the common memory 33, the bus controller 34, and the line controller 35 described above are connected by the lower bus 31 as illustrated. The lower bus 31 includes a data line 311, an address line 312, an access control line 313, a response line 314, and a timeout notification line 315. Further, a timer monitoring circuit 38 is provided. The timer monitoring circuit 38 monitors the response signal on the response line 314 after the access request, and if the response signal is not detected within a predetermined time, outputs a signal indicating that to the timeout notification line 315.
Send to. Such a situation occurs, for example, when the CPU 32 or the bus controller 34 tries to access an address that does not exist.

FIG. 3 is a block diagram of the bus controller 34. In the bus controller 34, a transmission buffer memory for temporarily storing data transferred between the upper bus 4 and the lower bus 31.
There is a reception buffer memory 341 and a reception buffer memory 342, and an upper bus interface 343 and a lower bus interface 344 are provided to mediate transfer between these buffer memories 341 and 342 and the buses 4 and 31. The memory control unit 345 controls writing / reading of the buffer memories 341 and 342. In addition, the bus controller 34 includes a microprocessor 347 of a micro program control system as a main controller and an upper bus 4
It has an upper bus interface control unit 346 that controls the data input / output for the lower bus 31 by a connection logic, and a lower bus interface control unit 348 that controls the data input / output for the lower bus 31 by the connection logic. The upper bus 4 is composed of a data line 41, an address / command line 42, an access control line 43, and a response line 44.

FIG. 4 is a configuration diagram of the lower bus interface control unit 348 in the bus controller 34. The lower bus interface control unit 348 includes an interface control unit 3481, a self-response mode flip-flop 3482 set and reset by the microprocessor 347 via the control line 3487, and a self-response timing generation circuit 3483. The interface control unit 3481 includes a microprocessor 347 and a control line 3
Communicating via 488, lower bus interface control unit 348
To carry out the main control operations of. When the self-response mode flip-flop 3482 is in the set state, the self-response timing generation circuit unit 3483 responds to the self-response timing after a certain time normally required for writing program data from the generation of the access request signal on the access control line 313. A signal is generated on signal line 3484. The AND circuit 3486 passes the response signal on the response line 314 only when the self-response mode flip-flop 3482 is in the reset state, and the OR circuit 3485 outputs the response signal from the AND circuit 3486 or the self-response mode signal line 3484. The response signal is sent to the interface control unit 3481.

FIG. 5 shows the details of the lower bus interface mechanism in the line controller 35. The line controller 35 also incorporates a micro processor 358 of a micro program control system, and a memory 351 for storing the micro program.
have. Further, a lower bus interface 352, a memory control unit 353, a lower bus interface control unit 354, an access address register (A register) 355, a self address register (O register) 356, and a comparator (CMP) 357 are provided. The access address register 355 is the lower bus 3
The access request address transferred on the address line 312 in 1 is received. The self address register 356 has memory 3
Information indicating the range of addresses assigned to 51 is preset.

Next, a general description of the data transfer operation on the lower bus will be given by taking the case where the bus controller 34 transfers data to the memory 351 in the line controller 35 as an example.
There are two modes of transfer operation, that is, a normal mode and a self-response mode. In the normal mode, a different operation is performed depending on whether or not a normal response is obtained.

The first half of the transfer operation is the same in all cases. That is, the microprocessor 347 in the bus controller 34.
Sets the start address of the access destination and the number of transfer bytes to the lower bus interface control unit 348 and activates it. The activated lower bus interface control unit 348
Address and access request to the address line 312 respectively
And the lower bus interface 344 to send data to the data line 311. The line controller 35 receives the address on the address line 312 in the access address register 355, and checks by the comparator 357 whether it is within the address range indicated by the self address register 356.

Normal mode is used for normal data transfers other than broadcast program loading and is indicated by the self-response mode flip-flop 3482 (FIG. 4) being in the reset state. In the normal mode, the comparator 357 becomes “Y
If "ES" is indicated, the lower bus interface control unit 354 returns a response via the response line 314, controls the lower bus interface 352 and the memory control unit 353, and stores in the memory 351 obtained from the access address. Data line 311 to each position
Write the data above. On the other hand, when the lower bus interface control unit 348 in the bus controller 34 detects the response on the response line 314, it turns off the signals on the data line 311, the address line 312, and the access control line 313, and the next bus Shift to cycle. FIG. 6 shows the timing of various signals in this case.

On the other hand, if the comparator 357 in the access destination line controller 35 indicates "NO", no response is sent to the response line 314. If no response is generated from the common memory 33, the timer monitoring circuit 38 (FIG. 2) sends a time-out signal to the time-out notification line 315 after a predetermined time t ₁ . The lower bus interface control unit 348 in the bus controller 34, which is the access source, receives the time-out signal, turns off the signals on the data line 311, the address line 312, and the access control line 313, and generates a time-out. Is recorded, and execution of error handling for the timeout is started. FIG. 7 shows the timing of various signals in this case. The time t ₁ is set long enough to allow accidental delays in response.

The self-responsive mode is a special mode according to the present invention for program loading and is indicated by the self-responsive flip-flop 3482 being in the set state. In this mode, the line controller 35 that is the access destination sends a response on the response line 314 according to whether or not the access address is in the address range belonging to itself, as in the normal mode. Or do not send. However, the self-response timing generation circuit 3483 in the bus controller 34, which is the access source,
Regardless of whether or not there is a response on 4, a self-response signal is generated on signal line 3484 after a predetermined time t ₂ . This self-response signal is
It is sent to the interface control unit 3481 via the OR circuit 3485,
Upon receiving this, the interface control unit 3481 receives the data line 311, the address line 31 as in the case of receiving the normal response.
2, the signal on the access control line 313 is turned off, and the process goes to the next bus cycle. FIG. 8 shows the timing of various signals in this mode. Time t ₂ is set to a value that is normally required for the transfer of the program data.

Next, the process of program loading will be described. Now, the program data for all modules is prepared in the disk 5, and the loading of the program to the module 1 has been completed by self-IPL (Initial Program Loading), and each module 1,
It is also assumed that the bus controllers 14, 24, 34 in 2, 3 are also in an operable state. Next, it is necessary to load the microprograms controlling the line controllers 25, 26, 35 in the modules 2, 3 to the microprogram storage memories 251, 261, 351 in the respective line controllers.
To simplify the explanation, the microprogram is
Common to all line controllers.

First, in the module 1 which is the main body of loading, the loading control program stores the line controller microprogram data read from the disk 5 in the storage address (from the address n + m-m + n) on the memory in the first line controller of each module. Address 1) and transfer to the transmission buffer 141 in the bus controller 14. The bus controller 14 then activates its broadcast function and sends out a broadcast message containing this microprogram data and address information onto the upper bus 4. The bus controllers 24 and 34 in the respective modules 2 and 3 take in the broadcast messages to the reception buffers 242 and 342, respectively.

For example, in the bus controller 34, the microprocessor 347 sets the self-response mode flip-flop 3482 in the lower bus interface control unit 348 and then, according to the address information in the received message, the microprocessor in the received message. Program data, line controller
The data is transferred from the address n of the microprogram storage memory 351 in the address 35 to the address n + m-1 by the above-mentioned procedure. Although the line controller 35 is sent onto the line of response 314 a response, Regardless, after a time t _2, autoreactive timing generating circuit 3483 is to generate a self-response signal on line 3484, the bus cycle To finish. In the other modules 2 as well, similarly, the microprogram data is stored in the microprogram storage memory 251 in the line controller 25.

Subsequently, the loading control program in the module 1 starts loading the micro program to the second line controller in each module. Disk 5
The microprogram data read again from the memory is stored in the memory in the second line controller of each module (addresses p to p + m-1),
In the same way as the previous time, it was edited into a broadcast message, passed through the bus controller 14 and the host bus 4, and then each module 2,
It is transferred to the bus controllers 24 and 34 in 3.

In the module 2, as in the previous time, the micro program storage memory 26 in the second line controller 26
The received microprogram data is stored in the addresses from p above to p + m-1. On the other hand, Module 3
, The second line controller (in other words, p
There is no memory from address to address p + m-1) and therefore no response on response line 314 is generated. However, since the bus controller 34 is in self-response mode,
The self-response timing generation circuit 3483 generates a self-response signal on the signal line 3484 after the time t ₂ , so that the bus cycle ends normally as if the second line controller were actually present. Therefore, the program loading process also proceeds smoothly to the next step.

When the program loading process is completed, the microprocessor 347 in the bus controller 34 of the module 3 is
Resets self-reply mode flip-flop 3482 to normal mode. After that, if an attempt is made to access an unimplemented address space, the timer monitoring circuit will
38 generates a time-out signal, which causes time-out error handling.

In the conventional system, in the case of the program loading to the second line controller in the above example,
It is necessary to specify only the module 2 as the destination and transfer the program data. If this is done via broadcast, a timeout error will occur in module 3 after time t ₁ .

〔The invention's effect〕

According to the present invention, a module that loads a program does not need to check the difference in the address spaces of various modules that receive the load and perform the loading process separately, and a uniform broadcast loading process common to all the modules can be performed. Can be done. Therefore, the total time required for program loading is shortened, there is no need to maintain and manage the information indicating the address space of various modules, and the program for program loading is simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a multiprocessor system which is an embodiment of the present invention, and FIG. 2 is a first block diagram.
A block diagram showing in detail one of the modules shown in the figure, FIG. 3 is a block diagram showing details of the bus controller in the module shown in FIG.
FIG. 5 is a block diagram showing the details of the lower-order bus interface control unit in the bus controller of FIG. 3, and FIG. 5 is a block diagram showing the details of the lower-order bus interface mechanism of the line controller in the module of FIG. 6 is a time chart of various signals in the normal access process in the normal mode, FIG. 7 is a time chart of various signals in the time-out process in the normal mode, and FIG. 8 is a time chart of various signals in the self-response mode. 1 …… Processing module for rotation, 2,3 ……
Processing module that receives rotation, 4 …… High-order bus, 5 …… Disk that stores programs, 11,21,
31 …… Lower bus, 14,24,34 …… Bus controller, 251,
261,351 …… Micro program storage memory, 38 …… Timer detection circuit for timeout detection, 348 …… Lower bus interface controller in bus controller, 3482 …… Self-response mode flip-flop, 3483 …… Self-response timing creation Circuit, 354 ... lower-order bus interface control unit in line controller, 355 ... access address register, 356 ... self-address register, 357 ... comparator.

Claims (2)

[Claims] 1. A first communication path comprising: a first communication path; and a means for sending the program information source and the program information from the program information source together with its storage address as broadcast communication information on the first communication path. A first processing module connected to the first communication path and a plurality of second processing modules connected to the first communication path, each of the second processing modules being on a second communication path and on the first communication path. Means for receiving communication information and transmitting information contained therein and a storage address on the second communication path, and a memory having a predetermined address space and the storage address on the second communication path included in the address space At least 1 having means for storing the information on the second communication path in the memory and generating response information
And a second processing unit for monitoring the response information and storing the information and the storage address.
Response monitoring means for performing error processing when the response information does not appear within a predetermined first time from the transmission on the communication path; and second of the program information and storage address included in the broadcast communication information. Self-response means for generating self-response information equivalent to the response information after a predetermined second time shorter than the first time from transmission on the communication path, and a multiprocessor system. 2. The apparatus according to claim 1, further comprising means for keeping the self-responsive means normally inoperative and switching it to an operating state prior to the sending of the program information and the storage address onto the second communication path. The multiprocessor system according to item 1.