JPH07105715B2 - Programmable logic system and programmable logic element therefor - Google Patents

Description

Detailed Description of the Invention

[Industrial applications]

The present invention relates to a programmable logic element for a master and a logical function based on definition data which is arranged on the downstream side of the master programmable logic element or a slave programmable logic element on the upstream side via a data line. A programmable logic system including a programmable logic element for a slave, and a programmable logic element (hereinafter, simply referred to as a logic element) used for the programmable logic system, in particular, a master mode is set from an external memory. Counts the synchronization clock supplied from the master mode logic element to the slave mode logic element when the logic function definition data is transferred and supplied to the slave mode programmable logic element via the programmer logic element. Stop the synchronization clock at the end of data transfer Because the programmable logic system is not necessary to provide a pulse counter, and to a programmable logic device therefor.

[Prior art]

For example, in a programmable logic element whose logic function is determined by definition data input from a memory such as an external ROM or EPROM, for example, in a programmable gate array, supply logic function definition data to each programmable logic element before use. It is necessary to define the logical function. Therefore, conventionally, for example, as shown in FIG. 10, a plurality of (n + 1 in the figure) programmable logic elements are connected in series, and the programmable logic element on the most upstream side is a programmable logic element in a master (MASTER) mode (hereinafter , A read-only memory (ROM) 20 storing logic function definition data of each programmable logic element as the master logic element 10a.
Connected to. On the other hand, for example, n slave mode programmable logic elements (hereinafter referred to as slave logic elements) having the same hardware configuration as the master logic element 10a and having the same hardware configuration as that of the master logic element 10a.
10b is connected in series with the master logic element 10a. When loading the logic function definition data, the address counter 11 of the master logic element 10a outputs an address to the ROM 20, and corresponding to this address, for example, 8-bit definition data is output from the ROM 20. . Based on this definition data, the master data is first stored in the circuit definition memory 12 of the master logic element 10a, and then the slave data is stored in the output terminal Dou of the master logic element 10a.
The data is output from t, input to the input terminal Din of the slave logic element 10b on the downstream side, and sequentially transferred and stored in the order of slave No. 1, ... No. n. That is, the logic element 10b, which is a slave other than the master, is the master logic element 1
The logical function definition data is received from the ROM 20 via 0a. After the definition mode ends, the use mode is entered. Therefore, the master logic element 10a uses the synchronization clock CCLK for determining the data acquisition timing so that each slave logic element 10b can accurately receive the definition data. And to synchronize the definition end of each logic element,
The total number of clocks until the logic function definition data is transferred to all slave logic elements 10b is counted, and the definition data is stored in the circuit definition memory of all programmable logic elements.
After being stored in 12, it is necessary to stop this synchronizing clock CCLK to end the define mode and enter the use mode. Therefore, in a system having a plurality of programmable logic elements, conventionally, a pulse counter 16 is provided inside each programmable logic element in addition to the pulse generator (PG) 14, and the definition data of the master logic element 10a In order to load the definition data from the ROM 20 into the entire system, the pulse generation number of the synchronization clock CCLK corresponding to the total number of data is written to control the pulse generation of the synchronization clock CCLK.

[Problems to be Solved by the Invention]

However, in the above method, it is necessary to incorporate the pulse counter 16 in each programmable logic element without fail, and the slave logic element 10b and the master logic element 10a.
Since the same pulse counter is required, the area is large and integration is hindered. Further, since the size of the pulse counter 16 determines the total number of definition data of the system, the pulse counter 16 has a relatively large size in consideration of the case of a relatively large system that uses a large number of programmable logic elements. There is no choice but to become a scale counter. On the other hand, in the case of a small system that does not use a plurality of programmable logic elements, the pulse counter 16 is completely useless, and when viewed as an integrated circuit as a whole, it leads to an increase in chip cost or a decrease in yield. Had. The present invention has been made to solve the above-mentioned conventional problems, and is a programmable logic system for storing data for circuit function definition in the entire system, which does not require a pulse counter corresponding to the total number of data, And a programmable logic element therefor.

[Means for Solving the Problems]

The present invention provides a master programmable logic element and a logic function provided by a definition data which is arranged downstream of the master programmable logic element or a slave programmable logic element on the upstream side via a data line. In a programmable logic system including a slave programmable logic element that is determined, the slave programmable logic element has the same holding unit that temporarily holds input data, and the same data that the holding unit holds. Data, output means for outputting to the data line on the downstream side, the state of the data line on the downstream side and the data temporarily held in the holding means are compared, and the slave programmable logic element adjacent to the downstream side By the downstream definition end detecting means for detecting the end of definition and the downstream definition end detecting means, Until the end of definition of the programmable logic element adjacent to the flow side is detected, the input definition data is transmitted to the slave programmable logic element adjacent to the downstream side, and the slave programmable logic element adjacent to the downstream side is transmitted. When the definition end is detected, in order to use the input definition data to define its own logical function, the data switching means for switching to take in the self and the self detecting the end of definition of the own logical state. A definition end detection means and a self-definition end notification means for fixing the state of the upstream data line to a constant value at least temporarily when the self-definition end detection means detects the end of its definition. In addition, the programmable logic element for master detects the state of the data line on the downstream side, and the programmable logic device for slave adjacent to the downstream side is detected. Detecting the defined end of a logical element, thereby, by including all definitions end detection means for detecting a defined termination of all programmable logic devices for a slave is obtained by achieving the above object. Further, the master programmable logic element,
It includes a means for supplying a clock to each slave programmable logic element and a clock cycle changing means for temporarily changing the cycle of the clock at the end of the definition of all slave programmable logic elements. The element further includes a clock change detection means for detecting a change in the clock cycle. Further, an output terminal fixing means for fixing the potential to a constant value is connected to the output terminal of the data line of the slave programmable logic element on the most downstream side at least temporarily. According to the present invention, in a programmable logic device, at least a part of a series of definition data groups to which a boundary detection code is added for each definition data of one programmable logic device is used as a clock input from the outside. An input unit for inputting in synchronization, a holding unit for temporarily holding the data input by the input unit, and the same data as the data held by the holding unit are synchronized with the clock,
Output means for outputting to an output terminal connected to the downstream data line, a circuit definition memory for storing a definition data group input by the input means, an output terminal of the output means and the holding means. A match detection unit that detects the boundary detection code by a match or a mismatch with the temporarily held data, and the boundary detection code is detected by the match detection unit, and the definition end of the programmable logic element adjacent to the downstream side is completed. Until it is detected, the input definition data group is output to the output terminal as it is. On the other hand, when the boundary detection code is detected, the input definition data is disconnected from the output means. The data switching means for inputting to the circuit definition memory and the end of data storage in the circuit definition memory to be used for defining the logic function of the user Self-definition end detection means for detecting the end of the definition of the function, and when the self-definition end detection means detects the end of the definition of itself, the self-definition end is notified to the programmable logic element adjacent on the upstream side. The above object is achieved by including input terminal fixing means for fixing the potential of the input terminal of the input means at least temporarily to a constant value.

[Action]

In the programmable logic system according to the present invention,
A slave programmable logic element, holding means for temporarily holding input data, output means for outputting the same data as the data held by the holding means to a data line on the downstream side; Side definition end detection means for detecting the definition end of the slave programmable logic element adjacent to the downstream side by comparing the state of the data line on the side with the data temporarily held in the holding means, and the downstream side Until the definition completion detecting means detects the definition completion of the programmable logic element adjacent to the downstream side, the input definition data is transmitted to the slave programmable logic element adjacent to the downstream side, and the definition data is adjacent to the downstream side. When the end of definition of the slave programmable logic element is detected, the input definition data is used to define its own logic function. A data switching means for switching so as to take in a self-defined end detection means for detecting a defined termination of their logic functions, by the self-defined end detection means,
When the self-definition end is detected, including the self-definition end notification means for fixing the state of the data line on the upstream side to a constant value at least temporarily, the programmable logic element for master is configured to detect the data on the downstream side. Detecting the end of definition of the slave programmable logic elements adjacent to the downstream side by detecting the state of the line, thereby including all definition end detecting means for detecting the end of definition of all slave programmable logic elements By this, the completion of definition of each slave logic element is sequentially notified to the slave logic element on the upstream side via the data line supplied to the slave side, and finally the master logic element defines all slave logic elements. I am trying to notify the end. Therefore, the control of the generation of the basic clock of the master logic element can be controlled without using a large-scale circuit such as a pulse counter, and the number of slave logic elements is not limited by the size of the pulse counter. Therefore, it becomes possible to realize a more integrated programmable logic system, which results in extremely high industrial value such as improvement in yield and improvement in productivity. The master programmable logic element further supplies means for supplying a clock to each slave programmable logic element from itself, and a clock cycle for temporarily changing the cycle of the clock at the end of the definition of all slave programmable logic elements. Each slave programmable logic element including a changing means further includes a clock change detecting means for detecting a change in the clock cycle so that the clock supplied from the master logic element to each slave logic element is changed. If the cycle is temporarily changed at the end of the definition of all slave logic elements, and each slave logic element is notified of the end of the definition of all slave logic elements, It is possible to end the definition mode synchronously and change to the usage mode such as I / O. Kill. In the programmable logic device according to the present invention,
Input means for inputting at least a part of a series of definition data groups to which a boundary detection code is added for each definition data for one programmable logic element in synchronization with an externally input clock. A holding means for temporarily holding the data inputted by the input means, and an output to which the same data as the data held by the holding means is connected to a downstream data line in synchronization with the clock Output means for outputting to the terminal, circuit definition memory for storing the definition data group inputted by the input means, and output terminal of the output means and data held temporarily in the holding means are matched or mismatched. By the coincidence detection means for detecting the boundary detection code, and the coincidence detection means detects the boundary detection code, and the definition of the programmable logic element adjacent to the downstream side is completed. Until it is detected, the input definition data group is output to the output terminal as it is. On the other hand, when the boundary detection code is detected, the input definition data is disconnected from the output means. Data switching means for inputting to the circuit definition memory for use to define its own logical function, and self-definition completion detecting means for detecting completion of definition of its own logical function by completion of data storage in the circuit definition memory. When the self-definition end detecting means detects the self-definition end, the potential of the input terminal of the input means is at least temporarily to notify the programmable logic element adjacent to the upstream side of the self-definition end. By providing an input terminal fixing means for fixing a fixed value, it becomes possible to identify the boundary of each logic element of a series of logic function definition data, and the programmer himself When the storage of the definition data defining the logical function of the logic block is completed, the input terminal of the input means to which a series of definition data groups is input is temporarily fixed, and the upstream programmable connected to the input terminal is connected. The boundary detection code is detected by matching or non-matching between the output terminal of the logic element and the data temporarily held in the holding means for temporarily holding the data input by the input means, and by the match detection. The definition data is separated from the output means and input to the circuit definition memory. Therefore, it is possible to detect the end of data storage of the logic element (downstream when viewed from the programmable logic element on the upstream side) and notify the end of data storage of the programmable logic element to the upstream logic element. The system can be easily configured.

【Example】

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a first diagram of a programmable logic device according to the present invention.
A master logic element 30a configured using the embodiment,
It shows a part of a programmable logic system including n slave logic elements 30b. A series of definition data groups used in the present embodiment is, as illustrated in FIG. 2, a boundary detection code for each definition data of one logical element, and in the case of FIG. A boundary detection code consisting of 3 bits of "1" and 1 bit of "0" for notifying the start of definition is added. Here, the first 3 bits of the boundary detection code are set to "1" because the input terminal Din of the downstream logic element, that is, the output terminal Dout of the logic element at the end of storage of the downstream data. This is because the pull-down is performed, and conversely, when the input terminal Din is pulled up at the end of the data storage of the downstream side logic element, the boundary detection code is, for example, “0001” in order from the beginning. Can be Unlike the conventional example shown in FIG. 10, each programmable logic element has no pulse counter. That is, as in the conventional case, the synchronization clock CCLK is supplied from the master logic element 30a to the slave logic element 30b, but the control signal for stopping the supply of the synchronization clock CCLK is not from the pulse counter as in the conventional case. However, in this embodiment, the output terminal Dout is output from the slave logic element on the downstream side.
Be entered via. This is the basic idea of the present invention, which will be specifically described below. Each programmable logic element has an input terminal Din and an output terminal Dout for logic function definition data as in the conventional case. The logic function definition data as shown in FIG. 2 input from the input terminal Din is input to the flip-flop (FF) 34 via the input buffer 32 and the changeover switch 36.
And via the output buffer 38, it is input to the input terminal Din of the slave logic element on the downstream side of the output terminal Dout. Here, as shown in FIG. 3, the flip-flop 34 receives an inverted signal of the synchronizing clock CCLK (φ) as a clock input, and the output buffer 38 outputs a clock φ ′ (third part) of the clock φ. (See FIG. 4 or FIG. 4). Therefore, the definition data is output at the rising edge of the clock φ'and input to the slave logic element on the downstream side at the falling edge of the clock φ. In addition, the input buffer 32 includes a weak latching inverter 40 and an input terminal Di at the end of data storage of the logic element.
For pulling down and fixing n nodes, for example, n
An input terminal fixing transistor 42, which is a channel MOS transistor, is coupled. Further, the changeover switch 36 is configured to connect the output of the flip-flop 34 to the output buffer 38 in the initial state after the power is turned on. The latching inverter 40 is for holding data when the input terminal fixing transistor 42 is off, and has a capacitive (parasitic) element in the preceding stage,
It can be omitted if it is a holding means. What is important here is a circuit configuration for switching the changeover switch 36 toward the internal circuit definition memory 44 to define the logic of the logic element. In the present embodiment, in order to detect the end of storage of downstream data, a series of definitions is obtained by taking the exclusive OR of the node of the output buffer 38 (that is, the node of the output terminal Dout) and the node of the flip-flop 34. An inconsistency detection circuit 46 is provided for detecting the boundary detection code of the data group. That is, the output terminal Dout
Is a transistor 42 for fixing the input terminal of the logic element on the downstream side.
Alternatively, when the boundary detection code "111" is entered when the resistor R (in the case of the logic element on the most downstream side) is pulled down, as shown in FIG.
Output occurs. Here, the ON time of the operation signal φ ″ of the mismatch detection circuit 46 is shorter than the corresponding clock φ because the pull-down by the input terminal fixing transistor and the like and the next data overlap each other. This is to prevent malfunction of the data detection circuit by the output signal of the mismatch detection circuit 46.
48 operates to switch the change-over switch 36, and the necessary definition data is introduced into the circuit definition memory 44 of its own. Furthermore,
When the storage of the definition data in its own circuit definition memory 44 is completed, the definition terminal signal output from the circuit definition memory 44 turns on the input terminal fixing transistor 42 at the timing of the clock ▲ ▼. As a result, the input terminal Din of the logic element is pulled down. As described above, the logic element finishes the introduction and storage of its own definition data and fixes the node of its own input terminal Din to “0” in synchronization with the clock ▲ ▼. At this time, a plurality of "1" signals indicating the boundaries of the definition data are input to the input terminal Din from the output terminal Dout of the upstream logic element. Therefore, the upstream logic element detects that the signal "1" output from the flip-flop 34 and the signal "0" at the node of the output terminal Dout do not match, and indicates the boundary of this definition data. A plurality of (three in the embodiment) "1" signals for definition sent after being detected as data to be stored in its own circuit definition memory 44, and its own changeover switch.
36 is switched to the circuit definition memory 44 direction. These series of operations are sequentially repeated, and finally, by the output from the data detection circuit 48 (not shown) provided at the output terminal Dout inside the master logic element 30a and the definition end signal of itself, Clock CCLK supplied from the pulse generator 50 to the external slave logic element 30b
The supply of (φ) is stopped. In the figure, 52 is an address counter. In addition, as described above, finally the master logic element 30
When the end of the entire definition is notified to a, as shown in FIG. 5, the cycle of the clock CCLK is temporarily changed, thereby notifying the slave logic elements 30b of the end of the entire definition and synchronizing. It is also possible to change the usage mode for I / O, etc. Also, the output terminal Dout of the slave logic element 30b on the most downstream side
Since there is no logic element on the downstream side, for example, by using a resistor R of about 5 to 10 KΩ, the output terminal is grounded and pulled down (fixed) at all times or only during definition, so that the mismatch detection circuit. 46 can be activated. In the above description, the slave logic element and the master logic element are separately described for the operation, but the actual circuit configurations are all common. Further, another example of the detection circuit for detecting the node signal of the output terminal Dout and the signal output from the flip-flop is shown in FIGS.
It will be described with reference to the drawings. This FIG. 6 embodies the circuit of FIG.
Two flip-flops for easy timing design
FF1 and FF2 are used, and FF3 and the exclusive OR element 96a are the mismatch detection circuit 4 in FIG.
It has the same function as 6. The circuit operation timing is shown in FIG. First,
The data input by the input Din is latched in FF1 at the rising timing of the clock and further latched in FF2 at the rising timing of the clock φ '. At this time, the exclusive OR element 98 determines whether the data is output to Dout or the internal circuit definition memory 44. That is, when the output of the mismatch detection circuit 96 is φ (that is, when no mismatch is detected) and the MODE signal is “φ”, the output of the exclusive OR element 98 is “φ”,
This signal is input to the two OR elements 99a and 99b, only the OR element 99a becomes active, and the data is input to the circuit definition memory 44. On the other hand, when the MODE signal is "1", on the contrary, only the logical sum element 99b becomes active, and the data is output to Dout via the output buffer 38. Here, in order to mainly explain the function of the mismatch detection circuit 96, a case where data is output to the Dout terminal via the output buffer 38 will be considered. Data is driven to the Dout terminal by the output buffer 38 which becomes active at the clock φ ', and the half cycle which is not driven varies depending on the operating condition of the Din terminal of the downstream element. For example, in the state where the writing of the definition data to the downstream element has not been completed, the downstream Din terminal holds the data of the upstream Dout terminal (see FIG. 7). On the other hand, the mismatch detection circuit 96 on the upstream side always operates the Dout terminal node and the Q of FF2.
The outputs are compared at the rising timing of the clock φ, and no mismatch is detected. However, when the final data dl is written in the downstream definition memory and the definition is completed, the downstream element
The Din terminal is forcibly pulled down at the timing of ▼, that is, at the timing when the Dout terminal of the upstream element is not driven. At this time, FF is connected to the Dout terminal of the upstream element.
The mismatch detection bit "1" latched in 2 is output, and this "1" data is pulled down to "φ" at the timing of the clock ▲ ▼. This is compared with the Q output “1” of FF2 at the rising edge of the clock φ, a non-coincidence signal “1” is generated and input to the exclusive OR element 98, and the output of this element changes from “1” to “0”. The change causes the data to be input next to the circuit definition memory 44 (see FIG. 7). In the first embodiment, the logical function of the master logic element 30a is defined last, but the rise time of each logic element varies, so that the rise of each slave logic element is different. The definition data may be sent out faster than the above. Therefore, in order to stabilize the operation of each slave logic element 30b, it may be better to define the master logic element 30a first. The second embodiment of the present invention, which is suitable for such a case, will be described in detail. The main part (from the input terminal Din to the output terminal Dout) of the programmable logic element according to the second embodiment is configured as shown in FIG. 8, and the initial position of the changeover switch 36 by the output of the data detection circuit 48, And the input terminal fixing transistor 42 by the definition end signal from the circuit definition memory 44.
The on / off state of is different from the first embodiment in that it can be changed between the master mode and the slave mode. Since the other points are the same as those of the first embodiment, detailed description will be omitted. In the second embodiment, the changeover switch 36 of the logic element 30a in the master mode is different from the slave mode logic element 30b shown in FIG. 9 in the initial state after power-on as shown in FIG. On the contrary, the definition data input via the input buffer 32 and the flip-flop 34 is first introduced into its own circuit definition memory 44. Also, the input terminal fixing transistor 42 becomes 0 when it is used as a master so as to pass the node of the input terminal Din backward without pulling down the node of the input terminal Din even after its definition is completed, and becomes a slave. It is designed to operate in consideration of the state of the mode signal MODE which becomes 1 when used. On the other hand, in this second embodiment, as shown in FIG. 9, in the programmable logic element 30b in the slave mode, the changeover switch 36 sends the definition data to the output buffer 38 when the power is turned on, as in the first embodiment. While being switched to the passing direction, the input terminal fixing transistor 42 is
It is designed to pull down immediately after its definition is completed. Each clock waveform in the second embodiment is the same as that in the first embodiment shown in FIG. In addition, the said Example shows an example of the circuit structure of the programmable logic element which concerns on this invention, and the circuit structure of the programmable logic element which concerns on this invention is not limited to this.

【effect】

As described above, according to the present invention, it is not necessary to provide a pulse counter corresponding to the total number of data for storing circuit function definition data in the entire programmable logic system. Further, there is no limitation on the number of slave logic elements depending on the size of the pulse counter. Therefore,
A more integrated programmable logic system can be realized with high yield and productivity.

[Brief description of drawings]

FIG. 1 is a first diagram of a programmable logic device according to the present invention.
FIG. 2 is a block diagram showing an example of a programmable logic system including a plurality of embodiments, FIG. 2 is a diagram showing an example of a series of definition data groups used in the first embodiment, and FIG. FIG. 4 is a diagram showing an example of the operation timing of the data detection circuit in the first embodiment, FIG. 4 is a diagram showing an example of the clock timing of the data detection circuit of the first and second embodiments, and FIG. FIG. 6 is a diagram showing an example of a clock waveform at the end of the entire definition in a modification of the embodiment, FIG. 6 is a circuit diagram showing another configuration example in the first embodiment, and FIG. 7 is a circuit shown in FIG. FIG. 8 is a diagram showing the operation timing, FIG. 8 is a circuit diagram showing the configuration of the second embodiment of the present invention, and a state in which the master mode is set, and FIG. 9 is a programmable mode also set in the slave mode. Circuit diagram showing the state of the logic element, Fig. 10 The programmable logic device come is a block diagram showing an example of a plurality used was a programmable logic systems. 30a …… Master programmable logic element, 30b …… Slave programmable logic element, Din …… input terminal, Dout …… output terminal, CCLK …… synchronization clock, 32 …… input buffer, 34 …… flip-flop, 36 ...... Changeover switch, 38 …… Output buffer, 42 …… Input terminal fixing transistor, 44 …… Circuit definition memory, 46 …… Mismatch detection circuit, 48 …… Data detection circuit.

Claims (4)

[Claims] 1. A master programmable logic element and a logic function based on definition data which is arranged downstream of the master programmable logic element and which is input from the master programmable logic element or an upstream slave programmable logic element via a data line. In a programmable logic system including a slave programmable logic element for which the slave programmable programmable logic element is determined, the slave programmable logic element temporarily holds input data, and data held by the holding means. Output means for outputting the same data to the data line on the downstream side and the state of the data line on the downstream side and the data temporarily held in the holding means are compared, and programmable for slaves adjacent to the downstream side Downstream definition end detecting means for detecting the end of definition of the logic element, and the downstream definition end detecting means. Until the definition end of the programmable logic element adjacent to the downstream side is detected, the input definition data is transmitted to the slave programmable logic element adjacent to the downstream side, and the slave programmable logic element adjacent to the downstream side is transmitted. When the definition end of the element is detected, the definition data to be input is switched so that it is used to define its own logic function, and the end of definition of its own logic function is detected. Self-definition end detection means, and self-definition end notification means for fixing the state of the upstream data line to a constant value at least temporarily when the self-definition end detection means detects the self-definition end And the programmable logic element for master detects the state of the data line on the downstream side, It detects the definition end of Roguramaburu logic elements, thereby, a programmable logic system, which comprises a total definition end detection means for detecting definition end of all the slave for a programmable logic device. 2. The programmable logic element for master according to claim 1, further comprising means for supplying a clock from the programmable logic element for itself to each programmable logic element for slaves, and a cycle of the clock of all programmable logic elements for slaves. A programmable logic system comprising: clock cycle changing means for temporarily changing at the end of definition, wherein each slave programmable logic element further includes clock change detecting means for detecting a change in the clock cycle. 3. The output terminal fixing means for fixing the potential to a constant value at least temporarily to the output terminal of the data line of the slave programmable logic element on the most downstream side according to claim 1 or 2. A programmable logic system characterized by being implemented. 4. At least a part of a series of definition data groups to which a boundary detection code is added for each definition data for one programmable logic element is input in synchronization with a clock input from the outside. Input means, a holding means for temporarily holding the data input by the input means, and the same data as the data held by the holding means, in synchronization with the clock, on the downstream side data line. Output means for outputting to an output terminal to which is connected, a circuit definition memory for storing a definition data group input by the input means, an output terminal of the output means and data temporarily held in the holding means. Match detection means for detecting the boundary detection code, and the boundary detection code is detected by the match detection means, and the programmable logic adjacent to the downstream side is detected. Until the end of the element definition is detected, the input definition data group is output to the output terminal as it is. On the other hand, when the boundary detection code is detected, the input definition data is output. The data switching means for inputting to the circuit definition memory so as to be used to define its own logical function by disconnecting it from the means, and the end of data storage in the circuit definition memory detect the end of definition of its own logical function. Self-definition end detection means, and when the self-definition end detection means detects the self-definition end, in order to notify the programmable logic element adjacent to the upstream side of the self-definition end, the potential of the input terminal of the input means A programmable logic element, comprising: input terminal fixing means for fixing at least temporarily to a constant value.