JPH07105485B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH07105485B2 JPH07105485B2 JP29524188A JP29524188A JPH07105485B2 JP H07105485 B2 JPH07105485 B2 JP H07105485B2 JP 29524188 A JP29524188 A JP 29524188A JP 29524188 A JP29524188 A JP 29524188A JP H07105485 B2 JPH07105485 B2 JP H07105485B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- impurity
- impurity region
- substrate
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title description 11
- 239000012535 impurity Substances 0.000 claims description 121
- 239000000758 substrate Substances 0.000 claims description 29
- 230000002093 peripheral effect Effects 0.000 claims description 14
- 230000000903 blocking effect Effects 0.000 description 17
- 230000005684 electric field Effects 0.000 description 14
- 238000000034 method Methods 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 11
- 230000001681 protective effect Effects 0.000 description 8
- 238000013459 approach Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） この発明は、チップサイズが小さく、安定した逆電圧阻
止特性を有する半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a small chip size and stable reverse voltage blocking characteristics, and a manufacturing method thereof.
第２図はプレーナー型半導体装置の一種である従来のダ
イオードを示す断面図である。N+基板１上にはN-エピタ
キシャル層２が形成されている。N-エピタキシャル層２
上にはＰ型不純物領域たるアノード領域３及びＮ型不純
物領域たる環状のフィールドミッティングリング４が形
成されている。フィールドリミッティングリング４は、
空乏層が伸び過ぎてN-エピタキシャル層２の側面（通常
の場合ダイシング面）に達するのを防止する。アノード
領域３上にはアノード電極６が形成され、N+基板１の下
面にはカソード電極７が形成されている。アノード領域
３とフィールドリミッティングリング４との間のN-エピ
タキシャル層２上には二酸化シリコンより成る接合保護
膜８が形成されている。フィールドリミッティングリン
グ４上には電極９が形成されている。FIG. 2 is a sectional view showing a conventional diode which is a kind of planar type semiconductor device. An N − epitaxial layer 2 is formed on the N + substrate 1. N - Epitaxial layer 2
An anode region 3 that is a P-type impurity region and an annular field-mitting ring 4 that is an N-type impurity region are formed on the top. Field limiting ring 4
It prevents the depletion layer from extending too much and reaching the side surface of the N − epitaxial layer 2 (normally the dicing surface). An anode electrode 6 is formed on the anode region 3, and a cathode electrode 7 is formed on the lower surface of the N + substrate 1. A junction protective film 8 made of silicon dioxide is formed on the N − epitaxial layer 2 between the anode region 3 and the field limiting ring 4. An electrode 9 is formed on the field limiting ring 4.
上記のような構成を有するダイオードのアノード電極６
とカソード電極７との間に逆電圧を印加すると、アノー
ド領域３とN-エピタキシャル層２により規定されるPN接
合部より空乏層10が広がる。そして、アノード電極６と
カソード電極７との間に与えられる電圧の差が所定値以
上になると降伏が生じる。上記動作において、良好な逆
電圧阻止特性を得るのに障害となる問題がある。それ
は、空乏層10の断面形状の曲率半径の問題である。すな
わち、第２図に示すａ部での空乏層10の曲率半径は空乏
層10の他の部分での曲率半径より小さくなる。その結
果、ａ部付近の電位傾斜が大きくなり電界集中が生じ良
好な逆電圧阻止特性が得れない。ａ部での曲率半径を大
きくするための構造としては特開昭61−84830号公報に
示された構造がある。第３図は上記公報に示された構造
を有するダイオードの断面図である。このダイオードの
構造では、アノード領域３において外周方向Ａに近づく
ほどＰ型不純物濃度を低くし、かつＰ型不純物の拡散の
深さを浅くしている。その他の構成は、第２図に示した
ダイオードと同様である。このように構成することによ
りａ部での空乏層10の曲率半径は空乏層10の他の部分の
それと比し小さくなることはない。そのため、ａ部に電
界集中は起きず良好な逆電圧阻止特性が得られる。さら
に、アノード領域３のＰ型不純物濃度が低い領域には空
乏層10が伸びるので、このことからも空乏層10の曲率半
径が大きくなり、良好な逆電圧阻止特性が得られる。Anode electrode 6 of diode having the above structure
When a reverse voltage is applied between the cathode electrode 7 and the cathode electrode 7, the depletion layer 10 expands from the PN junction defined by the anode region 3 and the N − epitaxial layer 2. Then, when the difference in voltage applied between the anode electrode 6 and the cathode electrode 7 exceeds a predetermined value, breakdown occurs. In the above operation, there is a problem that it becomes a hindrance in obtaining a good reverse voltage blocking characteristic. It is a problem of the radius of curvature of the cross-sectional shape of the depletion layer 10. That is, the radius of curvature of the depletion layer 10 in the portion a shown in FIG. 2 is smaller than the radius of curvature in the other portions of the depletion layer 10. As a result, the potential gradient in the vicinity of the portion a becomes large, electric field concentration occurs, and good reverse voltage blocking characteristics cannot be obtained. As a structure for increasing the radius of curvature at the portion a, there is a structure disclosed in JP-A-61-84830. FIG. 3 is a sectional view of a diode having the structure shown in the above publication. In the structure of this diode, the P-type impurity concentration is made lower and the diffusion depth of the P-type impurity is made shallower as it approaches the outer peripheral direction A in the anode region 3. Other configurations are similar to those of the diode shown in FIG. With this structure, the radius of curvature of the depletion layer 10 at the portion a does not become smaller than that of the other portions of the depletion layer 10. Therefore, electric field concentration does not occur in the portion a, and good reverse voltage blocking characteristics can be obtained. Furthermore, since the depletion layer 10 extends in the region of the anode region 3 where the P-type impurity concentration is low, the radius of curvature of the depletion layer 10 also increases, and good reverse voltage blocking characteristics can be obtained.
第４図は第３図に示したダイオードの製造工程を説明す
るための図であり、このうち第４図（ａ）はアノード領
域３を形成するためにN-エピタキシャル層２の表面に形
成したシリコン酸化膜12に写真製版の手法により不純物
導入孔13を設けた状態の一部平面図、第４図（ｂ）はア
ノード領域３形成後のＸ−Ｘ線での断面図である。FIG. 4 is a view for explaining the manufacturing process of the diode shown in FIG. 3, of which FIG. 4 (a) is formed on the surface of the N − epitaxial layer 2 to form the anode region 3. FIG. 4 (b) is a sectional view taken along line XX after the anode region 3 is formed, in which a part of the silicon oxide film 12 is provided with an impurity introduction hole 13 by a photolithography method.
第４図により、第３図に示したダイオードの製造工程の
概略を説明する。N+基板１上にN-エピタキシャル層２を
成長させる。次に、酸化を行ったあと、第４図（ａ）に
示したようにシリコン酸化膜12に不純物導入孔13を設け
る。その不純物導入孔13を介しN-エピタキシャル層２上
にＰ型不純物を導入し、その後熱処理することによりア
ノード領域３を形成する。このとき、外周方向Ａに近づ
くほど不純物導入孔13の開口面積が小さくなり、あるい
は外周方向Ａに近づくにつれ不純物導入孔13の間隔が徐
々に広くなるように不純物導入孔13を形成することによ
って、外周方向Ａに近づくほどＰ型不純物濃度を低く
し、かつＰ型不純物の拡散の深さを浅く形成するように
する。このようなアノード領域３の形成状態を第４図
（ｂ）に示す。次に、接合保護膜８を形成し、その後ア
ノード電極6,カソード電極7,電極９を形成する。このよ
うにして、外周方向Ａに近づくほどＰ型不純物濃度が低
く、かつＰ型不純物の拡散の深さを浅くし、曲率半径の
大きいアノード領域３を形成する。An outline of the manufacturing process of the diode shown in FIG. 3 will be described with reference to FIG. The N − epitaxial layer 2 is grown on the N + substrate 1. Next, after performing oxidation, an impurity introduction hole 13 is provided in the silicon oxide film 12 as shown in FIG. The anode region 3 is formed by introducing a P-type impurity into the N − epitaxial layer 2 through the impurity introduction hole 13 and then performing a heat treatment. At this time, the impurity introducing holes 13 are formed so that the opening area of the impurity introducing holes 13 becomes smaller as the distance from the outer peripheral direction A approaches, or the interval between the impurity introducing holes 13 becomes gradually wider as approaching the outer peripheral direction A. The P-type impurity concentration is made lower and the diffusion depth of the P-type impurity is made shallower as it approaches the outer peripheral direction A. The formation state of such an anode region 3 is shown in FIG. Next, the bonding protection film 8 is formed, and then the anode electrode 6, the cathode electrode 7, and the electrode 9 are formed. In this way, the closer to the outer peripheral direction A, the lower the P-type impurity concentration is, the shallower the P-type impurity diffusion depth is, and the anode region 3 having a large radius of curvature is formed.
また、ａ部での曲率半径を大きくし、電界集中を防止す
る他の方法としては、ディプレッションリングを設ける
ことが従来より知られている。すなわち、第５図に示す
ように、アノード領域３とフィールドリミッティングリ
ング４のとの間にＰ型不純物領域である環状のディプレ
ッションリング11を設けるものである。ディプレッショ
ンリング11を設けることにより空乏層10が第５図に示す
ように広がり、ａ部での曲率半径を大きくするものであ
る。Further, as another method of increasing the radius of curvature at the portion a to prevent the electric field from being concentrated, it has been conventionally known to provide a depletion ring. That is, as shown in FIG. 5, an annular depletion ring 11 which is a P-type impurity region is provided between the anode region 3 and the field limiting ring 4. By providing the depletion ring 11, the depletion layer 10 expands as shown in FIG. 5, and the radius of curvature at the portion a is increased.
ところで、N-エピタキシャル層２とアノード領域３によ
り規定されるPN接合は接合保護膜８により外部からの直
接の汚染から守られているが、空乏層10の形状は、接合
保護膜８上の電荷，接合保護膜８中の電荷より影響を受
け、表面近くの空乏層10の幅が内部での空乏層10の幅よ
り狭くなる。そのため、降状電圧は表面の空乏層10の幅
により決定されてしまい、所望の逆電圧阻止特性が得ら
れない。この問題を解決するにも上述したディプレッシ
ョンリング11が用いられる。ディプレッションリング11
を用いた構成は、前述した第５図のとおりである。ディ
プレッションリング11を新たに設けることにより、表面
付近での空乏層10の幅を十分に確保することができ、降
伏電圧は従来のように表面付近の空乏層10の幅により決
定されることがなく、所望の逆電圧阻止特性が得られ
る。また、表面付近の空乏層10の幅が内部の幅より狭く
ならないので、最大電界強度はディプレッションリング
11を設けない場合に比し小さくなる。そのため、空乏層
10が接合保護膜８上あるいは接合保護膜８中の電荷から
うける影響が小さくなり、安定した降伏電圧が得られ
る。第５図において、（ｂ）は（ａ）のＹ−Ｙに沿って
の電界強度の度合を示す。By the way, the PN junction defined by the N − epitaxial layer 2 and the anode region 3 is protected from direct contamination from the outside by the junction protective film 8, but the shape of the depletion layer 10 is the charge on the junction protective film 8. The width of the depletion layer 10 near the surface is narrower than the width of the depletion layer 10 inside, affected by the charges in the junction protective film 8. Therefore, the breakdown voltage is determined by the width of the depletion layer 10 on the surface, and the desired reverse voltage blocking characteristic cannot be obtained. The depletion ring 11 described above is also used to solve this problem. Depression ring 11
The configuration using is as shown in FIG. 5 described above. By newly providing the depletion ring 11, the width of the depletion layer 10 near the surface can be sufficiently secured, and the breakdown voltage is not determined by the width of the depletion layer 10 near the surface unlike the conventional case. , Desired reverse voltage blocking characteristics can be obtained. Also, since the width of the depletion layer 10 near the surface does not become narrower than the width inside, the maximum electric field strength is the depletion ring.
It is smaller than when 11 is not provided. Therefore, the depletion layer
The influence of 10 on the junction protective film 8 or the electric charge in the junction protective film 8 is reduced, and a stable breakdown voltage is obtained. In FIG. 5, (b) shows the degree of electric field strength along YY of (a).
従来、空乏層の曲率半径を大きくしたり、接合保護膜８
上の電荷及び接合保護膜８中の電荷から空乏層10が影響
を受けないようにするために、上記のような方法が取ら
れていた。Conventionally, the radius of curvature of the depletion layer is increased or the junction protective film 8
In order to prevent the depletion layer 10 from being affected by the charge above and the charge in the junction protective film 8, the above method has been taken.
しかし、アノード領域３のａ部の曲率半径を大きくする
のち第３図及び第４図により説明した方法をとる場合、
１ケ所でもＰ型不純物の拡散の深さが浅くなりすぎた
り、深くなりすぎたりすると、その部分での空乏層10の
曲率半径が小さくなる。その結果、アノード電極６とカ
ソード電極７の間に逆電圧を印加すると前記曲率半径が
小さくなった部分で電界集中が生じ、所望の逆電圧阻止
特性が得られないという問題点が生じ、これを防止する
ために精緻な写真製版技術が必要であるという問題点が
あった。However, when the method described with reference to FIGS. 3 and 4 is used after increasing the radius of curvature of the portion a of the anode region 3,
If the depth of diffusion of the P-type impurity becomes too shallow or too deep even at one place, the radius of curvature of the depletion layer 10 at that portion becomes small. As a result, when a reverse voltage is applied between the anode electrode 6 and the cathode electrode 7, electric field concentration occurs at the portion where the radius of curvature becomes small, and there arises a problem that desired reverse voltage blocking characteristics cannot be obtained. There is a problem in that a precise photoengraving technique is required to prevent this.
また、空乏層10の幅を適正に保つためにデプレッション
リング11を設ける場合、より安定した逆電圧阻止特性を
得るため以下のような構造にすることが提案されてい
る。すなわち、ディプレッションリング11を浅く形成す
ることである。こうすることにより、さらに空乏層10の
曲率半径を大きくし、より安定した逆電圧阻止特性が得
られる。しかし、一般にアノード領域３を構成するＰ型
不純物領域と、ディプレッションリング11を構成するＰ
型不純物領域は同時に形成される。そのため、上記よう
な構成にするためには、Ｐ型不純物を複数回に分けて行
い、別々にアノード領域３とディプレッションリング11
を形成する必要がある。この場合、工程数が増加し、製
造コストが上昇するという問題点があった。Further, in the case where the depletion ring 11 is provided in order to keep the width of the depletion layer 10 appropriate, it has been proposed to have the following structure in order to obtain a more stable reverse voltage blocking characteristic. That is, the depletion ring 11 is formed shallowly. By doing so, the radius of curvature of the depletion layer 10 is further increased, and a more stable reverse voltage blocking characteristic can be obtained. However, in general, the P-type impurity region forming the anode region 3 and the P-type impurity region forming the depletion ring 11 are formed.
The type impurity regions are formed at the same time. Therefore, in order to obtain the above structure, the P-type impurity is divided into a plurality of times, and the anode region 3 and the depletion ring 11 are separately formed.
Need to be formed. In this case, there has been a problem that the number of steps is increased and the manufacturing cost is increased.
また、ディプレッションリング11を設ける領域は、ダイ
オード本体の機能を発揮するのに必要な領域（以下能動
領域という）に十分な面積を確保するために、できるだ
け小さいほうが望ましい。能動領域の面積はダイオード
の取扱う電圧・電流でほぼ決定されてしまい、能動領域
の面積を小さくするのは困難である。そのため、チップ
サイズの縮小、ひいては製品コストの軽減を測るのに最
も簡単な方法がディプレッションリング11の領域を小さ
くすることになる。しかし、上記の要望は、逆電圧阻止
特性の安定化という面から見ると相反する要望であり、
上記要望を取り入れると逆電圧阻止特性が不安定になる
という問題点があった。Further, it is desirable that the region where the depletion ring 11 is provided is as small as possible in order to secure a sufficient area for a region (hereinafter referred to as an active region) required to exhibit the function of the diode body. The area of the active region is almost determined by the voltage and current handled by the diode, and it is difficult to reduce the area of the active region. Therefore, the simplest method for measuring the reduction of the chip size and hence the reduction of the product cost is to reduce the area of the depletion ring 11. However, the above requests are conflicting requests from the viewpoint of stabilizing the reverse voltage blocking characteristic,
If the above request is incorporated, there is a problem that the reverse voltage blocking characteristic becomes unstable.
この発明は上記のような問題点を解決するためになされ
たもので、より安定した逆電圧阻止特性を有し、かつチ
ップサイズの小さい半導体装置を得ること、及び、より
簡単な方法で前記半導体装置を製造することができる製
造方法を得ることを目的とする。The present invention has been made to solve the above problems, and has a more stable reverse voltage blocking characteristic and a semiconductor device having a small chip size, and a semiconductor device having a simpler method. It is an object to obtain a manufacturing method capable of manufacturing a device.
この発明に係る半導体装置は、第１導電型の基板と、基
板の一主面上に形成された第２導電型の第１の不純物領
域と、第１の不純物領域の外周部分を形成するように前
記基板の一主面上に形成され、不純物濃度が第１の不純
物領域より低い第２導電型の第２の不純物領域と、第２
の不純物領域から所定の距離を離し、かつ第２の不純物
領域をとり囲む形で前記基板の一主面上に帯状に形成さ
れたデプレッションリングたる不純物濃度が第１の不純
物領域よりも低い第２導電型の第３の不純物領域とを備
えている。A semiconductor device according to the present invention forms a first conductivity type substrate, a second conductivity type first impurity region formed on one main surface of the substrate, and an outer peripheral portion of the first impurity region. A second impurity region of a second conductivity type formed on one main surface of the substrate and having an impurity concentration lower than that of the first impurity region;
A second region having a lower impurity concentration than the first impurity region, which is a depletion ring formed in a strip shape on the one main surface of the substrate so as to be separated from the impurity region by a predetermined distance and surround the second impurity region. And a third impurity region of conductivity type.
この発明に係る半導体装置の製造方法は、不純物を導入
すべき領域に開口部に加えて非開口部を設けることによ
り不純物導入量を調整することができるマスクを用い、
前記基板の第1,第２及び第３の領域に前記第１の領域よ
りも前記第２及び第３の領域が不純物導入量が少なくな
るように、前記基板に第２導電型の不純物を導入する工
程と、不純物が導入された基板を熱処理することによ
り、第１の領域において第２導電型の第１の不純物領域
を形成するとともに、これと同時に第２の領域において
不純物濃度が第１の不純物領域の濃度より低く、第１の
不純物領域の外周部分を形成する第２導電型の第２の不
純物領域と、第３の領域において不純物濃度が第１の不
純物領域の濃度により低く、第２の不純物領域から所定
の距離を離し、かつ第２の不純物領域を取り囲む形で帯
状をなす第２導電型の第３の不純物領域とを形成する工
程とを備えている。A method of manufacturing a semiconductor device according to the present invention uses a mask capable of adjusting an impurity introduction amount by providing a non-opening portion in addition to an opening portion in a region where impurities are to be introduced,
Impurity of the second conductivity type is introduced into the substrate so that the amount of impurities introduced into the first, second and third regions of the second and third regions is smaller than that of the first region. And a heat treatment of the substrate into which the impurities have been introduced, a first impurity region of the second conductivity type is formed in the first region, and at the same time, the impurity concentration of the first region is set to the first region. A second impurity region of a second conductivity type, which has a concentration lower than that of the impurity region and which forms an outer peripheral portion of the first impurity region; and a third impurity region whose impurity concentration is lower than that of the first impurity region, Forming a strip-shaped third impurity region of the second conductivity type that is apart from the impurity region by a predetermined distance and surrounds the second impurity region.
この発明に係る半導体装置では、基板と第１の領域間に
逆電圧をかけることにより生じる空乏層は、不純物濃度
の低い領域、つまり第２及び第３の不純物領域内まで伸
び、最大電界強度は小さくなる。In the semiconductor device according to the present invention, the depletion layer generated by applying a reverse voltage between the substrate and the first region extends to a region having a low impurity concentration, that is, the second and third impurity regions, and the maximum electric field strength is Get smaller.
不純物を導入すべき領域に開口部に加えて非開口部を設
けることにより不純物導入量を調整することができるマ
スクを用い、基板の第1,第２及び第３の領域に第１の領
域よりも第２及び第３の領域の方が不純物導入量が少な
くなるように、基板に第２導電型の不純物を導入する。
その後、上記のようにして不純物が導入された基板に熱
処理を施し、第１の領域において第２導電型の第１の不
純物領域を形成するとともに、これと同時に第２及び第
３の領域において不純物濃度が第１の不純物領域の濃度
より低い第２導電型の第２及び第３の不純物領域を形成
する。By using a mask that can adjust the amount of impurities introduced by providing a non-opening in addition to an opening in the region where impurities should be introduced, the first, second, and third regions of the substrate can be formed from the first region. Also, impurities of the second conductivity type are introduced into the substrate so that the amount of impurities introduced into the second and third regions is smaller.
Thereafter, the substrate into which the impurities have been introduced as described above is subjected to a heat treatment to form a first impurity region of the second conductivity type in the first region, and at the same time, to form impurities in the second and third regions. A second conductivity type second and third impurity regions having a concentration lower than that of the first impurity region are formed.
第１図はこの発明の一実施例を示す図であり、このうち
（ａ）は半導体装置の断面を示し、（ｂ）は（ａ）のＹ
−Ｙでの電界強度の度合を示す。第１図（ａ）におい
て、第５図に示した従来のダイオードとの相違点は、ア
ノード領域３を外周方向Ａに近づくほどＰ型不純物の濃
度を低くし、かつＰ型不純物の拡散の深さを徐々に浅く
したこと及びディプレッションリング11のＰ型不純物の
濃度を低くしたことである。その他の構成は従来のダイ
オードと同様である。FIG. 1 is a diagram showing an embodiment of the present invention, in which (a) shows a cross section of a semiconductor device and (b) shows Y of (a).
The degree of electric field strength at -Y is shown. In FIG. 1 (a), the difference from the conventional diode shown in FIG. 5 is that the concentration of the P-type impurity is lowered as the anode region 3 is closer to the outer peripheral direction A and the diffusion depth of the P-type impurity is increased. That is, the depth is gradually reduced and the concentration of P-type impurities in the depletion ring 11 is reduced. Other configurations are similar to those of the conventional diode.
このようなダイオードのカソード電極６とアノード電極
７に逆電圧を印加したとする。ディプレッションリング
11のＰ型不純物濃度を低くし、かつ、アノード領域３の
外周方向ＡのＰ型不純物濃度を低くしているので、空乏
層10は第１図に示すようにディプレッションリング11内
及びアノード領域３内にまで大きく延びる。そのため、
従来と同じ設計サイズのディプレッションリング11を持
っていても最大電界強度は従来に比し小さくなり、従来
と同程度の最大電界強度を得ようとする場合は、従来に
比しディプレッションリング11の設置領域の幅を小さく
することができる。その結果、チップサイズは小さくな
り、製品コストの軽減が図れる。It is assumed that a reverse voltage is applied to the cathode electrode 6 and the anode electrode 7 of such a diode. Depletion ring
Since the P-type impurity concentration of 11 and the P-type impurity concentration of the anode region 3 in the outer peripheral direction A are reduced, the depletion layer 10 is formed in the depletion ring 11 and the anode region 3 as shown in FIG. It extends greatly inside. for that reason,
Even if you have a depletion ring 11 of the same design size as before, the maximum electric field strength will be smaller than before, and if you want to obtain the same maximum electric field strength as before, install the depletion ring 11 compared to before. The width of the area can be reduced. As a result, the chip size is reduced and the product cost can be reduced.
また、アノード領域３において、外周方向Ａに近づくに
つれて徐々にＰ型不純物の拡散の深さを浅くし、曲率半
径を大きくなるようにしている。従って、従来のように
（第２図参照）ａ部分において、空乏層10の幅が狭くな
ることがなく、より平面接合に近くなる。そのためａ部
分での電界集中を防止でき、より安定な逆電圧阻止特性
を得ることができる。Further, in the anode region 3, the depth of diffusion of the P-type impurities is gradually reduced as the position approaches the outer peripheral direction A, and the radius of curvature is increased. Therefore, the width of the depletion layer 10 does not become narrower in the portion a as in the conventional case (see FIG. 2), and it becomes closer to the planar junction. Therefore, it is possible to prevent the electric field from being concentrated at the portion a, and to obtain a more stable reverse voltage blocking characteristic.
次に、上記のようなダイオードの製造方法について説明
する。N+基板１上にN-エピタキシャル層２を形成する。
次に、ガラスマスクパターンを用いＰ型不純物をN-エピ
タキシャル層２上に付着させる。このとき、Ｐ型の不純
物濃度を薄くしたい領域（アノード領域３の外周方向Ａ
の領域，デプレッションリング11となる領域）が細やか
なパターン（ストライプ状，短冊状，メッシュ状等）に
分割されたガラスマスクパターンを用いる（第４図
（ａ）参照）。このようなガラスマスクパターンを用い
一度に、Ｐ型不純物をN-エピタキシャル層２上の付着さ
せる。すると、単位面積あたりのＰ型不純物の付着量に
差が生じる。その後、長時間のドライブ拡散により、上
記パターンに従って分割して付着されたＰ型不純物を一
体化することにより、アノード領域３及びディプレッシ
ョンリング11を形成する。このようにして形成されたア
ノード領域３は、外周方向Ａに近づくほどＰ型の不純物
の濃度が低く、かつ、その拡散の深さが浅くなる。ま
た、ディプレッションリング11のＰ型不純物の濃度は、
従来より低くなる。その後、従来と同様、アノード電極
6,カソード電極7,接合保護膜8,電極９を形成する。上記
のような方法によると、一回の拡散工程による異なる濃
度と異なる拡散深さを有するアノード領域３とディプレ
ッションリング11が形成でき、作業工程増加によるコス
ト上昇はない。また、従来のように１カ所でもＰ型不純
物の拡散の深さが浅くなったり深くなったりすることに
よりアノード領域３の曲率半径が小さくなっても、ディ
プレッションリング11があるので、従来ほど電界集中は
生じず、逆電圧阻止特性が従来ほど悪化しない。また、
ディプレッションリング11の部分において、上記のよう
な現象が生じ、ディプレッションリング11の曲率半径が
小さくなっても、ディプレッションリング11はフローテ
ィング状態にあるので、逆電圧阻止特性には影響しな
い。従って、従来ほど精緻な写真製版技術は必要ない。Next, a method for manufacturing the above diode will be described. An N − epitaxial layer 2 is formed on the N + substrate 1.
Next, a P-type impurity is deposited on the N − epitaxial layer 2 using a glass mask pattern. At this time, a region where the P-type impurity concentration is desired to be reduced (in the outer peripheral direction A of the anode region 3)
The glass mask pattern is used in which the area (1) and the area to be the depletion ring 11) are divided into fine patterns (stripe, strip, mesh, etc.) (see FIG. 4 (a)). Using such a glass mask pattern, P-type impurities are deposited on the N − epitaxial layer 2 at a time. Then, a difference occurs in the amount of P-type impurities attached per unit area. Then, the anode region 3 and the depletion ring 11 are formed by integrating the P-type impurities divided and adhered according to the above pattern by drive diffusion for a long time. The anode region 3 thus formed has a lower concentration of P-type impurities and a shallower depth of diffusion as it approaches the outer peripheral direction A. The concentration of P-type impurities in the depletion ring 11 is
It will be lower than before. After that, the anode electrode
6, the cathode electrode 7, the bonding protection film 8 and the electrode 9 are formed. According to the above method, the anode region 3 and the depletion ring 11 having different concentrations and different diffusion depths can be formed by one diffusion process, and the cost does not increase due to the increase in the work process. Further, even if the radius of curvature of the anode region 3 becomes small due to the depth of diffusion of the P-type impurity becoming shallow or deep even in one place as in the conventional case, the depletion ring 11 is provided, so that the electric field concentration is as high as in the conventional case. Does not occur and the reverse voltage blocking characteristic does not deteriorate as much as the conventional one. Also,
Even if the above-described phenomenon occurs in the depletion ring 11 and the radius of curvature of the depletion ring 11 becomes small, the depletion ring 11 is in the floating state, so that it does not affect the reverse voltage blocking characteristic. Therefore, a more precise photoengraving technique than the conventional one is not required.
なお、上記実施例ではダイオードについて説明したが、
トランジスタ，ゲートターンオフサイリスタ等のプレー
ナ等の電力用半導体素子にもこの発明は適用でき、上記
実施例と同様の効果が得られる。また、上記実施例にお
いて、Ｐ型とＮ型を逆にしてもよい。Although the diode has been described in the above embodiment,
The present invention can also be applied to power semiconductor devices such as transistors and gate turn-off thyristors, and the like, and the same effects as those of the above embodiments can be obtained. Further, in the above embodiment, the P type and the N type may be reversed.
以上のように、請求項１記載の半導体装置によれば、基
板の一主面上に形成され、不純物濃度が第１の不純物領
域より低い第２導電型の第２及び第３の不純物領域を備
えているので、基板と第１の不純物領域に逆電圧を印加
すると、基板と第１の不純物領域とにより規定されるPN
接合部より生じる空乏層は、第２及び第３の不純物領域
内まで伸び、最大電界強度が小さくなる。そのため、最
大電界強度を従来と同じに保つながら、チップサイズを
小さくすることができ、製品コストを軽減することがで
きるという効果がある。また、第２及び第３の不純物領
域を設けているので、空乏層の曲率半径が著しく小さく
なることがないとともに、表面からの影響により空乏層
の幅がせまくなることを防止することができ、安定した
逆電圧阻止特性が得られる。As described above, according to the semiconductor device of the first aspect, the second conductivity type second and third impurity regions formed on the one main surface of the substrate and having the impurity concentration lower than that of the first impurity region are formed. Therefore, when a reverse voltage is applied to the substrate and the first impurity region, the PN defined by the substrate and the first impurity region is provided.
The depletion layer generated from the junction extends into the second and third impurity regions, and the maximum electric field strength decreases. Therefore, there is an effect that the chip size can be reduced and the product cost can be reduced while keeping the maximum electric field strength the same as the conventional one. In addition, since the second and third impurity regions are provided, the radius of curvature of the depletion layer is not significantly reduced, and the width of the depletion layer can be prevented from becoming narrow due to the influence from the surface. Stable reverse voltage blocking characteristics can be obtained.
請求項２記載の半導体装置の製造方法によれば、第１導
電型の基板を準備する工程と、不純物を導入すべき領域
に開口部に加えて非開口部を設けることにより不純物導
入量が調整されるマスクを用い、前記基板の第1,第２及
び第３の領域に前記第１の領域よりも前記第２及び第３
の領域の方が不純物導入量が少なくなるように、前記基
板に第２導電型の不純物を導入する工程と、不純物が導
入された前記基板を熱処理することにより、前記第１の
領域において第２導電型の第１の不純物領域を形成する
とともに、これと同時に不純物濃度が前記第１の不純物
領域の濃度より低い第２導電型の第２及び第３の不純物
領域を形成する工程とを備えているので、第１の不純物
領域及び第2,第３の不純物領域を同一工程により同時に
形成でき、製造コストが上昇しないという効果があると
ともに、第２の不純物領域に加えて第３不純物領域を設
けているため、第３の不純物領域を設けない場合に比べ
て、上記の不純物導入工程においてさほど精緻な写真製
版技術を必要としないという効果がある。According to the method of manufacturing a semiconductor device according to claim 2, the amount of impurity introduction is adjusted by preparing a substrate of the first conductivity type and providing a non-opening portion in addition to the opening portion in the region where the impurity is to be introduced. Using a mask formed on the first, second and third regions of the substrate, the second and third regions more than the first region.
In the first region, the second conductivity type impurity is introduced into the substrate so that the amount of the impurity introduced into the first region is smaller, and the substrate in which the impurity is introduced is heat-treated. Forming a first conductivity type impurity region, and at the same time forming second conductivity type second and third impurity regions having an impurity concentration lower than that of the first impurity region. Since the first impurity region and the second and third impurity regions can be simultaneously formed in the same step, the manufacturing cost is not increased, and the third impurity region is provided in addition to the second impurity region. Therefore, as compared with the case where the third impurity region is not provided, there is an effect that a so precise photolithography technique is not required in the above-mentioned impurity introduction step.
第１図はこの発明の一実施例を示す図、第２図は従来の
ダイオードを示す断面図、第３図ないし第５図は第２図
に示したダイオードの改良ダイオードの問題点を説明す
るための図である。 図において、２はN-エピタキシャル層、３はアノード領
域、11はディプレッションリングである。 なお、各図中同一符号は同一または相当部分を示す。FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a sectional view showing a conventional diode, and FIGS. 3 to 5 are diagrams for explaining the problems of the improved diode of the diode shown in FIG. FIG. In the figure, 2 is an N - epitaxial layer, 3 is an anode region, and 11 is a depletion ring. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (2)
純物領域と、 前記第１の不純物領域の外周部分を形成するように前記
基板の一主面上に形成され、不純物濃度が前記第１の不
純物領域より低い第２導電型の第２の不純物領域と、 前記第２の不純物領域から所定の距離を離し、かつ前記
第２の不純物領域を取り囲む形で前記基板の一主面上に
帯状に形成された不純物濃度が前記第１の不純物領域よ
り低い第２導電型の第３の不純物領域とを備えたことを
特徴とする半導体装置。1. A first conductivity type substrate, a second conductivity type first impurity region formed on one main surface of the substrate, and an outer peripheral portion of the first impurity region. A second impurity region of a second conductivity type formed on the one main surface of the substrate and having an impurity concentration lower than that of the first impurity region; A second conductivity type third impurity region having a lower impurity concentration than the first impurity region, the impurity concentration being formed in a strip shape on the one main surface of the substrate so as to surround the second impurity region. Semiconductor device.
けることにより不純物導入量を調整することができるマ
スクを用い、前記基板の第1,第２及び第３の領域に前記
第１の領域よりも前記第２及び第３の領域の方が不純物
導入量が少なくなるように、前記基板に第２導電型の不
純物を導入する工程と、 不純物が導入された前記基板を熱処理することにより、
前記第１の領域において第２導電型の第１の不純物領域
を形成するとともに、これと同時に前記第２の領域にお
いて不純物濃度が前記第１の不純物領域の濃度より低
く、前記第１の不純物領域の外周部分を形成する第２導
電型の第２の不純物領域と、前記第３の領域において不
純物濃度が前記第１の不純物領域の濃度より低く、前記
第２の不純物領域から所定の距離を離し、かつ前記第２
の不純物領域を取り囲む形で帯状をなす第２導電型の第
３の不純物領域とを形成する工程とを備える半導体装置
の製造方法。2. A step of preparing a substrate of the first conductivity type, and a mask capable of adjusting an impurity introduction amount by providing a non-opening in addition to an opening in a region where an impurity is to be introduced, Impurities of the second conductivity type are applied to the substrate so that the amount of impurities introduced into the first, second and third regions of the substrate is smaller in the second and third regions than in the first region. By the step of introducing and by heat-treating the substrate into which impurities are introduced,
The first impurity region of the second conductivity type is formed in the first region, and at the same time, the impurity concentration in the second region is lower than the concentration of the first impurity region, and the first impurity region is formed. The second impurity region of the second conductivity type forming the outer peripheral portion of the second impurity region and the third region have an impurity concentration lower than that of the first impurity region and separated from the second impurity region by a predetermined distance. And the second
Forming a strip-shaped third impurity region surrounding the impurity region of the second conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29524188A JPH07105485B2 (en) | 1988-11-22 | 1988-11-22 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29524188A JPH07105485B2 (en) | 1988-11-22 | 1988-11-22 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02142184A JPH02142184A (en) | 1990-05-31 |
| JPH07105485B2 true JPH07105485B2 (en) | 1995-11-13 |
Family
ID=17818043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29524188A Expired - Lifetime JPH07105485B2 (en) | 1988-11-22 | 1988-11-22 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07105485B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0661753A1 (en) * | 1994-01-04 | 1995-07-05 | Motorola, Inc. | Semiconductor structure with field limiting ring and method for making |
| JP3628613B2 (en) * | 1997-11-03 | 2005-03-16 | インフィネオン テクノロジース アクチエンゲゼルシャフト | High pressure resistant edge structure for semiconductor components |
| AU2002351686B2 (en) * | 2002-01-15 | 2008-04-10 | Robert Bosch Gmbh | Semiconductor arrangement comprising a pn-transition and method for producing a semiconductor arrangement |
| JP2004281949A (en) * | 2003-03-19 | 2004-10-07 | Nippon Inter Electronics Corp | Semiconductor device and its manufacturing method |
| JP6020317B2 (en) | 2013-04-05 | 2016-11-02 | 三菱電機株式会社 | Semiconductor element |
-
1988
- 1988-11-22 JP JP29524188A patent/JPH07105485B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02142184A (en) | 1990-05-31 |
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