JPH07105272A - Bus connection system - Google Patents

Abstract

PURPOSE:To improve signal transmission characteristics of a bus line by connecting external terminals, which are at different array positions among plural external terminals, to the same bus line in common between mutually different semiconductor integrated circuits. CONSTITUTION:Address terminals A1-A6 are provided as external terminals of memory devices. An address bus ABUS to which the memory devices IC1-IC6 are connected includes six bus lines a11-a6 and has a power line 30 for supplying high-potential side electric power Vcc to the memory devices IC1-IC6 and a ground line 40 as a reference voltage line. Then external terminals which are at different array places among the address terminals A1-A6 are connected to the same bus line in common among the mutual different memory devices. Therefore, variance in capacity among the bus lines a1-a6 is nearly eliminated and the maximum capacity on the bus lines is reducible, so that the address signal transmission characteristics can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus connection system for a semiconductor integrated circuit in which a plurality of external terminals having the same function are arranged, and more particularly to a technique effectively applied to a memory module.

[0002]

2. Description of the Related Art A memory module is capable of addressing a plurality of memories arranged on, for example, a mounting board based on a signal supplied from an external address input terminal common to them. Eight 1-bit RAMs (random access memories) can be mounted to form a × 8-bit memory module. In such a memory module, the address signal supplied from the microprocessor or the like may be directly supplied to the external address input terminal provided on the mounting substrate, as in the case where the semiconductor memory device is used alone.

As an example of a document describing a memory card which is an example of a memory module, there are pages 334 to 336 of "Integrated Circuit Application Handbook" published by Asakura Shoten on June 30, 1981.

[0004]

For example, in a memory module, in a plurality of memory devices, a plurality of address terminals and the like are arranged at a predetermined pitch. In that case, the address terminals at the same arrangement location are common. Is coupled to the bus line. That is, the address terminals A1 of all memory devices are commonly connected to the same bus line. Here, the bus line refers to individual wirings forming the bus. However, when focusing on the capacitance (electrostatic capacitance) of the address terminals in one memory device, the capacitance is not constant depending on the address terminals. Therefore, as described above, the address terminals at the same array location are connected to a common bus line. It has been found by the present inventor that the method causes a large variation in capacitance between bus lines, which causes deterioration of the transfer characteristic of the address signal.

An object of the present invention is to provide a technique for improving the signal transfer characteristic of a bus line in a bus connection of a plurality of semiconductor integrated circuits.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, among the semiconductor integrated circuits different from each other, the external terminals of different arrangement positions among the plurality of external terminals are wired so as to be commonly connected to the same bus line.

If attention is paid to the address terminals,
In the semiconductor integrated circuits different from each other, the address terminals in which the plurality of address terminals are arranged are arranged so as to be commonly connected to the same bus line.

Further, when focusing on the data terminal,
Between the different semiconductor integrated circuits, the data terminals having different arrangement positions among the plurality of data terminals are wired so as to be commonly connected to the same bus line.

[0011]

According to the above-mentioned means, it is possible to reduce the capacitance of the bus lines by connecting the external terminals of the plurality of external terminals, which are arranged at different positions, to the same bus line in common between different semiconductor integrated circuits. Variability is reduced, which achieves improved address and data signaling characteristics.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a memory module which is an embodiment of the method of the present invention.

This memory module is not particularly limited, but six memory devices IC1 to IC are mounted on the mounting substrate 1.
6 built-in, and 6 external address input terminals AT1 to AT
6 and 6 external data input / output terminals I / O1 to I / O6
Therefore, it is configured as a DRAM module of several megabytes as a whole. The above memory devices IC1 to IC
6, which is not particularly limited, is a DRAM (dynamic random access memory) as an example of a semiconductor integrated circuit.
Memory) is applied. Then, a row address strobe signal RAS * (* indicates low active) and a column address strobe signal CAS are externally provided to the mounting substrate 1.
* And the read / write signal R / W * are supplied as external control signals.

In FIG. 1, in the above memory module,
Memory devices IC1 to IC6 and address bus ABUS
Is shown.

Although not particularly limited, as typically shown in FIG. 1, the memory device IC1 has address terminals A1 to A6 in addition to the high-potential-side power supply Vcc terminal and the ground terminal GND. These address terminals A1 to A
Reference numeral 6 is an external terminal as a memory device. still,
Actually, terminals for exchanging various control signals and data are provided, but they are omitted in FIG. 1 for convenience of description.

The address bus ABUS to which the memory devices IC1 to IC6 are coupled is composed of six bus lines a.
1 to a6 are included. Incidentally, the line 30 is a memory device I
Reference numeral 40 is a power supply line for supplying the high potential side power supply Vcc to C1 to IC6, and 40 is a ground line as a reference voltage line.

Here, according to the prior art, the address terminals of the same array location among the plurality of memory devices IC1 to IC6 are coupled to a common bus line.
In this embodiment, in order to improve the signal propagation characteristics of the bus,
As shown in FIG. 1, among the memory devices different from each other, the external terminals having different arrangement positions among the plurality of address terminals A1 to A6 are commonly connected to the same bus line. For example, the bus line a1 includes the address terminal A1 of the memory device IC1 and the memory device IC2.
Address terminal A2, memory device IC3 address terminal A3, memory device IC4 address terminal A4,
The address terminal A5 of the memory device IC5 and the address terminal A6 of the memory device IC6 are coupled.
Further, on the bus line a2, the address terminal A2 of the memory device IC1, the address terminal A3 of the memory device IC2, the address terminal A4 of the memory device IC3, the address terminal A5 of the memory device IC4, the address terminal A6 of the memory device IC5, and the memory Device IC6
Address terminal A1 is connected. Further, the bus line a3 has an address terminal A of the memory device IC1.
3, address terminal A4 of memory device IC2, address terminal A5 of memory device IC3, memory device I
The address terminal A6 of C4, the address terminal A1 of the memory device IC5, and the address terminal A2 of the memory device IC6 are coupled.

In the semiconductor integrated circuit, the capacitance viewed from an external terminal such as an address terminal is determined by the surface area of the input first stage gate and the lead frame forming the external terminal. Then, such capacitances have almost the same value in the semiconductor integrated circuits having the same product number. That is, when the capacity of the address terminal a1 of the memory device IC1 is 6 pF (picofarad), the other memory devices IC2 to IC6
Even at the same address terminal A1 in, the value is 6 pF. In such a memory device having the same part number, the capacities of the same address terminals are almost the same. Therefore, when the same terminals are commonly connected to a bus line as in the conventional method, the variation in the capacity between the bus lines is very large. turn into. For example, address terminals A1, A2, A3
The capacitances of A4, A5, and A6 are 6 pF and 5 p, respectively.
In the case of F, 4pF, 4pF, 4pF, and 5pF, if the bus line a1 is commonly connected by the conventional method, the capacitance of the bus line a1 becomes 36 pF (= 6 × 6).
The capacitance of 2, a6 is 30 pF (= 6 × 5), and the capacitance of the bus lines a3, a4, a5 is 24 pF (= 6 ×).
4). In this case, the variation between the bus lines a1 to a6 is 36 to 24 pF, and the maximum capacitance of the bus line is 36.
pF.

On the other hand, as in the method of this embodiment, a plurality of address terminals A1 are provided between different memory devices.
When external terminals of different arrangement positions among A6 to A6 are commonly connected to the same bus line, a1 = a2 = a3 = a4 = a5 = a6 = (6 + 5 + 4 +
4 + 4 + 5) = 28 pF, and the capacitance variation between the bus lines a1 to a6 is set to a negligible value. Moreover, since the maximum capacity of the bus line is 28 pF, the maximum capacity of the conventional method is 3
It is smaller than 6 pF. When such a bus connection method is adopted, the physical address of the memory module is different from that in the conventional method, but the logical address does not change and no trouble occurs in the memory operation.

According to the above embodiment, the following operational effects can be obtained. (1) Between memory devices different from each other, the external terminals having different arrangement positions among the plurality of address terminals A1 to A6 are commonly connected to the same bus line, so that the variation in capacitance between the bus lines a1 to a6. Can be substantially zero, the maximum capacity of the bus line can be reduced, and the address signal transfer characteristics in the bus lines a1 to a6 can be improved.

(2) The number of external terminals tends to increase due to the higher integration of semiconductor integrated circuits. When the number of external terminals increases in this way, it is difficult to suppress variations in capacitance between the external terminals due to the layout. In such a case, as in the above-described embodiment, the different external terminals of the plurality of address terminals A1 to A6, which are arranged differently, are shared by the same bus line between the different memory devices. If they are connected, the improvement of the address signal transfer characteristic is remarkable.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the bus connection of the address terminal was explained as an example of the external terminal, but other external terminals such as the data input terminal, the data output terminal,
In the bus connection of I / O terminals and the like, as in the above-described embodiment, the different external terminals of the plurality of external terminals, which are arranged at different locations, are commonly connected to the same bus line between the different memory devices. The signal transfer characteristics on the data bus can be improved.

In the above description, the invention made by the present inventor is the field of application behind the invention.
Although the case where the present invention is applied to the memory module by M has been described, the present invention is not limited thereto, and can be applied to various memory boards such as personal computers, and various board systems adopting the bus system.

The present invention can be applied on condition that a plurality of external terminals having at least the same function are arranged.

[0026]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, among different semiconductor integrated circuits, external terminals of different arrangement positions among a plurality of external terminals are commonly connected to the same bus line,
Since the variation in capacitance in the bus line is reduced,
It is possible to improve the signal transfer characteristics in the bus line.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a connection relationship between a memory device and an address bus in a memory module to which a method according to an embodiment of the present invention is applied.

FIG. 2 is an overall configuration block diagram of the memory module.

[Explanation of symbols]

 1 mounting board 30 power line 40 ground line IC1 to IC6 memory device AT1 to AT6 external address input terminal I / O1 to I / O6 external data input / output terminal ABUS address bus a1 to a6 bus line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ryo Saeki 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division

Claims (3)

[Claims] 1. A bus connection method for a semiconductor integrated circuit, wherein a plurality of external terminals having the same function are arranged, wherein the different external terminals of the plurality of external terminals are arranged at different locations. However, the bus connection method is characterized in that wiring is performed so as to be commonly connected to the same bus line. 2. In a bus connection method of a semiconductor integrated circuit in which a plurality of address terminals for taking in an address signal are arranged, different semiconductor integrated circuits have different arrangement positions among the plurality of address terminals. A bus connection method in which address terminals are wired so that they are commonly connected to the same bus line. 3. A bus connection method for a semiconductor integrated circuit, comprising a plurality of data terminals arranged for enabling data exchange with the outside, wherein the plurality of data terminals are provided between different semiconductor integrated circuits. Among them, the bus connection method characterized in that the data terminals having different arrangement locations are wired so as to be commonly connected to the same bus line.