JPH07105168A - Microcomputer - Google Patents

Abstract

PURPOSE:To provide a microcomputer which can rewrite information without detaching the semiconductor package of an EPROM from a printed circuit board body. CONSTITUTION:This microcomputer is equipped with a serial interface circuit 2 which converts serial data 101 into parallel data and outputs them, a serial interface circuit 2 which converts parallel data read out of the EPROM 3 and outputs them, a write data storage part 5 which temporarily stores the parallel data outputted from the circuit 2, a read data storage part 6 which temporarily stores parallel data read out of a ROM 3, a control part 7 which sets a write or read mode for the ROM 3 through a CPU 1, an address setting part 8 which sets an address of the ROM 3 when data are written or read, an address control part 9 which selects the address of the setting part 8 and specifies the address of the ROM 3, and an instruction control part 10 which receives instructions from the ROM 3 and an FROM 4, and selects the instruction from the FROM 4 and supplies it to the CPU 1 in control mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer containing an EPROM.

[0002]

2. Description of the Related Art Generally, rewritable EP of stored contents
In a microcomputer having a built-in ROM, the EPROM is used as a data storage means during software development of the microcomputer. For example, in the process of developing electric appliances controlled by a microcomputer, the development work after actually assembling the set of electric appliances as a prototype mainly focuses on debugging software for operating the microcomputer. However, if a defect is found during debugging, it is necessary to correct the software. In such a case, the software that needs to be corrected is usually written in the EPROM, so in practice, the stored content of the EPROM mounted as a semiconductor package is changed in the set of the electric appliance. It will be a work to do.

Conventional EPRO in such a case
As a means for changing the memory contents of M, E ROM eraser erases all the memory contents of the EPROM, and then E
A means of writing new information by a PROM writer is used. In that case, when changing the stored contents of the EPROM mounted on the printed circuit board of the semiconductor integrated circuit, the work of removing the semiconductor package including the EPROM from the printed circuit board and rewriting the EPROM information is required. Has been done.

A memory for storing the information read from the master ROM as a memory content changing means for avoiding the above-mentioned means of removing the semiconductor package including the EPROM from the printed board and rewriting the information,
RO for writing the information read in the memory into the EPROM
A rewriting adapter connected by a cable to the EPROM rewriting device body having an M writer,
By directly mounting on the EPROM mounted on the printed circuit board, ultraviolet rays are radiated from the lamp built in the rewriting adapter to erase the stored contents of the EPROM via a command from the main body of the EPROM rewriting device. However, there has been proposed a means for writing information in the EPROM via the rewriting adapter according to a command from the ROM writer (eg, Japanese Patent Laid-Open No. 2-310399).
Issue).

On the other hand, in a microcomputer which generally has a built-in EPROM, an EP
As for ROM writing / reading, as described above, E
A PROM writer is used. For this purpose, as shown in FIG. 3, a plurality of terminals used for inputting a mode signal 301 for setting an operation mode such as writing / reading to the EPROM 3, and In order to input the data actually written in the EPROM 3 or to output the data read from the EPROM 3, a plurality of terminals provided for input / output of write / read data and the CPU 1 are written in the EPROM 3. Address or EP
A terminal for setting an address 303 to be read from the ROM 3 is provided as a dedicated terminal for the microcomputer.

[0006]

In the conventional microcomputer described above, a semiconductor chip having an EPROM mounted therein is used as a memory content changing unit of the built-in EPROM each time the information in the EPROM is rewritten. The information is rewritten by removing it from the printed circuit board on which the microcomputer is formed, and after the rewriting of information, the semiconductor chip containing the EPROM must be attached to the printed circuit board again. For this reason, a special tool or technique for exclusive use is required, and the number of man-hours for the work is increased, and the semiconductor chip itself is damaged due to the repetition of the above-mentioned work, and the contact failure between the semiconductor chip and the printed circuit board. There is a drawback that it becomes an incentive.

Further, the above-mentioned proposal example (Japanese Patent Laid-Open No. 2-103)
No. 799), it is necessary to use the EPROM writer when rewriting the information in the EPROM by using the means for changing the stored content using the rewriting adapter. This EPROM writer is used. As described above, the EPROM has a plurality of terminals for setting operation modes such as writing / reading.
A plurality of terminals used for input / output of write / read data, and terminals for setting write / read addresses corresponding to EPROMs are required as dedicated terminals for the microcomputer, respectively. Due to the increase in the number of these dedicated terminals, There is a drawback that the terminal function becomes complicated and the area occupied by the semiconductor chip increases.

[0008]

A microcomputer of the present invention is an erasable programmable read-only memory (hereinafter referred to as an EPROM) and a firmware read-only memory that stores instructions for controlling write / read operations on the EPROM. In a microcomputer including at least a memory (hereinafter referred to as FROM), serial data to be written to the EPROM is externally input, converted into parallel data and output, and read out from the EPROM. A serial interface circuit that converts parallel data to serial data and outputs the data to the outside, and a write data storage unit that temporarily stores the parallel data output from the serial interface circuit as an input,
Either a write mode or a read mode corresponding to the EPROM is set via a read data storage unit for inputting and temporarily storing parallel data read from the EPROM, and a control signal from the CPU. An address setting unit that sets a write address for the EPROM in the write mode and a read address for the EPROM in the read mode via a control signal from the mode control unit and the CPU, and the address setting unit. And the above C
In the normal operation mode in which the addresses output from the PUs are respectively received and set through a predetermined mode switching signal, the address output from the CPU is selected to specify the address of the EPROM to switch the mode. In the write / read control mode set via a signal, the addresses are output from the EPROM and the FROM, and the address control unit that selects the address output from the address setting unit and specifies the address of the EPROM. In the normal operation mode set via the mode switching signal, the EPR is received.
A command output from the OM is selected and supplied to the CPU, and write / write is set via the mode switching signal.
In the read control mode, a command control unit for selecting a command output from the FROM and supplying it to the CPU is provided as an interface unit corresponding to the EPROM.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, the CPU 1
, Serial interface circuit 2, and EPROM 3
A FROM 4, a write data storage unit 5, a read data storage unit 6, a mode control unit 7, an address setting unit 8, an address control unit 9, and an instruction control unit 10. The FROM4 is an EPROM.
3 is a read-only memory that stores instructions for controlling the write / read operation for the memory cell 3. Further, FIGS. 2A and 2B are flowcharts showing operation procedures at the time of writing and reading of this embodiment, respectively. The operation of this embodiment will be described below with reference to FIGS. 1 and 2.

First, the operation mode will be described. In the present embodiment, the mode switching signal 102 input to the address control unit 9 and the instruction control unit 10 from the outside.
Two operation modes including a normal operation mode and a write / read control mode are set as operation modes corresponding to the EPROM 3 via.

EPR depending on the above operation mode
Regarding the address designation for the OM3, in the normal operation mode, the address output from the CPU 1 via the address control unit 9 is selected, the address for the EPROM 3 is designated, and in the write / read control mode, the address is designated. The address set in the address setting unit 8 is selected via the control unit 9,
An address for EPROM 3 is designated. On the other hand, similarly, regarding the selection of the command input to the CPU 1 which is influenced by the above-mentioned operation mode, in the normal operation mode, the command output from the EPROM 3 is selected via the command control unit 10 to be transmitted to the CPU 1. In the write / read control mode, the command output from the FROM 4 via the command control unit 10 is selected and supplied to the CPU 1.

The EPR will be described below with reference to FIGS. 1 and 2.
The operation in the write / read control mode corresponding to OM3 will be described.

First, in response to the mode switching signal 102 inputted from the outside, the address control section 9 and the instruction control section 1 are received.
Both 0 are in the operation state corresponding to the write / read control mode, and a state is set in which the address set in the address setting unit 8 is selected via the address control unit 9 and designated and input to the EPROM 3. Further, the state in which the CPU 1 is controlled by the instruction from the FROM 4 is set via the instruction control unit 10.

At the time of writing to the EPROM 3 (see FIG.
In (a), first, the inhibit mode in which the operation of the EPROM 3 is stopped is set to the mode control unit 7.
(Step 201). Further, the serial data 101 written in the EPROM 3 is input from the external device, the serial data 101 is input to the serial interface circuit 2 and converted into parallel data (step 202), and the conversion is performed. The output parallel data is transferred to the write data storage unit 5 and temporarily stored and set (step 203). Next, the address setting unit 8 sets the address in the EPROM 3 in which the parallel data is written (step 204), and the mode control unit 7 sets the write mode (step 205). The parallel data stored in the write data storage unit 5 is set by the address setting unit 8 E
It is written in the address of PROM3 (step 20).
6). After the end of the operation of step 206, the process returns to step 201, and the above-mentioned operation is repeatedly executed, and the EPR is performed.
When the write operation for all the addresses in OM3 is completed, the write operation is completed.

When reading from the EPROM 3 (see FIG. 2B), first, an inhibit mode for stopping the operation of the EPROM 3 is set in the mode control section 7 (step 211). Next, the address in the EPROM 3 to be read is set in the address setting section 8 (step 212), and the read mode is set in the mode control section 7 (step 213), whereby the address setting section 8 sets it. The stored contents of the address of the EPROM 3 are read as parallel data (step 214).
The parallel data read in step 214 is temporarily stored and set in the read data storage section 6 (step 215), and the inhibit mode for stopping the operation of the EPROM 3 again is set in the mode control section 7 (step 216). Next, the read parallel data stored and set in the read data storage unit 6 is transferred to the serial interface circuit 2 via the internal bus (step 217), and the serial interface circuit 2 serially reads the serial data. The data is converted and output to an external device (step 218). After the operation of step 218 is completed, the process returns to step 212, and the above-described operation is repeatedly executed to check the reading of all addresses in the EPROM 3. The series of writing / reading operations for the EPROM 3 is executed according to dedicated software stored in the FROM 4.

[0017]

As described above, the present invention provides the EPR.
By providing a dedicated interface circuit corresponding to the OM and accessing the EPROM, the EP
It is possible to write / read data in a state where the semiconductor package containing the ROM is mounted on the printed circuit board as it is, and it is possible to avoid damage or the like in the semiconductor package. There is an effect that it is possible to prevent a contact failure between them.

Further, since writing to the EPROM can be performed through serial communication without using the EPROM writer, an address setting terminal and a mode setting terminal required when accessing the EPROM. Further, there is an effect that it is not necessary to provide a data transfer terminal or the like on the semiconductor package or the like, and the area occupied by the semiconductor chip is also reduced by this.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a flowchart of an operation procedure of the present embodiment.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 CPU 2 Serial Interface Circuit 3 EPROM 4 FROM 5 Write Data Storage Section 6 Read Data Storage Section 7 Mode Control Section 8 Address Setting Section 9 Address Control Section 10 Command Control Section

Claims (1)

[Claims] 1. An erasable programmable read-only memory (hereinafter referred to as EPROM), and a firmware read-only memory (hereinafter referred to as FROM, which stores instructions for controlling write / read operations for the EPROM).
In which at least the serial data to be written to the EPROM is input from the outside, converted into parallel data and output, and the parallel data read from the EPROM is serialized. A serial interface circuit for converting the data and outputting the data to the outside, a write data storage section for temporarily storing the parallel data output from the serial interface circuit as an input, and a parallel read from the EPROM A read data storage unit for inputting and temporarily storing data, a mode control unit for setting a write mode or a read mode corresponding to the EPROM via a control signal from the CPU, and a CPU Write via control signal In a mode, a write address for the EPROM is set, and in a read mode, an address setting unit for setting a read address for the EPROM, and addresses output from the address setting unit and the CPU, respectively, are received. In the normal operation mode set via the mode switching signal, the address output from the CPU is selected to specify the address of the EPROM, and in the write / read control mode set via the mode switching signal. In the above, the EPR is selected by selecting an address output from the address setting section.
In response to the commands output from the EPROM and the FROM and the address control unit designating the address of the OM, the commands output from the EPROM are transmitted in the normal operation mode set via the mode switching signal. An EPROM for selecting and supplying the instruction to the CPU and supplying the instruction to the CPU in the write / read control mode set via the mode switching signal. A microcomputer provided as an interface means corresponding to.