JPH07104723A - Display system - Google Patents

Abstract

PURPOSE:To display text data, graphics data, the image data and coexistingly display them on a flat pannel display with high picture quality by providing a display controller means enlarging or reducing the expanded image data and selectively displaying the image data and the display data. CONSTITUTION:By an animation expansion program stored in a main memory 3, the compressed image data stored in a CD-ROM 17 are read and expanded through a CD-ROM controller 15 and a system bus controller 11 to be outputted to a multi-media display controller 7. By the multi-media display controller 7, in addition to the display processing of the text data and the graphics data, the processing for superposing respective display timing for respective displays of a still picture and an animation or the coexisting display of them, and the processing of control, enlargement/reduction of a display area, and the control of the write/read of the animation data in/from a frame buffer memory 25 are performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control system, and more particularly to a multimedia display control system for storing image data in a frame buffer.

[0002]

2. Description of the Related Art Conventionally, a VGA (Video Graphics Array) has been used as a graphics controller (video subsystem) for a portable computer.
Is used. The VGA has a mechanism for controlling display display, and has a display function with a resolution of 640 × 480 pixels. In recent years, along with the development of portable computers, computers called multimedia personal computers have been developed. On this computer,
In addition to text data and graphics data, image data such as moving images and still images can be displayed on the CRT. Image data is displayed using YUV signals conventionally used in televisions, videos, etc., so that text data and graphics data are displayed using an RGB display circuit built in the computer body. Image data is displayed by connecting the option board to the computer body. As such an option board, for example,
C-Cube Microsystems CL-
450 (Registered Trademark) D
There is an development board. This board is MPEG (Moving Picture Codin)
g Experts Group) video alg
MPEG compress using orithm
The d video signal is expanded, the YUV signal is converted into an RGB signal, and the RGB signal is output. It should be noted that MPEG is an organization that is promoting the standardization of a color moving image storage encoding system, and
It is a subordinate organization of JTCI (International Committee for Standardization of Information Processing) jointly promoted by (International Organization for Standardization) and IEC (International Electrotechnical Commission). On the other hand, it may also refer to an encoding method for storing color moving images. MPEG-1 for CD-ROM applications and MPE for higher image quality
There is G-2. Each transfer rate is 1.5 Mbit /
Seconds or less and 5M-10M bits / second.

In addition, DVI (Dig of Intel Corp.
Italic Video Interactive) boards are known. On this DVI board, a 82750PB chip for compressing / decompressing an image, a VRAM for storing image data, and a 827 for controlling display of image data.
A 50DB chip or the like is mounted.

However, when such an option board is connected to the computer main body, there are two subsystems, that is, an RGB display subsystem built into the computer main body and a YUV display subsystem on the option board. Therefore, there is a drawback that the circuit configuration becomes redundant.

Further, with the development of a laptop type portable computer, even in a portable computer adopting a flat panel such as a TFT color LCD, image data such as text data, graphics data, moving image data and still image data can be displayed and displayed. It is desired to perform mixed display using a flat panel display.

In order to solve such a problem, in a portable computer adopting a flat panel display such as a TFT color LCD as a display device, another display controller has a display controller which is standardly mounted on the main body. A technique for displaying graphics data and image data on a common display circuit by substituting a part of the display function has been developed. An example of this is Japanese Patent Application No. 4-135189.

Further, in recent years, a technique has been developed in which all of the functions similar to those of a system for displaying image data such as moving images and still images in addition to text data and graphics data by using these hardware logics are realized by software. For example, Video f of Microsoft Corporation
Or Windows and Indeo of Intel Corporation of the United States are known. Of these, Indeo is a technology in which the DVI displays image data by software.
160 without dedicated hardware logic such as board
A moving image with about 120 pixels can be displayed. 82750
Although the image quality is inferior to the case of using a DVI board on which a DB chip is mounted or the case of using a PB chip disclosed in Japanese Patent Application No. 4-135189, it does not require a dedicated hardware logic. The system can be realized at a low price. In this case, image data such as a moving image or a still image is decompressed by software and sent to a graphics controller such as VGA like text data and graphics data. The graphics controller uses the expanded data as C
Display on RT or flat panel display.

[0008]

However, in this software method, since the graphics controller always performs processing for display, it takes time to fetch the decompressed data of the moving image. Also VRA
When an inexpensive DRAM is used as M, it takes more time to process, so that it is not possible to obtain a sufficient transfer speed for displaying a moving image, and as a result, the display image quality is deteriorated. was there. Generally, the image quality deteriorates in the form of a reduction in the number of frames that can be displayed per second.

The object of the present invention is to provide a TFT for a display device.
In a portable computer that adopts a flat panel such as a color LCD, it is possible to display image data such as text data, graphics data, moving image data and still image data by simply improving the display controller that is standardly installed in the main body. It is an object of the present invention to provide a display system capable of displaying a mixed display of them with high image quality on a flat panel display.

[0010]

To achieve the above object, according to the multimedia display control system of the present invention, software means for converting compressed image data into decompressed image data; Frame buffer memory means for temporarily holding the expanded image data; video memory means for storing text data and graphics data; palette means for color-converting display data output from the video memory means;
The decompressed image data and the display data output from the palette means are read from the frame buffer memory means, and the decompressed image data is enlarged or reduced to an arbitrary size to display a screen to be displayed. Display controller means for selectively displaying display data output from the palette means at an arbitrary position is provided.

According to the present invention, in a system for expanding a moving image by software, deterioration of image quality can be prevented by adding a minimum amount of hardware. Further, for the monochrome LCD, it has a frame buffer for converting the display timing of the CRT into the display timing of the monochrome LCD, but in the case of the TFT color LCD, there is no need to convert the timing, so the frame buffer Not used. Therefore, by storing the image data expanded by software in the frame buffer, the monochrome LCD frame memory and the video memory for the image data are configured by a common memory (frame buffer). Therefore, the display system can be simplified. Further, since the frame buffer for storing the image data expanded by software is composed of DRAM, an inexpensive display system can be obtained.

In such a system for expanding a moving image by software, the addition of a minimum amount of hardware has the effect of preventing the deterioration of image quality. Also the conventional 827
When using a DVI board or the like on which a 50DB chip is mounted, or the PB disclosed in Japanese Patent Application No. 4-135189.
Compared to the system that displays videos using chips,
An inexpensive display system can be provided.

[0013]

1 is a block diagram showing the entire multimedia display control system of the present invention. central
A processing unit (CPU) 1, a main memory 3, a video capture board 5, and a multimedia display controller 7 are connected to a CPU bus 9. The system bus controller 11 is connected to the CPU bus 9 and the system bus 13. System bus 1
3, a CD-ROM controller 15 is further connected, and the CD-ROM controller 15 has a CD-ROM.
17 is connected. The video decoder 19 is connected to the system bus 13, the frame buffer memory 21, and the multimedia display controller 7. Further, frame buffer memories 23 and 25, a flat panel display (FPD) 27, and a CRT 29 are connected to the multimedia display controller 7. The frame buffer memory 23 is used to store VGA display data, for example. The frame buffer memory 25 is used to store moving image data. Decompression of compressed image data such as moving images and still images
For example, Intel's Indeo (US Intel
(Registered trademark of Corporation). Inde
o is the conventional DVI (Digital Video In)
teractive) (Intel Corpor, USA)
software, which is a technology for compressing, decompressing, and displaying image data, which was performed by
1 even if there is no dedicated hardware logic such as I board
A moving image of about 60 pixels x 120 pixels can be displayed.

In FIG. 1, the moving picture expansion program stored in the main memory 3 is, for example, a CD-ROM 17
The compressed image data stored in is read via the CR-ROM controller 15 and the system bus controller 11, expanded, and output to the multimedia display controller 7 in YUV form or RGB form. The multimedia display controller 7 displays a still image, in addition to displaying text data and graphics data using the normal frame buffer memory 23.
Processing for superimposing display timings for displaying each moving picture or mixed display thereof, control of display area, enlargement / reduction processing, and writing / reading of moving picture data to / from the frame buffer memory 25 are performed. . The frame buffer memory 25 includes JPEG (Joint Photographic) in addition to moving picture data such as MPEG video data and DVI video data described later.
Still images such as Experts Group) can also be stored. Hereinafter, in the embodiment of the present invention, the image data includes moving image data and still image data. JPEG is an organization that is promoting the standardization of color still image encoding methods, and
It is a joint organization of the International Organization for Standardization and CCITT (International Telegraph and Telephone Advisory Committee). On the other hand, it may also refer to a color still image encoding method.

FIG. 2 is a diagram showing a case where the moving picture decompression program stored in the main memory 3 or the moving picture data supplied from the multimedia display control system shown in FIG. 1 is stored in the frame buffer provided in the computer main body. It is a figure which shows a concept. 2 that are the same as those in FIG. 1 are designated by the same reference numerals. In this embodiment, moving image data is stored by using the frame buffer 25 for converting the CRT display timing into the monochrome LCD timing, so that a display timing conversion buffer from the CRT to the LCD and a moving image data storage frame buffer are provided. The redundancy of having is removed, and the circuit is simplified.

In FIG. 2, a graphic subsystem built in the computer main body is a display subsystem for displaying graphic software,
For example, VGA Video Graphics Arra
y). The moving picture decompression program stored in the main memory 3 has a function of decompressing the image compression data supplied via the CPU bus 9. The compressed image data is stored in, for example, the CD-ROM 17 or the hard disk 6. Image compression data is decompressed, CP
It is output to the frame buffer 25 via the U bus 9.
For more information on frame buffer 25, see USSN 0
7 / 906,834.

The frame buffer 25 has two roles. One is that the display device is a monochrome LCD (Liquid
CRT in the case of Crystal Display)
By reading the display data written in the frame buffer at the timing of, at the timing of the monochrome LCD,
Used to display data on monochrome LCD at CRT timing. Another role is that when a TFT color LCD is used as a display device, it is not necessary to use the frame buffer 25 to convert the CRT timing to the LCD timing, so that the frame buffer 25 is used to store the image expansion data. Used as a memory to store.

The VGA memory 23 is a VRAM for storing display data in the VGA graphic subsystem. Display data is written in the VGA memory 23 by the CPU via the CPU bus 9. The display data stored in the VGA memory 23 is read out via the display read port and output to the palette 39. The palette 39 color-converts the display data and outputs it to the multiplexer 41. The multiplexer 41 selects the display data from the palette 39 and the image data from the frame buffer 25 and outputs it to the DAC 47 when the display device is a CRT, and the color LCD gradation circuit 45 when the display device is a color LCD. Output to.

It should be noted that in FIG. 2, VGA surrounded by a broken line
VGA where the part that is written as the core is conventionally known
Chips (eg, Para. USA, December 9, 1988)
dise Systems, Inc. "PVGA1A" chip shown in the PVGA1A specification issued by the company, and in the present invention, the pallet 3
9, a multiplexer 41, a monochrome LCD gradation control circuit 43, a color LCD gradation control circuit 45, and a DAC 47 are added to form a one-chip LSI.

The flow of display data when the display device is a monochrome LCD, a color LCD, or a CRT will be described below. In case of monochrome LCD, V
The display data written in the GA memory 23 is read out through the display read port and written in the frame buffer 25 through the write port of the frame buffer 25. The display data written in the frame buffer 25 is read out at the display timing of the monochrome LCD, and is passed through the monochrome LCD gradation control circuit 43 to the monochrome LC.
It is output to D.

In the case of a color LCD, VGA memory 2
The display data read from No. 3 is color-converted in the palette 39, selected by the image data stored in the frame buffer 25 and the multiplexer 41, and output to the color LCD via the color gradation control circuit 45.

In the case of a CRT, the display data output from the VGA memory 23 is color-converted via the palette 39, selected by the image data stored in the frame buffer 25 and the multiplexer 41, and converted into analog data by the DAC 47. And output to the CRT.

As shown in FIGS. 3 and 4, a window for MPEG video data can be cut off on the VGA display screen to display the VGA and MPEG video data display data in a mixed manner. There are two methods for this mixed display. The first method is as shown in FIG.
The display data of A is 24 with the display data of MPEG.
This is a method of displaying in a bit configuration. This writes VGA display data and MPEG display data to the frame buffer 25 and displays them on a color LCD or CRT. However, 16 or 256 colors are sufficient for the graphics data, and 16 bits per pixel is not necessary. On the other hand, writing speed is important,
When writing 6 bits, there is a drawback that the writing speed is slower than that of 4 bits (16 colors) or 8 bits (256 colors).

The second method is to convert VGA graphics data into 4 bits (1 bit) per pixel as shown in FIG.
This is a method of displaying only image data in a 16-bit configuration with 6-color) or 8-bit (256 colors) configuration. With this configuration, graphic data can be accessed only by 4 bits or 8 bits, and therefore high-speed processing is possible. This outputs the VGA graphics data to the multiplexer 41 via the VGA memory 23 and the palette 39, and the frame buffer 2
This is a method of outputting the image data of No. 5 to the multiplexer 41, switching control by the multiplexer 41, and outputting to the color LCD or CRT.

Although the TFT color LCD is used in the above-mentioned embodiment, the STN color LCD may be used. FIG. 5 is a detailed block diagram of writing the moving image data shown in FIG. 2 into the frame buffer 25 and controlling reading of the moving image data from the frame buffer 25. The same parts as those in FIGS. 1 and 2 are designated by the same reference numerals.

Display area and write FIFO controller 4
Reference numeral 9 controls the display area and the write FIFO 53 based on the control information from the moving picture control register 51. The enlargement / reduction and read FIFO control unit 55 controls the enlargement / reduction of the moving image data and the read FIFO 57 based on the control information from the moving image control register 51. The superposition control unit 59 uses the moving image control register 51.
Based on the control information from, the switching timing of the multiplexer 41 is controlled so that the moving image data read from the read FIFO 57 and the display data read from the RAM 39 are overlapped and mixed display is performed. R
The AMDAC control circuit 61 uses the pallet 39 for the CRT.
8-bit data (P7-
0) is converted to RGB 6-bit data. DAC47
Converts the video data or display data output from the multiplexer 41 into RGB analog signals.

In this embodiment, the expanded moving image data output from the CPU bus 9 is enlarged or reduced vertically and horizontally,
It can be displayed at any position on the screen. The moving image data is, for example, image data of 360 × 240 dots and 60 frames / s. Data width is 16 bits, 65, 53
6-color display is possible. Reduction / enlargement is 1/6 vertically and horizontally
It is performed in units of 4 and can be displayed in a range of up to 1024x512 dots.

The moving image data is written in the frame buffer 25. The video D is read according to the area to be displayed from the frame buffer (this is defined by the moving picture control register 51), and is combined with the display data from the video memory.
Input to AC.

The memory access to the frame buffer 25 is one pixel access with 16 bits. The display size of the moving image data is determined by the start X direction / start Y direction register and the size X / size Y register and is written in the frame buffer 25. By stopping the writing to the frame buffer 25, the moving image display can be stopped.

The data to be written in the frame buffer 25 is composed of 16 bits. In this case, Red data and Blue data are 5 bits, and Green data is 6 bits.
Composed of bits. FIG. 6 shows the structure of moving image data.

Frame buffer 2 for storing moving image data
5 uses 1350K bits (360x240x16 bits) of the video memory (256Kx16) 67 shown in Fig. 5. FIG. 7 shows the memory configuration of the frame buffer 25.

In order to display the moving image data in real time, the moving image data from the CPU bus 9 is written to the frame buffer 25 as it is, and 360 × 240 dots × 16 bits / bit from the frame buffer 25 within the time for displaying the screen (VGA). It is necessary to read the moving image data of the pixel. The moving image data read from the frame buffer 25 is performed in line units for the reduction processing.

Of the one-line display time (horizontal period), the time excluding the moving picture read time (360 dots × 16 bits) and the refresh time is assigned to the writing of the moving picture data.

In the moving picture data write, the moving picture data from the CPU bus 9 is written in a write FIFO (8 dots: 8 × 16).
Dots) (described later), and when the write FIFO becomes full while the moving image data is being read from the frame buffer 25, the data is written to the frame buffer 25. C
The writing is completed in the shortest time to display two screens (VGA) from the PU bus without interruption. FIG. 8 shows the timing of read / write of moving image data (30 frames / s).

In moving image data reading, data for each line is stored in a read FIFO (360 dots: 360 × 16 bits) (described later). The range of moving image data to be displayed is defined by the horizontal / vertical display start register and the horizontal / vertical display end register, and is displayed in the determined overlapping range. To reduce or expand video data,
This is performed in units of 1/64 of moving image data output from the CPU bus 9 independently in the horizontal and vertical directions. Horizontal / vertical reduction / enlargement scales are set in the horizontal and vertical scale registers. If the range to be displayed is smaller than the range of moving image data in the moving image data memory, it is reduced, and if it is large, it is enlarged.

The display range is reduced by thinning out certain display dots in the horizontal direction and certain display lines in the vertical direction with respect to the read and stored read FIFO data.
FIG. 9 shows a conceptual diagram of moving image data read in the reduction processing.

Similarly, for expanding the display range, a certain display dot is inserted in the horizontal direction and a certain display line is inserted in the vertical direction. As the data insertion method, a method of simply rescanning the immediately preceding data and a method of calculating the halftone of the preceding and following data and inserting the data are inserted. FIG. 10 shows a conceptual diagram of halftone insertion in the enlargement processing. It may be displayed like a stripe depending on the difference in data before and after, and a smooth change can be realized by inserting an intermediate gradation. The halftone insertion mode is set by setting bit 1 of the moving image mode register. Superimposition of moving image data is performed within the range determined by the combination of the window and the color key area. Which range is to be superimposed and displayed is selected by bit 5-2 of the moving image mode register. The window is defined by the horizontal / vertical region start register and the horizontal / vertical end register. The color key area indicates a case where the setting value of the color comparison register is compared with the color data (color lookup table selection) and all the bits match. FIG. 11 is a conceptual diagram showing the position of superposition. Horizontal display start /
If the range determined above does not match the display range determined by the end register and the vertical display start / end register, the superposition of that location is ignored. The start position of the moving image data is determined by the start address register value.

The moving image data can be panned in the horizontal and vertical directions. Set the column and row addresses required for panning in the horizontal panning and vertical panning registers.

For superimposing the 18-bit RGB data output from the color look-up table of the video DAC and the 16-bit moving image data read from the frame buffer, the RGB of the moving image data is converted to the RGB data MS.
Perform according to B. "0" is inserted in the least significant bit of the R data and B data of the moving image data. R in Figure 12
The conceptual diagram of superimposing GB data and moving image data is shown. 1. Video mode register D7: Video data input 0: Decoder 1: CPU D6: Video display still 0: Not still 1: Still D5-D2: Overlay range 0: VGA 1: Video data VGA screen and video data are displayed Select a range.

OVL3 color key area, window (F3) OVL2 color key area, window outside (F2) OVL1 color key area outside, window (F1) OVL0 color key area outside, window outside (F0) D1: intermediate Gradation insertion 0: Impossible 1: Acceptable D0: Display enable 0: Impossible 1: Acceptable 2. Horizontal display start register D7-D0: Horizontal display start Sets the horizontal display start. Display in the range defined by the horizontal display start / end register and vertical display start / end register. The set value must be smaller than the value of the horizontal display end register in the range of 0-1023 by the number of pixel clocks from the fall of the horizontal sync signal (LPC). 3. Horizontal display end register D7-D0: Horizontal display end Set the horizontal display end. The setting value is in the range of 0-1023 from the falling edge of the horizontal sync signal (LPC) by the number of pixel clocks. 4. Vertical display start register D7-D0: Vertical display start Set the vertical display start. The set value must be smaller than the value of the vertical display end register in the range of 0 to 511, which is the number of pixel clocks from the fall of the vertical synchronizing signal (FPC). 5. Vertical display end register D7-D0: Vertical display end Set the vertical end that can be displayed. The set value is set within the range of 0 to 511, which is the number of pixel clocks from the fall of the vertical synchronization signal (FPC). 6. Start address register (High) D7: Start X direction bit 8 D6: Size X bit 9 D5: Size X bit 8 D4: Size Y bit 8 D3: Horizontal total dot number 9 D2: Horizontal total dot number Bit 8 D1: Vertical total dot number bit 8 D0: Display start address Set the linear address (16 bits) of the video data frame buffer. 7. Start address register (Middle) D7-D0: Display start address Set the linear address of the video data frame buffer. 8. Start address register (Low) D7-D0: Display start address Set the linear address of the video data frame buffer. 9. Horizontal area start register D7-D0: Horizontal area start register Set the horizontal start of the window. Display in the range defined by the horizontal start / end register and vertical start / end register. The set value must be smaller than the value of the horizontal area end register in the range of 0-1023 by the number of pixel clocks from the fall of the horizontal synchronizing signal (LPC). 10. Horizontal area end register D7-D0: Horizontal area end Set the horizontal end of the window. The setting value is
The number of pixel clocks is set to the range of 0 to 1023 from the trailing edge of the horizontal synchronizing signal (LPC). 11. Vertical area start register D7-D0: Vertical area start register Set the vertical start of the window. The setting value is
It must be smaller than the value of the vertical area end register in the range of 0 to 511, which is the number of pixel clocks from the fall of the vertical synchronizing signal (FPC). 12. Vertical area end register D7-D0: Vertical area end Set the vertical end of the window. The setting value is
The range is 0 to 511, which is the number of pixel clocks from the fall of the vertical synchronization signal (FPC). 13. Overflow register 0 D7-D6: Not used D5: Horizontal display start bit 9 D4: Horizontal display start bit 8 D3: Horizontal display end bit 9 D2: Horizontal display end bit 8 D1: Vertical display start bit 8 D0 : Vertical display end bit 8 14. Overflow register 1 D7: Unused D6: Horizontal panning bit 8 D5: Horizontal area start bit 9 D4: Horizontal area start bit 8 D3: Horizontal area end bit 9 D2: Horizontal area end bit 8 D1: Vertical area Start bit 8 D0: Vertical area end bit 8 15. Horizontal scale register D7-D6: Horizontal zoom ratio HZ1 HZ0 Function 0 0 No zoom 0 1 2 times 1 0 4 times 1 1 8 times However, the zoomed display area is the maximum display area (1024x
If it exceeds 512), the setting becomes invalid.

D5-D0: Horizontal scale Set horizontal scale / 64 dots for reduction / enlargement for moving image data stored in the frame buffer. The set value is in the range of 1-63. When 0 is set and when 1 to 31 is set at a zoom ratio of 2, 4, or 8 times,
Do not reduce / enlarge. In the case of enlargement, the magnification is set in combination with HZ1-0. HZ1-0 HSL5-0 (D5-D0) Magnification unit X X 0 1 -0 0 X 1 -0 0 1-63 1 / 64-63 / 64 1/64 0 1 32-63 1-2 times 1/32 1 0 32-63 2-4 times 1/16 1 1 32-63 4-8 times 1/8 16. Vertical scale register D7-D6: Vertical zoom ratio VZ1 VZ0 Function 0 0 No zoom 0 1 2 times 1 0 4 times 1 1 8 times However, the zoomed display area is the maximum display area (1024x
If it exceeds 512), the setting becomes invalid.

D5-D0: Vertical scale Scale for vertical / downscale / 64 lines is set for the moving image data stored in the moving image data memory. The set value is in the range of 1-63. If 0 is set, and if 1-31 is set at a zoom magnification of 2, 4, or 8, no reduction / enlargement is performed. 17. Color comparison register D7-D0: Color comparison color data (color lookup table selection) and C
Comparison with MP7-0 (D7-D0) is performed. It is defined as a color key area when all bits are equal. 18. Color mask register D7-D0: Valid / invalid of color data 0: Valid
1: Invalid When valid, the color data value is compared with the color comparison register value. When invalid, the comparison result is the same regardless of the value of the color data. 19. Horizontal panning register D7-D0: Horizontal panning column address Set in the range of 0-359. 20. Vertical panning register D7-D0: Vertical panning column address Set in the range of 0-239. 21. General control register D7-D3: Unused (= "0") D2: Video display enable signal 0: Input 1: Output D1: Vertical sync polarity 0: Positive polarity 1: Negative polarity D0: Horizontal synchronization polarity 0: Positive polarity 1 Negative polarity FIG. 13 is a circuit diagram showing a control circuit for receiving moving image data from the CPU bus 9 and writing it in the moving image data frame buffer 25.

According to this embodiment, the speed at which moving image data is received from the CPU bus 9 based on the parameter register group indicating the size and start position of the moving image data, and is received from the CPU bus 9 by the write FIFO 53 that is temporarily held. And adjust the writing speed to the frame buffer for moving image data, and write in the frame buffer for moving image data in real time. Further, it has a reading FIFO 57 for adjusting the speed of reading from the moving image data frame buffer 25 and the display speed and enlarging or reducing the data read from the moving image data frame buffer 25.
Video data is displayed in real time even if it is scaled up or down.

In FIG. 13, a register group 71 holds moving image data from video data, and a counter 73 described later.
The count values from are stored in order. Counter 73
Selects a register that should hold moving image data from the register group 71. The counter 75 sequentially selects the values of the register group 71 by the multiplexer 77.
The frequency divider circuit 79 receives the memory clock as an input and outputs a control clock of frequency division by 2 and frequency division by 16. The multiplexer 77 selects from the register group 71 according to the output value of the counter 75. The moving picture control register 51 holds each format of moving picture data. The area control circuit 49 is the moving picture control register 5
The display area of the moving image data is controlled according to the value of 1. The memory control circuit 65 controls the address and the like of the moving picture data frame buffer 25 according to the value of the moving picture control register 51. The frame buffer memory 25 has a frame buffer function of storing moving image data.

FIG. 14 shows a frame buffer 2 for moving image data.
5 is a circuit diagram showing a control circuit for reading out data from No. 5 and performing enlargement / reduction processing. FIG. The register group 81 holds the data from the moving image data frame buffer 25 and sequentially stores the data by the counter 83. The counter 83 selects a register holding data from the register group 81. The counter 85 sequentially selects the values of the register group 81 by the multiplexer 87 in order to output them. The multiplexer 87 selects from the register group 81 according to the value of the counter 85. The enlargement / reduction circuit 55 performs enlargement / reduction processing according to the value of the moving image control register 51. The moving picture control register 51 holds each format of moving picture data. The superposition control circuit 59 superimposes the output of the multiplexer 87 and the VGA video output.

FIG. 15 is a waveform diagram showing the operation of each control circuit shown in FIGS. 13 and 14. The waveform diagram of the write FIFO, the waveform diagram of the memory write, the waveform diagram of the memory read, and the read FIFO are shown. Consists of waveform diagrams.

Now, the moving image data format is 16 bits / pixel, horizontal x vertical resolution x frequency is 360 dots x 2
A case of 40 dots × 30 Hz will be described. Register group 7
1 is composed of 16 bits × 8 latches and can hold moving image data for 8 pixels. When the moving image data from the video decoder comes in, the octal counter 73 counts up for each pixel. The clock of the counter is the memory clock divided by 16. Area control circuit 49
Determines the area to be displayed from the size of the moving image data set in the moving image control register 51 and the value of the start position,
Output the enable signal of the counter. According to this counter value, the moving image data is sequentially held in the register group 71. When all eight register groups 71 are full, the register groups 71 sequentially output the data in order to write to the frame buffer 25 for moving image data using the multiplexer 77. Therefore, the octal counter 75 is used. The clock of the counter 75 is a memory clock divided by 2, and operates at a speed eight times that of the counter 73. Writing to the frame buffer 25 is performed with two memory clocks, and the timing is generated by the memory control circuit 65. Therefore, the speed of taking out from the register group 71 and the speed of writing to the frame buffer 25 are the same, and when holding 8 pixels from the CPU bus 9 in the register group 71, moving image data for 8 pixels is stored in the frame buffer. 25 will be sent.

At this time, the moving image data can be stored in the frame buffer 25 without impairing the moving speed.
Next, the data stored in the frame buffer 25 is read in the gap for writing the moving image data in the frame buffer 25. The read control is performed by the memory control circuit 65. Writing to the frame buffer 25 is performed when the memory write in FIG. 15 is "H", and therefore can be used as the read time at other times. Figure 15 shows the read time.
The memory read of is "H". As shown in FIG. 15, while writing 56 dots of moving image data, 360 dots of moving image data are read out. The data read at this time is held in the register group 81. The register group 81 has a structure of 16 bits × 360 pieces. That is, one line is prepared for the enlargement / reduction processing. The holding in the register group 81 is sequentially performed by the 360-ary counter 83. This counter clock is a memory clock divided by two. The register group 81 is filled up by one line, and sequentially output using the multiplexer 87 for display. For this purpose, a 360-base counter 8
5 is used. The clock of the counter 85 uses the pixel clock for display. Further, in order to perform the enlargement / reduction processing, the enlargement / reduction processing circuit 55 outputs the enable signal of the counter 85. Enlargement / reduction processing circuit 55
In the case of enlargement processing based on the horizontal and vertical scale ratios set in the moving image control register 51, the counter is stopped and scanning is performed a plurality of times, and in the case of reduction processing,
Scanning is performed by skipping the counter and thinning it out. The moving image data output from the multiplexer 87 is combined with the VGA video output by the superposition control circuit 59. The combined video output becomes an input of the video DAC, is converted into analog data, and is input to an external display device such as a CRT.

FIG. 16 is a detailed block diagram of the enlargement / reduction processing circuit 55 shown in FIG. In FIG. 16, the arithmetic unit 1
Reference numeral 71 calculates the basic dot number of 64 dots in the reduction processing and the horizontal display dot number set in the horizontal scale register 173. In the horizontal scale register 173, how many dots of 64 dots are desired to be displayed is set. The initial value "1" is applied to the D input terminal of the 32-ary counter 175, and counting is performed in synchronization with the pixel clock signal shown in FIG. 17, as shown by the 32-ary counter in FIG. The 32-ary counter 175 generates a load signal for the 360-ary counter 85, which will be described later. The output of the arithmetic unit 171 is -1 by the -1 circuit 172 and supplied to the A input terminal of the comparator 171. Further, the Q output from the 32-ary counter 175 is applied to the B input terminal of the comparator 171. The comparator 177 compares the inputs of A and B, and when they match, outputs the value to the multiplexer 179. The comparator 181 has a horizontal scale value applied to the A input and a constant "
32 ". The comparator 181 determines whether the reduction ratio is 1/2 or less. This means that when the reduction ratio is 1/2 or less, less data is displayed than data to be deleted. This is to obtain the data to be displayed, which will be described later in detail.

If A> B, the comparator 181 compares the comparator 1
A selection signal is output so that the multiplexer 179 selects the output of 77, otherwise "1". The output from the multiplexer 179 is 360 as a load signal.
It is supplied to the advance counter 85 (counter 85 shown in FIG. 14). The calculator 185 divides 64 dots by the number of horizontal display dots. The calculator 187 adds the output of the 360-ary counter 85 to the calculation result from the calculator 185. The output of the calculator 187 is supplied to the D input terminal of the 360-ary counter 85. The 360-base counter 85 is 36 in FIG.
Counting is performed as indicated by the 0-ary counter R, and the selection condition of the multiplexer 87 (FIG. 14) is output. Calculator 1
A comparator 89 calculates (A * B-1) the output (A input) from the -1 circuit 172 and the zoom magnification (B input).
Supply to 91. The comparator 191 compares the Q output from the cow 175 with the output from the calculator 189, and if they match, the zoom signal shown in FIG.
Output to 3. The enlargement control circuit 193 performs enlargement control in response to the zoom signal, and supplies the enable signal shown in FIG. 17 to the counter 85.

FIG. 18 is a detailed circuit diagram of the expansion control circuit shown in FIG. In FIG. 18, the pixel clock is set to 2
The frequency divided by 4, the frequency divided by 4, and the frequency divided by 8 are supplied to AND gates 195, 197, and 199, respectively. Furthermore, the 7-bit value of the horizontal scale register is AND gates 195, 1
97,199. In this embodiment, when the bits 6 and 7 are "01", they are 1-2 times, and when they are "10", they are 2-4.
If it is "11", it will be 4-8 times, and bit 0
From 6 bits of bit 5 to the value of 32-63 (1-2
1/64 unit is defined for double, 1/16 unit for 2-4 times, and 1/8 unit for 4-8 times). Each A
The outputs of the ND gates 195, 197, and 199 are ORed by the OR gate 201 to generate the expansion enable signal. The OR gate 203 takes the OR of the enlargement enable signal and the zoom signal to generate the ENABLE signal.

Conventionally, when displaying moving image data or still image data in a region in which the horizontal and vertical directions are reduced, certain dots are thinned out in the horizontal direction according to the scale value in the horizontal direction and vertical in the vertical direction. A line is thinned according to the scale value. As a method of thinning out,
The number of dots in the horizontal direction was divided by the value obtained by thinning the number of dots to be displayed from the number of dots in the horizontal direction, and it was standard to perform every -1 value. (Refer to FIG. 19) However, the above method is effective when the reduction ratio is 1 to 1/2, but when the reduction ratio is reduced to 1/2 or less, the number of thinning-outs becomes continuous. There is a problem that another means for controlling is required, the number of circuits is increased, and if the number of consecutive times is not properly controlled, a specific dot is lost and display quality is deteriorated.

In this embodiment, a display controller for reducing and displaying data from the frame buffer at an arbitrary screen position has a reducing means which is divided according to the reduction ratio, and a linear thinning method is used to display quality. A good display controller can be obtained.

In this embodiment, it is necessary to omit certain dots in order to obtain the data to be displayed by being reduced from the original horizontal display data. The dropout ratio is calculated from the output of the parameter register that stores the number of horizontal display dots (horizontal scale), and when the count value matches the count value, the dropout is performed to periodically drop. Output an enable signal to drop it,
This becomes the load enable of the line counter for determining the memory data selection condition. The memory data is held by a plurality of latches, a dot to be displayed (not missing) is selected by a multiplexer for the number of lines, and is sent to a video output circuit. In the circuit which determines the ratio of the dots to be dropped and generates the load enable signal of the line counter, the reduction ratio is divided into cases to indicate the optimal drop ratio, and the display dots are always shown at equal intervals.

In FIG. 20, the moving picture control register 51 sets the number of display dots in the horizontal direction (horizontal scale value). The arithmetic unit 91 executes (A ÷ (A−B)) − 1.
The arithmetic unit 93 executes A ÷ B. The arithmetic unit 95 executes A + B. The comparator 99 is effective when A = B.
(The comparator 99 outputs a logic "1" when A = B, and otherwise outputs a logic "0"). The comparator 101 is effective when A> B. (When A> B, the comparator 101 outputs logic “1”, otherwise, outputs logic “0”) Counter 10
7 generates a load signal for the counter 109. The multiplexer 105 selects the output of the comparator 99 when the output of the comparator 101 is "0", and selects the constant "1" when it is "1". The counter 103 is set with a constant "1" in response to the load signal LD, and counts in synchronization with the pixel clock signal. The counter 107 is the multiplexer 1
The selection condition of 09 is output. The register 111 holds memory data. The multiplexer 109 is the register 11
Select a value of 1.

Next, the operation of the above configuration will be described. A case where the size of the data stored in the frame buffer is 360 dots in the horizontal direction and the reduction rates are 1/4 and 3/4 will be described. The reduction processing in the horizontal direction is performed in units of 64 dots. Therefore, when the reduction ratio is 1/4, the scale value indicating the number of dots to be displayed in the horizontal direction is set to 16 dots. If the reduction ratio is 1/2 or less, the amount of data to be displayed is smaller than the amount of data to be omitted, so the data to be displayed is obtained.

First, the number of display dots in the horizontal direction (= 16) is output from the moving picture control register 51, and the arithmetic unit 93 outputs 64 ÷
16 = 4 is output. In addition, A =
16 and B = 32 are compared, and the multiplexer 105 selects "1" from this result. Therefore, counter 1
07 is always in the load enable state, and the adder 95 loads the output value of itself plus the output value "4" of the computing unit 93. As a result, the output values of the counter 107 are 0, 4, 8, 12 ,. ． ． It becomes 60, and 0, 4, 8, 1 of the memory data latched by the register 111
2 ,. ． ． The 60th data is sequentially selected by the multiplexer 109 and sent to the video output circuit.

When the reduction ratio is 3/4, the number of dots in the horizontal direction (= 48) is output from the moving image control register 51, and the arithmetic unit 91 calculates 64 ÷ (64−48) −1 = 3, and The arithmetic unit 93 calculates 64 ÷ 48 = 1. The output value of the counter 103 and the output value of the arithmetic unit 91 (=
3) is compared by the comparator 99, and if they match, an enable signal is generated. The comparator 101 compares A = 48 and B = 32, and the multiplexer 105 selects the output of the comparator 99. Multiplexer 105
Periodically outputs 0, 0, 1, 0, 0, 1 and the adder 9
A value obtained by adding "1" indicated by the calculator 93 to the output value of itself is loaded by 5. As a result, the output values of the counter 107 are 0, 1, 2, 4, 5, 6, 8 ,. ． ． 62, which is memory data 0, 1, 2, 4, 5, 6, 8 ,. ． ． The 62nd data is sequentially selected by the multiplexer 11 and sent to the video output circuit.

[0059]

As described above, according to the present invention, in a system for expanding a moving image by software, there is an effect of preventing deterioration of image quality by adding a minimum amount of hardware. In addition, when a DVI board or the like on which a conventional 82750DB chip is mounted is used, or when a Japanese Patent Application No. Hei 4-1351 is used.
An inexpensive display system can be provided as compared with the system for displaying a moving image using the PB chip or the like disclosed in 89.

[Brief description of drawings]

FIG. 1 is a block diagram showing an entire multimedia display control system of the present invention;

2 is a block diagram showing a first embodiment of the multimedia display control system shown in FIG. 1;

FIG. 3 is a conceptual diagram showing mixed display of 4-bit or 8-bit VGA graphic data and 24-bit MPEG moving image data in the embodiment shown in FIG. 2;

4 is a 16-bit VG in the embodiment shown in FIG.
A conceptual diagram showing mixed display of A graphic data and 16-bit MPEG moving image data;

5 is a detailed block diagram of writing control of moving image data shown in FIG. 2 into a frame buffer and reading control of moving image data from the frame buffer;

FIG. 6 is a diagram showing a bit configuration of moving image data;

FIG. 7 is a diagram showing a memory configuration of a frame buffer;

FIG. 8 is a waveform diagram showing the read / write timing of moving image data;

FIG. 9 is a conceptual diagram of moving image data read in reduction processing;

FIG. 10 is a conceptual diagram of halftone insertion in enlargement processing;

FIG. 11 is a conceptual diagram showing the position of superimposition of moving image data and display data;

FIG. 12 is a conceptual diagram of superimposing moving image data and display data;

FIG. 13 is a circuit diagram showing a control circuit for receiving moving image data from a CPU bus and writing it in a moving image data frame buffer;

FIG. 14 is a circuit diagram showing a control circuit for reading data from a moving image data frame buffer and performing enlargement / reduction processing;

FIG. 15 is a waveform chart showing the operation of each control circuit shown in FIGS. 13 and 14, and is a waveform chart of a write FIFO, a waveform chart at a memory write, a waveform chart at a memory read, and a waveform of a read FIFO. Show figure;

16 is a detailed block diagram of the enlargement / reduction processing circuit shown in FIG. 14;

FIG. 17 is a waveform diagram of signals appearing in FIGS. 16 and 18;

FIG. 18 is a block diagram for horizontal enlargement control;

FIG. 19 is a waveform chart showing an example of thinning in the case of a reduction ratio of 3/4 (horizontal dot number 64, display dot number 48).

FIG. 20 is a circuit diagram showing horizontal reduction processing.

[Explanation of symbols]

1 ... CPU, 3 ... Main memory, 9 ... CPU bus, 17
... CD-ROM, 13 ... System bus, 7 ... Multimedia display controller, 23 ... VGA memory, 25 ... Frame buffer memory, 39 ... Palette,
41 ... Multiplexer, 43 ... Monochrome LCD gradation control circuit, 45 ... Color LCD gradation control circuit, 47 ... DA
C, 49 ... Display area light FIFO control circuit, 51 ...
Moving image control register, 55 ... Enlargement / reduction processing circuit, 65 ... Memory control circuit, 57 ... Read FIFO, 55 ... Enlargement / reduction read FIFO control circuit, 67 ... Video memory, 59
... Superposition control circuit, 71, 81 ... Register group, 7
3, 75, 83, 85 ... Counter, 79 ... Divider circuit, 1
73 ... Horizontal scale register, 171, 185, 18
7, 189 ... Arithmetic unit, 177, 181, 191, ... Comparator, 193 ... Enlargement control circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06T 1/00 G09G 5/00 510 M 9471-5G 5/36 520 E 9471-5G 530 A 9471- 5G

Claims (4)

[Claims] 1. Software means for converting compressed image data into decompressed image data; frame buffer memory means for temporarily holding said decompressed image data; text data and graphics data stored therein. Video memory means for performing; color palette conversion of display data output from the video memory means;
The decompressed image data and the display data output from the palette means are read from the frame buffer memory means, and the decompressed image data is enlarged or reduced to an arbitrary size to display a screen to be displayed. A multimedia display control system comprising: display controller means for selectively displaying display data output from the palette means at an arbitrary position. 2. Software means for converting compressed image data into expanded image data; used for converting display timing for a CRT display device into display timing for the flat panel display; A flat panel display, comprising: display controller means for reading the decompressed image data, enlarging or reducing it to an arbitrary size, and displaying it at an arbitrary position on a screen to be displayed. Display control system for portable computers. 3. A software means for converting compressed image data into decompressed image data; frame buffer using a single-port memory used for temporarily holding the decompressed image data. Memory means; and display controller means for reading the decompressed image data from the frame buffer memory means, enlarging or reducing it to an arbitrary size, and displaying it at an arbitrary position to be displayed. And a display control system in a portable computer having a flat panel display. 4. CD-ROM means for holding compressed image data and reading the data as necessary; image data decompressed from the CD-ROM means and expanded. Software means for converting the decompressed image data to a frame buffer memory means used for temporarily holding the decompressed image data; reading the decompressed image data from the frame buffer memory means to an arbitrary size; A multimedia display device having a fret panel display, comprising: a display controller unit for enlarging or reducing the size to display at an arbitrary position on a screen to be displayed.