JPH07103993A - Pulse width measurement device and rotational speed measurement device - Google Patents

Abstract

PURPOSE:To provide a pulse width measurement device capable of accurately measuring a cycle of a pulse signal having a small width even when a measuring clock has a small frequency in the pulse width measurement device wherein an inputted pulse signal is detected so that start and stop of the counting opera tion of the measuring clock are determined. CONSTITUTION:The device comprises a dividing means 12 that counts an inputted basic clock and generates a measuring clock for every prescribed number of pulses of the clock and a dividing-control device 13 that controls the dividing means 12 in accordance with the discrimination of single measurement and continuous measurement of a cycle of a pulse signal so that the counting operation in the dividing means is reset at every start of the counting in the single measurement but the counting operation is not reset at least during the continuation of the continuous measurement.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width measuring device for detecting an input pulse signal, determining the start and end of counting of a measuring clock, and measuring the period of the pulse signal.

[0002]

2. Description of the Related Art An input pulse signal (including an AC signal) is detected to determine the start and end of counting of a clock for measurement, and the cycle of the input pulse signal (half cycle, time related to cycle) is determined. A pulse width measuring device for measuring has been put into practical use. The pulse width measuring device is applied to, for example, a vehicle wheel speed measuring device.

The wheel speed measuring device is an ABS (Anti-Lock Br
eaking System) occupies an important component of the device,
The vehicle speed sensor inputs an AC signal formed for each rotation angle of a wheel unit, measures the cycle of the AC signal, and converts the AC signal into wheel speeds.

FIG. 4 is an explanatory diagram of the ABS device. Figure 4
In the figure, (a) shows the configuration and (b) shows the operation. Here, an arithmetic unit for controlling a vehicle (hereinafter referred to as ECU: Electronic
As an interrupt program in the Control Unit)
An ABS device is configured.

Referring to FIG. 4, an ECU mounted on an automobile
Reference numeral 45 is configured as a program-controlled microcomputer circuit, and includes a CPU, a memory, an A / D converter,
Built-in D / A converter, power supply circuit, etc. ECU 45
Assigns computing power in a time-division manner, and executes various computing processes such as engine control, constant speed running, and suspension control. However, when the brake is strongly operated by the driver, the ABS control program is activated and interrupt processing is performed.

The vehicle speed sensor 43 connected to the wheel 41 is
Detects the magnetic flux of each tooth of the permanent magnet formed in the gear type,
An AC signal whose polarity is inverted is formed for each unit rotation angle of the wheel 41. The ECU 45 obtains the cycle of this AC signal and converts it into a wheel speed.

The wheel speed calculator 47 of the ECU 45 rectifies the input AC signal, performs waveform processing, and converts it into a square wave pulse signal. The wheel speed calculator 47 outputs the number of measurement clocks integrated in one cycle of the pulse signal as the cycle of the pulse signal.

The calculation unit 49 of the ECU 45 periodically takes in the cycle of the AC signal measured by the wheel speed calculation unit 47,
The braking control signal is generated every moment as compared with a predetermined braking condition 48. The output unit 46 operates the actuator 44 based on the brake control signal every moment. Through such a series of processes, the hydraulic pressure applied to the brake 42 is increased or decreased, and the wheel speed is gradually attenuated.

In FIG. 4 (b), the vehicle speed v ₀ is the wheel speed V _0.
When the brake is strongly depressed from the constant-speed running state corresponding to, the wheel speed V is decelerated prior to the vehicle speed v, and slip occurs between the wheel contact surface and the road surface. Then, time t ₁
When the wheel speed V _C corresponding to the slip ratio of 10% is reached at time t ₂ after the brake has been strongly depressed by the ABS control, the ABS control is automatically started, and the ABS control is continued as long as the brake is continuously depressed.

In the ABS control, an instantaneous vehicle speed v is calculated from the instantaneous wheel speeds obtained for the four wheels. And
Target wheel speed V that provides a slip ratio of 10% with respect to vehicle speed v
Calculate ₁ Then, the momentary effect of the brake is adjusted, and the wheel speed V is gradually approached while vibrating with respect to the target wheel speed V ₁ .

By the way, the ECU 45 shown in FIG. 4 (a) processes a plurality of arithmetic operations in a time-division manner as described above. In recent years, the number of types of calculations to be processed by the ECU 45 has been increasing and becoming more complicated with the increase in multifunctionality of vehicles, automatic driving, automatic control of equipment, and the like.

Therefore, the old CPU in the ECU 45
It has been attempted to replace the above with a new type CPU with a high number of bits and high speed calculation to enhance the calculation capacity per hour in the ECU 45. However, in this case, the basic clock frequency used by the ECU 45 increases. Therefore, in order to prevent an increase in the number of processing bits required to measure the same time, it is necessary to adjust the measurement clock in the timer, counter, etc. of the ECU 45.

For example, as the CPU of the ECU 45 increases in speed, the basic clock frequency changes from 0.5 msec to 62.5 ns.
When the speed is increased to ec (0.0625 msec), the time that can be measured using the same 8-bit counter is reduced from 0.13 seconds to 0.016 seconds. And the same 0.
To measure 13 seconds, it is necessary to use an 11-bit counter instead of an 8-bit counter.

Therefore, the wheel speed calculator 47 of the ECU 45 shown in FIG. 4 (a) divides the basic clock to form a low-frequency measurement clock, and determines the cycle of the AC signal output from the vehicle speed sensor 43. We decided to count and measure this measurement clock.

[0015]

The ECU 45 shown in FIG. 4 (a)
When the cycle of the AC signal is measured by the wheel speed calculation unit 47 using the low-frequency measuring clock formed from the basic clock, there is a problem that the wheel speed measurement error increases at high speeds.

When the wheel speed is high, the cycle of the AC signal becomes short, and the number of measurement clocks counted in one cycle of the AC signal decreases. Then, the length of the measurement clock that is truncated without being involved in counting at the end of one cycle cannot be ignored.

That is, in single-shot measurement in which one cycle (half cycle) of the AC signal is measured only once, the error increases as the cycle becomes shorter. For example, in the range where the vehicle speed exceeds 100 km / h, the accurate wheel speed is obtained. Becomes impossible to measure. Although the ABS device should operate accurately at such a high speed, the operation of the ABS device becomes unstable due to the error in the wheel speed.

Further, in the ECU 45 shown in FIG. 4 (a), the calculation unit 49 causes the wheel speed calculation unit 4 to operate at regular intervals (for example, 5 msec).
Take the count value from 7. Then, the wheel speed calculation unit 47
Effectively uses this fixed time to improve the accuracy of cycle measurement. That is, the measurement clocks are counted for all half cycles of the AC signal input within this fixed time, and the cycle of the AC signal is obtained as the average value of the count values of each cycle. This eliminates the influence of variations in each cycle in the AC signal output from the vehicle speed sensor 43.

However, in this case, since the formation of the measurement clock is reset for the entire half cycle of the input AC signal, the above-mentioned error caused by the resolution of the measurement clock is not measured in a single shot. There is no difference from the case. Therefore, at high speeds, the measurement error of the wheel speed increases significantly.

For example, when the measurement clock is formed in a cycle of eight basic clocks by inverting the output every time four basic clocks are counted, the borrow signal for every eight basic clocks is the edge of the measurement clock. Is counted as
Then, in the measurement of the first half cycle of the AC signal,
At the maximum, the time corresponding to seven basic clocks may be truncated to cause a measurement error.

The time corresponding to the seven basic clocks can be ignored when the cycle of the AC signal is long, but cannot be ignored when the wheel speed exceeds 100 km / h and the cycle of the AC signal becomes short. . Then, the error of the wheel speed calculated from the count value of the measurement clock is increased, the brake operation processing is erroneously performed, the ABS device is erroneously operated, and the wheel 41
Lock or extend the braking distance.

An object of the present invention is to provide a pulse width measuring device capable of accurately measuring the cycle of a short pulse signal even with a low frequency measuring clock.

[0023]

FIG. 1 is an explanatory diagram of the basic configuration of the present invention. In FIG. 1, the pulse width measuring device according to claim 1 detects an input pulse signal, determines start and end of counting of a measurement clock, and determines a period of the pulse signal as a measurement number of the measurement clock. In the pulse width measuring device having the measuring means 11 for outputting as
The frequency dividing means 12 that counts the input basic clock and forms the measuring clock for each predetermined number thereof, and the frequency dividing means 12 according to the distinction between single-shot measurement and continuous measurement of the period of the pulse signal. (1) In the single-shot measurement, the counting operation in the frequency dividing means 12 is reset each time the counting is started, but (2) in the continuous measurement, at least the continuous counting operation in the frequency dividing means 12 is performed. The frequency dividing control means 13 that does not reset while the measurement is continued is provided.

According to a second aspect of the present invention, there is provided a rotation speed measuring device which forms a sensor signal (sine wave, rectangular wave, etc.) of one cycle which is inverted for each rotation angle of a rotating body, and a cycle of the sensor signal. In the rotational speed measuring device, the operating speed is measured and the rotational speed is calculated every moment. The arithmetic means counts the input basic clock and forms a measuring clock for each predetermined number of the basic clocks. Frequency dividing means, the input clock signal is detected to determine the start and end of counting of the measuring clock, and the measuring clock continuously generated by the frequency dividing means within a predetermined measuring period. A rotation speed based on an average value of a plurality of count values of the measurement clock in the measurement period and a measuring unit that outputs the count value of each of the plurality of continuous periods in the measurement period. And conversion means for, and has a.

[0025]

In FIG. 1, in the pulse width measuring device according to the first aspect, the continuous cycle (half cycle, etc.) of the input pulse signal.
When measuring, the frequency dividing means 1 for each cycle (half cycle, etc.)
2 is not reset, and counting is performed every cycle (half cycle, etc.) using the measurement clock that is continuously generated without interruption. That is, in the continuous measurement mode, the measuring unit 11 is reset but the frequency dividing unit 12 is not reset every cycle (half cycle, etc.).

Therefore, the basic clock that is discarded without being involved in counting in one cycle (half cycle etc.) reduces the time until the first counting in the next cycle (half cycle etc.), The count value in the next cycle (half cycle, etc.) is incremented by 1, and the error is canceled out as a result.

In this way, when measuring all cycles (half cycle, etc.) within a certain period of time, a measurement error in which the pulse signal is shortened and increases increases in the cycle (half cycle, etc.) continuously measured. Can be offset by a number. This is because the surplus time of the measurement clock is effectively used as the number of continuously measured cycles (half cycle, etc.) increases. As a result, as the number of measured cycles increases, the resolution of the measurement clock increases and accurate measurement can be performed even in a short cycle.

The average value does not have to be a count value for one cycle, but may be calculated as a count value corresponding to, for example, half cycles, 2.3 cycles, 7 cycles or the like.

On the other hand, in the single-shot measurement mode in which only one cycle (half cycle, etc.) is measured, the frequency dividing means 12 is reset every time the measuring means 11 is reset. As a result, the phases of the measurement clocks in each measurement are matched.

In the wheel speed measuring device of claim 2, for example,
The calculation unit 49 shown in FIG. 4 (a) fetches a plurality of count values stored in the wheel speed calculation unit 47 at regular intervals. The plurality of count values are obtained by counting the measurement clocks for all the cycles (half cycle, etc.) in this fixed time.

During this fixed time, the measuring clock is continuously generated without interruption (reset). Therefore, the error of the measurement clock is canceled for a plurality of cycles (half cycle, etc.) measured continuously, and the cycle (half cycle, etc.) as an average value is accurately obtained.

That is, when the wheel speed is low, one cycle of the AC signal is long, so that the measuring clock itself exhibits sufficient resolution. On the other hand, when the wheel speed increases, the resolution of the measurement clock itself becomes insufficient, but the number of cycles within a fixed time increases, so the remainder of the basic clock after the last counted measurement clock is It is used serially in cycles to substantially improve the resolution of the measurement clock.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is an explanatory view of a wheel speed computing device of the embodiment, and FIG. 3 is an explanatory view of pulse width measurement. In FIG. 2, (a) shows the configuration and (b) shows the operation. Here, in the ABS device of FIG. 4, the basic clock of the CPU is increased in frequency so that the ECU
The wheel speed calculation device adopted when the processing capacity of the above is increased will be described.

In FIG. 2A, the frequency divider circuit 22 is an EC
Divide the high frequency basic clock used in U,
Form a low frequency measurement clock. Frequency divider 22
Counts the basic clock and inverts the output every time a fixed number is reached to generate a measurement clock. When the clock reset signal is input from the control circuit 23, the frequency dividing circuit 22 returns the count value of the basic clock to 0 without inverting the output, and starts counting the basic clock again from the beginning.

The control circuit 23 resets the count of the measurement clock in the counter 21 each time the edge of the measurement signal is detected. When the reset signal is input from the control circuit 23, the counter 21 resets the count value to 0 and restarts counting the measurement clock from the beginning. At the same time,
The previous counting result is saved in the memory 24.

The memory 24 sends a plurality of count values continuously measured during this fixed time (5 msec) to the arithmetic unit 49 of FIG. 4A at fixed time intervals (5 msec).
The calculation unit 49 recalculates the brake control signal every fixed time (5 msec) and rewrites the output state.

In the wheel speed computing device of the embodiment, the continuous measurement mode is set, and the counter reset signal is not input to the frequency dividing circuit 22. That is, the 1-level length and the 0-level length of the square wave pulse of the measurement signal are continuously measured as the count value of the measurement clock, but at that time, the frequency dividing circuit 22 is not reset even once.

Therefore, the count value of the basic clock that does not reach the borrow signal in one half cycle measurement shortens the time until the first borrow signal in the next half cycle.

As a result, when the average value of a plurality of half cycles continuously measured within a fixed time is taken,
The counting error of the measurement signal due to the large period of the measurement clock is completely offset. That is, the increase in the number of samples taken within a fixed time offsets the increase in the error of each sample value.

Therefore, when the cycle of the measurement clock almost coincides with the cycle of the measurement signal corresponding to the wheel speed of several 100 km / h, the accurate cycle cannot be measured by single-shot measurement, The measurement error of the wheel speed obtained from the average value of the sample is not much different from the case of the wheel speed of several tens km / h.

In FIG. 2B, frequency division processing A shows a case where the frequency division circuit 22 is reset each time the edge of the measurement signal is detected. At this time, the half cycle is the basic clock 15
The half cycle of the measurement signal corresponding to the number of pieces is erroneously determined as 12 basic clocks.

That is, since the measurement clocks (borrow signals) for every four basic clocks are counted, the last three basic clocks are discarded in each half cycle, increasing the error.

On the other hand, in the frequency dividing processes B and C, the measurement clock (borrow signal) continues to be generated for every four basic clocks regardless of the edges of the measurement signal, and the counting error in one half cycle occurs. It is completely offset in the following half cycles. The frequency dividing processes B and C show that the phase of the measurement clock happens to be slightly deviated when the first half cycle is entered.

For example, the output of the vehicle speed sensor shown in FIG.
When the measurement clock is formed by dividing the basic clock by 400 Hz at 700 km at 00 km / h, the basic clock of the ECU 45 at 125 nsec, and the basic clock is divided by 4, the cycle becomes 7 pulses at 200 km / h.

At this time, if the frequency dividing process A is adopted and the frequency dividing circuit is reset for each measurement, in the worst case,
An error of (4-1) × 125 nsec × 6 = 2250 nsec occurs. This is the case of the periodic calculation between the same-polarity edges (every cycle), but in the case of the periodic calculation between the edges (every half cycle), (4-1) × 62.5 nsec × 13 = 48
An error of 75 nsec will occur.

This error is 0.22 when converted to wheel speed.
This corresponds to a measurement error of 1 km / h, which is converted to a fluctuation of G (acceleration) of 1.27 G. Since the G value of the control reference of the ABS device is 1.5 G, there is almost no margin and there is a risk of malfunction.

That is, at the vibrating wheel speed V in FIG. 2B, the timing at which the brake hydraulic pressure is reduced is G
It is selected at the timing when the absolute value of (deceleration acceleration) exceeds 1.5 G and the difference between the vehicle speed v and the wheel speed V reaches 10 to 15% of the vehicle speed v. Therefore, when the error reaches 1.27G, from 0.23G to 2.77G is 1.5G.
In the former case, the braking distance is increased, and in the latter case, the wheels are locked.

However, in actuality, as a result of the wheel speed being evaluated unreasonably lower than the actual value, when the slip ratio of 10 to 15% is reached, it has already reached 1.5 G in many cases.
The 1.5G cap is meaningless.

On the other hand, in the frequency dividing processes B and C, the error is canceled by a plurality of consecutive counts, so that the measurement error of the wheel speed is at a negligible level.

3, in the wheel speed measuring device of the embodiment, the wheel speed measurement error is compressed by effectively utilizing the interval of 5 msec at which a plurality of count values are read from the memory 24 of FIG. That is, the measurement clock is counted for each of a plurality of continuous half cycles included in 5 msec, and the measurement is performed by using the measurement clock that is continuously formed without being reset.

For example, at 200 km / h, one cycle is 0.7 msec, 7 pulses are counted, and 1 pulse is counted.
At 00 km / h, one cycle is 1.4 msec and 3.5
Counts are made for the pulses. In this way, the relative error of the wheel speed measurement is kept substantially constant over a wide range from high speed to medium speed to constant speed. The wheel speed V is calculated as V = KN / T, where K is a constant, T is the period, and N is the number of pulses.

[0052]

According to the pulse width measuring device of the first aspect,
While the pulse width measurement can be performed in the single-shot measurement mode as usual, the pulse width measurement with less measurement error can be performed in the continuous measurement mode.

According to the continuous measurement mode, the measurement error caused by the lack of the resolution of the measurement clock is almost completely canceled out for a plurality of continuous pulse signals (cycle, half cycle, etc.) included within a fixed time. To be done. Therefore, the pulse width can be measured with a substantially constant error regardless of the length of the cycle.

Further, even when the measuring clock of low frequency is used, the pulse width can be measured with high accuracy.
It is also possible to further reduce the frequency of the measurement clock and save the number of bits of the counter and timer. As a result, the CPU, communication interface, etc. are simplified and the processing speed is increased.

According to the wheel speed measuring device of the second aspect, the measurement error of the wheel speed can be kept substantially constant and low regardless of the level of the wheel speed from high speed to low speed.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a wheel speed calculation device according to an embodiment.

FIG. 3 is an explanatory diagram of pulse width measurement.

FIG. 4 is an explanatory diagram of an ABS device.

[Explanation of symbols]

 11 measuring means 12 frequency dividing means 13 frequency dividing control means

Claims (2)

[Claims] 1. A measuring means (11) for detecting the input pulse signal, determining the start and end of counting of the measuring clock, and outputting the cycle of the pulse signal as the number of measurements of the measuring clock. In a pulse width measuring device having: a frequency dividing means (12) for counting the input basic clocks and forming the measuring clocks for every predetermined number thereof; a single-shot measurement and a continuous measurement of the period of the pulse signal. The frequency dividing means (12) is controlled according to the distinction, (1) in the single-shot measurement, the counting operation in the frequency dividing means (12) is reset each time the counting is started, but (2) the continuous measurement Then, the pulse width measuring device is provided with a frequency dividing control means (13) that does not reset the counting operation in the frequency dividing means (12) at least while the continuous measurement is continued. 2. A rotation speed sensor that forms a sensor signal of one cycle for each rotation angle of a rotating body, and a calculation unit that measures the cycle of the sensor signal and calculates the rotation speed every moment. In the rotation speed measuring device, the arithmetic means counts the input basic clock and forms a measuring clock for each predetermined number of the frequency dividing means, and the sensor signal input to detect the measuring clock. The start and end of clock counting are determined, and the count value of the measurement clock continuously generated by the frequency dividing means within a predetermined measurement period is output for each of the plurality of consecutive periods in the measurement period. And a conversion unit that calculates a rotation speed based on an average value of a plurality of count values of the measurement clock in the measurement period. .