JPH07101939B2 - Band compression / decoding device - Google Patents

Description

The present invention relates to a band compression decoding device for decoding a band compression encoded moving picture television signal.

[Conventional technology]

If you want to compress and transmit the television signal,
An encoding method is often used in which the generation rate of encoded information is not constant and changes with time according to the property of the input signal.

The transmitting side and the receiving side of a digital transmission device using such an encoding system are provided with buffer memories, respectively, and speeds are respectively provided between the compression encoding side and the transmission line side and between the transmission line side and the compression decoding side. Convert. In this case, in the reception buffer memory, it is necessary to perform speed conversion without missing or duplicating encoded data. If the encoded data is lost or duplicated, a compression decoding error occurs, and the error continues until the error is refreshed by some method.

For this reason, conventionally, the delay time in the transmission buffer memory is set on the assumption that the encoding frequency and the decoding frequency of the image signal are locked so that the encoded data may not be lost or duplicated in the reception buffer memory. The measured value is transmitted to the receiving unit, and the receiving unit controls the reading of the receiving buffer memory so that the sum of the propagation delay times in the transmitting and receiving buffer memories becomes constant. (For example, Japanese Patent Laid-Open No. 58-59641) Therefore, naturally, since the propagation delay time in the transmission buffer memory must be smaller than the sum of the delay times in the transmission and reception buffer memories, there is a delay time in the transmission buffer memory. It is held down to value.

[Problems to be solved by the invention]

The conventional buffer memory control method described above is
It is established on the assumption that the encoding frequency and the decoding frequency of the image signal are locked, and when this assumption is not established, for example, when the decoding frequency is lower than the encoding frequency, There has been a problem that encoded data is accumulated in the receiving buffer memory more and more, the propagation delay time in the transmitting and receiving buffer memory cannot be made constant, and a decoding error occurs.

[Means for solving problems]

A compression / decoding device of the present invention includes a frame detection circuit that receives compression encoded data to which frame synchronization is added for each image signal frame and detects the frame synchronization of the compression encoded data, and a frame detection circuit that detects the frame synchronization. A multiplexing circuit that generates a frame number indicating the time series of the image frame for each image frame and multiplexes the frame number at the head of the compression encoded data, and compression encoding data that multiplexes the frame number is stored. A first buffer memory, a compression decoding circuit for reading the compression coded data stored in the first buffer memory and decoding the compression coded data at a faster speed than the compression coding, and the compression coded data read from the first buffer memory. A separation circuit that detects frame synchronization from the frame and separates the frame number, and the frame number that is separated by this separation circuit. A control circuit that compares the frame number generated in the multiplexing circuit and, when they are equal, suppresses the reading of the first buffer memory in units of one frame decoding time and stops the decoding operation of the compression decoding circuit; A second buffer memory for writing the decoded signal of the compression / decoding circuit and reading it in frame units at a predetermined frequency is provided.

[Action]

In the present invention, the compression / decoding frequency is set higher than the compression / encoding frequency, and the decoded signal of the compression / decoding circuit is written and converted into a regular frequency by a buffer memory which reads out in frame units at a predetermined frequency.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, reference numeral 51 denotes a frame detection circuit for receiving compression encoded data to which frame synchronization is added for each frame of an image signal and detecting frame synchronization of the compression encoded data, 52
Is a multiplexing circuit that generates a frame number indicating the time series of the image frame for each image frame detected by the frame detection circuit 51 and multiplexes the frame number at the beginning of the compression encoded data, and 53 is the above frame number. A buffer memory for storing the multiplexed compressed coded data, 54 is a separation circuit for detecting frame synchronization from the compressed coded data read from the buffer memory 53 and separating the frame numbers, 55
Is a compression / decoding circuit for reading the compression-encoded data stored in the buffer memory 53 and decoding by a predetermined method at a speed faster than the compression-encoding, and 56 is a frame number separated by the separation circuit 54 and is multiplexed. A control circuit for suppressing the reading operation of the buffer memory 53 and stopping the decoding operation of the compression decoding circuit 55 in 1 frame decoding time unit when comparing with the frame number generated in the circuit 52 and when they are equal, 57
Is a suppressor circuit, 58 is a buffer memory for writing the decoded signal of the compression / decoding circuit 55 and reading it in frame units at a predetermined frequency, and 59 is a clock generation circuit.

FIG. 2 is a time chart used to explain the operation of FIG.
(A) shows the coded frame number a,
(B) is the received compressed coded data b, (c) is the compressed and decoded data c, (d) is the decoded frame pulse d, (e).
Is the inhibit signal e, (f) is the output frame pulse f,
(G) is a write signal g, (h) is a read signal h,
(I) is a write signal i, (j) is a read signal j,
(K) shows the decoded signal k.

Then, in FIG. 2, each numeral indicates a frame number.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG.

First, the frame detection circuit 51 is a circuit that receives compression-coded data that has been compression-coded and to which frame synchronization has been added, and detects frame synchronization. This received compression-coded data b (see FIG. 2B). ), The frame pulse indicating the position is sent to the multiplexing circuit 52. When the multiplexing circuit 52 receives a frame pulse from the frame detection circuit 51, it increments the count of a built-in counter (not shown) to generate a frame number. This counter has a count value equal to or larger than the maximum number of image frames stored in the buffer memory 53, so that it is possible to judge how many frames of image data are stored in the buffer memory 53 when comparing the frame numbers at the input and output of the buffer memory 53. .

Then, the multiplexing circuit 52 multiplexes the generated frame number between the image frame synchronization and the compression coded data that follows based on the frame pulse, sends it to the buffer memory 53, and outputs the generated frame number to the control circuit 56. Send to. Here, the buffer memory 53 is a buffer memory for speed conversion for synchronizing the compression coded data received via the transmission line with the decoding timing of the compression decoding circuit 55, and the multiplexing circuit 52 multiplexes the frame numbers. The encoded data is written, and the compression-encoded data is read according to the read clock from the inhibition circuit 57.

Next, the data read from the buffer memory 53 is
Frame separation is performed in the separation circuit 54, the frame synchronization signal and the frame number multiplexed by the multiplexing circuit 52 are separated, and the separated frame number is sent to the control circuit 56.
The compression encoded data is sent to the compression decoding circuit 55, respectively.

Then, the control circuit 56 receives the frame number of the frame being written to the buffer memory 53 and the frame number of the frame being read from the buffer memory 53 from the multiplexing circuit 52 and the demultiplexing circuit 54, respectively, and the decoding frame from the compression decoding circuit 55. The frame pulse indicating the beginning of the frame pulse is received, two frame numbers are compared every time the frame pulse is received, and when the frame numbers match, the inhibition signal e (Fig. 2 (e in Fig. 2 (e )reference)
Then, the inhibition circuit 57 inhibits the read clock of the buffer memory 53 in response to the inhibition signal e, and controls the readout of the buffer memory 53. Here, the generation of the inhibition signal e is determined and determined for each frame pulse from the compression / decoding circuit 55.

On the other hand, this inhibition signal e is supplied to the compression decoding circuit 55,
Notify that the reading from the buffer memory 53 is stopped. The compression / decoding circuit 55 reads out and decodes the compression coded data from the buffer memory 53 according to a predetermined compression / decoding method, and the separation circuit 54
The read clock is supplied to the buffer memory 53 via the suppression circuit 57 and the decoded frame pulse d.
(See FIG. 2D) is supplied to the control circuit 56. Also,
The decoding operation is stopped while receiving the inhibition signal e from the control circuit 56.

Next, the image signal decoded by the compression decoding circuit 55 is sent to the buffer memory 58. This buffer memory 58 has 2
It has a frame memory for frames and alternately writes the decoded signal in frame units. When the reading is not completed, the decoded signal at that time is not written and thinned out. Further, the compression / decoding circuit 55 outputs the inhibition signal e from the control circuit 56 to the buffer memory 58, and the buffer memory 58 does not write the decoded signal when the inhibition signal e is output.

Then, the clock generation circuit 59 generates a read clock of the buffer memory 58 and a frame pulse to generate the timing of the decoded signal. The buffer memory 58 is read by alternately reading the data in the two frame memories frame by frame at the timing of the clock generation circuit 59. When the read data is insufficient, the same frame is read twice to obtain the insufficient data. Are replenished to reproduce a continuous decoded signal k (see FIG. 2 (k)).

Next, description will be given with reference to FIG. 2 which is an operation time chart showing the operation example of FIG.

First, the coded frame number a shown in FIG. 2 (a) indicates the time series of the frame to be coded, and is a signal synchronized with the frame of the image signal. By encoding this by the compression decoding method, the amount of generated information of each frame changes for each frame like the reception compression encoded data b shown in (b) of FIG. The received compressed coded data b is smoothed and decoded in the buffer memory 53. However, if the coding and decoding frequencies are not synchronized, the data in the buffer memory 53 is lost (compressed) during compression decoding.・ Flow) or shortage (underflow) will occur. Therefore, as in the present invention, as in the case of the decoded frame pulse d shown in FIG. 2 (d), the decoded frame frequency is set higher than the encoded frame frequency so that the buffer memory 53 is always in the underflow state. 2 to compare the frame numbers indicating the time series of the input / output data of the buffer memory 53, and when they are the same, that is, when the buffer memory 53 stores less than one frame of data, FIG. 2 (e). The underflow of the buffer memory 53 is prevented by generating the inhibition signal e as shown in FIG. 2 (frames in the shaded area of the compressed and decoded data c shown in FIG. 2C) to stop the decoding.

Next, the compression-decoded compression-decoded data c (see FIG. 2 (c)) has a frequency higher than the frame frequency of the normal image, and this must be converted to a predetermined frequency. The buffer memory 58 has that function, and the clock generation circuit 59 generates an output frame pulse f (see FIG. 2 (f)) having a normal frame frequency,
The buffer memory 58 is read. The compressed / decoded data c (see FIG. 2 (c)) is the write signals g and i.
(See FIGS. 2 (g) and 2 (i)) and written in each frame memory of the buffer memory 58. However, as in the 16th frame (see (16) of the write signal i shown in FIG. 2 (i)) and the 26th frame (see (26) of the write signal g shown in FIG. 2 (g)), If the write data of is not read, writing is prohibited. Then, the written data is read signals h and j.
(See FIGS. 2 (h) and 2 (j)) are alternately read and multiplexed to reproduce the decoded signal k (see FIG. 2 (k)).

〔The invention's effect〕

As described above, according to the present invention, the compression decoding frequency is set to be higher than the compression encoding frequency, the decoded signal of the compression decoding circuit is written, and the buffer memory that reads out in frame units at a predetermined frequency is normally used. By adopting the two-stage configuration of converting to the frequency of, there is an effect that a compression decoding error does not occur even when the coding frequency of the image signal and the frequency of the decoded image signal are different.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart used to explain the operation of FIG. 51 ... Frame detection circuit, 52 ... Multiplexing circuit, 53 ... Buffer memory, 54 ... Separation circuit, 55 ... Compression / decoding circuit, 56 ... Control circuit, 57 ... Suppression circuit, 58 ... Buffer memory, 59 …… Clock generation circuit.

Claims (1)

[Claims] 1. A band compression decoding apparatus for decoding a band compression coded moving picture television signal, wherein compressed coded data to which frame synchronization is added for each frame of an image signal is received, and the compressed coded data of the compressed coded data is received. A frame detection circuit that detects frame synchronization, and a multiplexing that generates a frame number indicating the time series of the image frame for each image frame detected by this frame detection circuit and multiplexes the frame number at the beginning of the compression encoded data. A circuit, a first buffer memory for storing compression coded data in which the frame numbers are multiplexed, and compression decoding for reading the compression coded data stored in the first buffer memory and decoding at a speed faster than the compression coding The circuit and frame compression are detected from the compression coded data read from the first buffer memory to detect the frame number. The separation circuit to be separated and the frame number separated by this separation circuit are compared with the frame number generated in the multiplexing circuit, and when they are equal, the first buffer memory is read in one frame decoding time unit. A control circuit for inhibiting the decoding operation of the compression decoding circuit and stopping the decoding operation of the compression decoding circuit; and a second buffer memory for writing the decoded signal of the compression decoding circuit and reading it in frame units at a predetermined frequency. Characteristic band compression decoding device.