JPH0698164A - High density integrated circuit for high-speed picture processing - Google Patents

Abstract

PURPOSE:To allow a high-speed picture data processing to have flexibility, and to speed up the processing by simultaneously executing the binarization processing of picture data in a signal reading system, and the media conversion processing of the picture data in a signal recording system in parallel. CONSTITUTION:The signal reading system, signal recording system, and media conversion system are independently constituted. In the signal reading system, an original placed on an original platen 5 is scanning-read by an original reading sensor 3, and scanning-converted into a corresponding analog signal. Next, this signal is converted into a digital signal by an A/D converter 2, and inputted through an input bus 32 to a high density integrated circuit 1 for a high speed picture processing as multiple picture data. In the signal recording system, serial binary picture data generated by a decoder 6 is inputted through a picture bus 37 to the circuit 1, converted into the binary picture data by a serial/parallel converting part 23, and supplied to a medial converting part 26. In the medial conversion system, the serial binary picture data from the decoder 6 are inputted through the bus 37 to the circuit 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-density image processing high-density integrated circuit for processing image data at high speed,
In particular, in a facsimile system, high-density for high-speed image processing suitable for performing binarization processing of multi-valued image data supplied from document reading means and media conversion processing of binary image data received via a line. Related to integrated circuits.

[0002]

2. Description of the Related Art Conventionally, as a facsimile system provided with a high-density integrated circuit for image processing, the following is known.

One of them is Japanese Patent Laid-Open No. Sho 60-94576.
The high-density integrated circuit for image processing disclosed in this facsimile system constitutes a one-chip high-density integrated circuit (LSI), and includes an analog signal processing unit and a digital signal processing unit. , Sensor driver interface, timer, sequencer, CPU interface, etc. In this high-density integrated circuit for image processing, an input bus for binary image data and a system bus are shared, and an image output bus and a memory bus are shared even in a high speed operation mode.

The second is the National Tec.
hnical Report Vol. 29 No. Two
Apr. 1983 pp80-85 "Facsimile control LSI", and in this facsimile system, by using a high-density integrated circuit for image processing, both-end deleting means at the time of transmission of an integral multiple of 32 pixels, and , Which can execute white pixel addition means at the time of reception, and additionally has a built-in ROM or RAM
When inserting the character stored in,
The insertion position and the character size can be set.

The third is electronic technology 1988-4.
This is disclosed in p.69 "Introduction of ASIC in Ultra High Speed Facsimile", and in this facsimile system, a block diagram showing a configuration capable of high speed image processing is shown. Means for operating the value image processing in parallel are also shown.

The fourth is the journal of the Institute of Image Electronics Engineers of Japan, 1986.
Vol. 15 No. 2 pp93-99, in which, in this facsimile system, a scaling algorithm for processing a read signal at high speed is shown, and when the size is enlarged, the enlargement is performed when reading from the line memory. When the size is reduced, the reduction process is performed at the time of writing to the line memory.

The fifth one is disclosed in Japanese Unexamined Patent Publication No. 4-107056. In this facsimile system, a bus for transferring image data from a decoding means to a printer is made independent from an MPU bus. It is designed to perform high-speed data processing.

[0008]

However, since all of the above-mentioned facsimile systems use the known image data processing system for facsimiles, an A4 size document is read at a resolution of 400 dpi (dots / inch). ), Read the original in 1 second,
Moreover, there is a problem that it is not suitable for realizing high speed processing such as recording at a constant speed.

In each of the facsimile systems, one image processing high-density integrated circuit (LSI) is used to simultaneously perform image data processing for both reading image data and recording image data. In addition, in the non-operation state in which the image data is not read and the image data is not recorded, the LSI
There was a problem that media conversion processing could not be executed inside.

Further, in any of the facsimile systems, when the number of lines to be processed is not determined at the start of the execution of the image data processing, the above processing cannot be executed, and the media conversion is not possible. In order to combine preset media during processing, it is necessary to separately prepare a memory for storing media for storing the media, and further, after the media conversion processing, the data after the media conversion processing is performed in the MPU. There was also the problem that it could not be edited.

The present invention eliminates all of the above-mentioned problems, and an object thereof is to allow image data processing in a high-density integrated circuit for image processing to operate in parallel, and to provide flexible and high-speed image data processing. It is to provide a high-density integrated circuit for high-speed image processing that enables the above.

[0012]

In order to achieve the above object, the present invention provides a signal reading system for outputting input multi-valued image data as binary image data by binarization processing, and an input 2 system.
A signal recording system for outputting value image data as image recording data by media conversion and an external MPU are coupled to M
A PU bus, an input bus to which the input multi-valued image data is supplied, an output bus for sending out image recording data from the signal recording system, and an output binary image data from the signal reading system. In a high-density integrated circuit for image processing, which comprises an image bus for inputting binary image data to a signal recording system and a memory bus for connecting an external memory, the image bus outputs from the signal reading system. It is composed of a first image bus for transmitting value image data and a second image bus for inputting binary image data to the signal recording system, and is built in each part of the signal reading system and the signal recording system. A means for operating the signal reading system and the signal recording system simultaneously and independently by setting the registered register is provided.

[0013]

According to the above-mentioned means, the MPU bus, the input bus to which the input multi-valued image data is supplied, and the output binary image data are respectively sent out into the high-density integrated circuit for high-speed image processing. In the signal reading system, the image bus (output bus), the second image bus (input bus) to which the input binary image data is input, and the output bus to which the image recording data is sent are independently provided. It becomes possible to simultaneously execute the binarization processing of the image data and the media conversion processing of the image data in the signal recording system in parallel. Therefore, the processing speed of the image data in the high-density integrated circuit for high-speed image processing is remarkably improved, and the speed of image data processing is markedly increased as compared with the conventional high-density integrated circuit for image processing of this kind. be able to.

Further, according to the above-mentioned means, as a specific structure, the pin for inputting and outputting the signal indicating the end of the page is led to the high-density integrated circuit for high-speed image processing. By notifying the end timing, the necessary processing can be executed even when the number of lines to be processed cannot be determined when the execution of reading the image data or recording the image data is started.

Further, according to the above means, as a concrete configuration, a media conversion processing memory (second memory) coupled to a high-speed image processing high-density integrated circuit is provided as a media conversion area, a recording buffer area, and a flower. Since it is divided into character addition areas, in high-density integrated circuits for high-speed image processing,
Using these areas, media conversion, recording buffer, and flower character addition functions can be time-division multiplexed and accessed.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a high density integrated circuit for high speed image processing according to the present invention.

In FIG. 1, 1 is a high-density integrated circuit (S-FVP) for high-speed image processing, 2 is an analog-digital converter (A / D), 3 is a document reading sensor including a CCD (charge coupled device), etc. 4, 4 is a document, 5 is a document table, 6 is a decoder, 7 is a digital-analog converter (D / A), 8
Is an MPU (control unit), 9 is a first external additional memory (F
IFO), 10 is an encoder, 11 is a recording device (LP) such as a laser printer, 12 is a second external additional memory (memory for media conversion processing), 13 is a read distortion correction unit, and 14 is a read high image quality. , 15 is a basic clock signal generator, 16 is an MPU interface (I / F), 1
7 is a sensor interface (I / F), 18 is a read timing setting unit, 19 is a video memory interface (I / F), 20 is a first changeover switch, 21 is a parallel-serial conversion unit, and 22 is a second changeover switch. Switch, 2
3 is a serial-parallel conversion unit, 24 is a third changeover switch, 25 is a media conversion timing setting unit, 26 is a media conversion unit, 27 is a recording buffer reading unit, 28 is a flower character addition control unit, and 29 is a media conversion basic unit. A clock signal generator, 30 a memory interface (I / F) for media conversion, 31 a recording interface (I / F),
32 is an input bus, 33 is a sensor bus, 34 is an MPU bus, 35 is a first memory bus, 36 is a first image bus,
37 is a second image bus, 38 is an output bus, and 39 is a second memory bus.

The high-density integrated circuit 1 for high-speed image processing
Is a read distortion correction unit 13 and a read image quality improvement unit 1 inside.
4, basic clock signal generator 15, MPU interface 16, sensor interface 17, read timing setting unit 18, video memory interface 19,
First changeover switch 20, parallel-serial conversion unit 2
A signal reading system including the first and second changeover switches 22, a serial-parallel conversion unit 23, and a third changeover switch 2
4, media conversion timing setting unit 25, media conversion unit 26, recording buffer reading unit 27, flower character addition control unit 2
8, a media conversion basic clock signal generator 29, a media conversion memory interface 30, and a recording interface 31 are provided as a signal recording system, and an input bus 32 connected to an external analog-digital converter 2 is provided. A sensor bus 33 connected to the external document reading sensor 3, a second image bus 37 connected to the external encoder 10, an MPU bus 34 connected to the external MPU 8, and an external first memory 9. First memory bus 35 connected, first image bus 36 connected to external decoder 6, output bus 3 connected to external recording device 11
8. Each has a second memory bus 39, which is also connected to the external second memory 12, therein.

That is, in this embodiment, the signal reading system, the signal recording system, the MPU bus 34 to which the control command from the MPU 8 is supplied, and the multi-valued image data from the analog-digital converter 2 are stored. Input bus 34,
A first memory bus 35 used when processing multi-valued image data, a second image bus 37 to which binary image data from the decoder 6 is input in parallel, and used when media conversion processing of binary image data is performed. A second memory conversion bus 39 for media conversion, a first image bus 36 for outputting binary image data in parallel to the encoder 10, and an output bus 3 for serially outputting a media conversion signal to the recording device 11.
8 are independent of each other.

The outline of the operation of the high-speed image processing high-density integrated circuit 1 having the above-described configuration is as follows.

First, the operation of the signal reading system will be described. After the document 4 placed on the document table 5 is scanned and read by the document reading sensor 3, photoelectric conversion is performed to generate a corresponding analog signal. This analog signal is
The digital signal is converted into a digital signal in the digital converter 2 and is input as multi-valued image data to the high-density integrated circuit 1 for high-speed image processing via the input bus 32. The multi-valued image data input to the high-speed image processing high-density integrated circuit 1 is first subjected to distortion correction in the reading distortion correction unit 13,
Next, the distortion-corrected multivalued image data is binarized by the read image quality improving unit 14. This binarization process
This is executed using the video memory interface 19 and the first external additional memory 9 connected via the first memory bus 35, and the control of the first external additional memory 9 is performed by the video memory interface 19. Here, the binarized binary image data is supplied to the parallel-serial conversion unit 21 via the first changeover switch 20, where it is converted into serial binary image data, and then this serial binary image is converted. The data is transferred to the encoder 10 via the second changeover switch 22 and the first image bus 36.

Next, the operation of the signal recording system will be described. The serial binary image data generated by the decoder 6 is
It is input to the high-density integrated circuit 1 for high-speed image processing via the second image bus 37. High-density integrated circuit for high-speed image processing 1
In the above, the serial binary image data is converted into parallel binary image data in the serial-parallel converter 23 via the third changeover switch 24, and is supplied to the media converter 26. The media conversion unit 26 performs media conversion processing such as enlargement / reduction on the input binary image data. This media conversion processing is executed using the media conversion second memory bus 39 connected via the media conversion memory interface 30 and the second memory bus 39. here,
The media conversion second memory bus 39 includes a line memory area for cutting out a media conversion processing window,
It has a buffer area for speed conversion that temporarily buffers the processed data and extracts it according to the output speed, and a flower character registration area that stores the character-added media that is registered in advance, and these areas are time-shared. Is accessed at. The serial image data thus media-converted is transferred to the recording device 11 via the recording interface 31 and the output bus 38.

In this embodiment, since the signal reading system and the signal recording system do not have a common component, the two systems are operated simultaneously and independently and with different timing clocks. It is possible to let

The operation of the media conversion system will be further described. Serial binary image data generated by the decoder 6 is input to the high-speed image processing high-density integrated circuit 1 through the second image bus 37. . Next, in the high-speed image processing high-density integrated circuit 1, the serial binary image data is converted into parallel binary image data in the serial-parallel conversion unit 23 via the third changeover switch 24, and the media conversion unit 26. Is supplied to. The media conversion unit 26 performs media conversion processing such as enlargement / reduction on the input binary image data. This media conversion processing is executed using the media conversion second memory bus 39 connected via the media conversion memory interface 30 and the second memory bus 39. Here, the second media conversion memory bus 39 is
Media conversion processing window A line memory area for cutting out and temporarily buffering the processed data,
A buffer area for speed conversion that is extracted according to the output speed,
It has a flower character registration area for storing the character-added media that is registered in advance, and these areas are accessed in a time division manner to the point where the media-converted serial image data is obtained. This is the same as the operation of the signal recording system. However, in the media conversion system, instead of supplying the serial image data to the recording device 11 via the recording interface 31 or the like as in the signal recording system, the first switching is switched to the signal recording system side. After being supplied to the parallel-serial conversion unit 21 via the switch 20 and converted into serial binary image data there, this serial binary image data is sent via the second changeover switch 22 and the first image bus 36. It is transferred to the encoder 10.

The operation of the media conversion system is enabled when the operation of the signal reading system and / or the recording processing system is not executed.

Next, FIGS. 2, 3 and 4 (a) show the functions of a plurality of write registers incorporated in the respective parts of the high-speed image processing high-density integrated circuit (S-FVP) 1. Similarly, FIG. 4B shows the respective functions of the plurality of read registers incorporated in the respective parts of the high-speed image processing high-density integrated circuit (S-FVP) 1.

2 to 4, the leftmost column is 0
Register numbers (#) such as 0, 01, 02, ..., 9D, 9E, and ADRR, TDAM,
..., ..., register names such as MDOD, the rightmost column, access port address setting, S-FVP output mode setting,
..., ..., respectively, showing the functional outline of the media conversion software output register and the like.

By setting the contents shown in FIGS. 2 to 4 in each of these registers before starting desired image data processing in the high-speed image processing high-density integrated circuit 1, It becomes possible to control the image data page by page without the intervention of software.

Here, by using each of the above registers,
Each control procedure in the signal reading system, the signal recording system, and the media conversion system will be described.

First, regarding the control procedure of the signal reading system, FIG. 5 showing the relationship between the reading parameter and the value of each register.
The operation will be described with reference to the operation explanatory diagram.

First, when an instruction to start reading is given from an operation unit such as a panel, the MPU 8 turns on a fluorescent lamp on the document placing table 5 to detect a read start point DET.
-Advance the document reading motor until it becomes BON.
In addition, each register 2F, 30, 31, 32, 44, 45, 46, 47 incorporated in the high-density integrated circuit 1 for high-speed image processing.
Shading correction start pixel position SCSSX, shading correction end pixel position SCSEX, peak value detection start pixel position SCPS within one line based on the setting contents of
X and the peak value detection end pixel position SCPEX are set.

Next, based on the setting contents of the register 05, writing is performed to the WCOM port, peak value detection and shading waveform writing are executed, and it is checked whether or not there is any abnormality in the fluorescent lamp.

Then, the reading start counter is read, and the registers 33, 34, 39, 3A, 41, 42, 3B, 3C in the high-density integrated circuit 1 for high-speed image processing are incorporated.
Based on the setting contents of 43, according to the sub-scanning read line density, the write line position SCSSY of the shading waveform immediately before the start of reading, the automatic shading correction mode A
UTOSHD, read image processing start line position SCVS
Y, the image transfer start line position SCBSY, the number of lines SCVLY after the non-detection state DET-B OFF of the reading start point until the end of the reading image processing, MP after the reading image processing
Set the number of lines SCBLY until the interrupt to U8 occurs. Further, each of the registers 35, 36, 37, 38, 3D built in the high-density integrated circuit 1 for high-speed image processing,
Based on the settings of 3E, 3F, 40, 2A, and 2B,
Image processing start pixel position SCVSX, image processing end pixel position SCVEX, image transfer start pixel position SC within one line
BSX, the number of image output bytes SCBNX, and the main scanning enlargement (reduction) ratios SCRUX and SCRDX are set.

Next, the MPU 8 sets the encoding processing start bit of the encoder 10 to "1".

Subsequently, the MPU 8 drives the original reading motor, and the control gate array generates the image processing start signal TSCAN to the high-speed image processing high-density integrated circuit 1.

Next, a high-density integrated circuit 1 for high-speed image processing
Updates the shading waveform write position counter and the read start position counter for each image processing start signal TSCAN, and the count value of each counter is the write line position SCSS of the shading waveform immediately before the start of reading.
When the read image processing start line position SCVSY becomes equal to Y, writing and reading of the shading waveform are started.

Next, 2 in the reading image quality improving section 14
When the binary image data after the binarization process has 8 bits,
The high-speed image processing high-density integrated circuit 1 generates a data request signal DREQ to the encoder 10 and requests transfer of binary image data. If the transfer of the previous binary image data is not completed before the next 8-bit binary image data is prepared, the previous binary image data is destroyed.

Next, a high-density integrated circuit 1 for high-speed image processing
Detects the edge portion from the ready state DET-B ON of the reading start point to the non-detection state DET-B OFF of the reading start point, and starts the reading end counter.

Here, when the count value of the reading end counter becomes equal to the number of lines SCVLY until the end of the reading image processing after the non-detection state DET-B OFF of the reading start point, the reading image quality improving section 14 operates. The binarization process is stopped, and the generation of the data request signal DREQ to the encoder 10 is also stopped.

Next, when the number of lines SCBLY is reached after the completion of the read image processing, the high-speed image processing high-density integrated circuit 1 interrupts the MPU 8 to indicate that the reading of the image data for one page of the original is completed. Inform.

The same applies to the second and subsequent pages of the manuscript.
The operation after the read operation of the read start counter is repeatedly executed.

Next, the control procedure of the signal recording system will be described with reference to the operation explanatory diagram of FIG. 6 showing the relationship between the recording parameter and the value of each register.

First, the MPU 8 includes the registers 4D, 4E, 4F, 5 built in the high-density integrated circuit 1 for high-speed image processing.
0, 48, 49, 4A, 4B, 53, 54, 51, 5
2, 55, 56, 59, 5A, 57, 58, 5B, 5
C, 5D, 5E, 61, 62, 5F, 60, 63, 64
The number of image input bytes per line M based on the setting contents of
DISX, sub-scanning image input line number MDISY, main-scanning enlargement (reduction) ratio MDRUX, MDRDX, sub-scanning enlargement (reduction) ratio MDRUY, MDRDY, main-scan output byte number MDOSX, sub-scan output line number MDOSY, main-scan left margin End position MDMSX, main scan right margin start position MDMEX, sub scan upper margin end position MDMSY, sub scan upper margin start position MDMEY, main scan image read start position MDBSX, main scan image read end position MDBE
X, the sub-scanning image reading start position MDBSY, and the sub-scanning image reading end position MDBEY are set.

Next, the MPU 8 sets the decoding process start bit of the decoder 6 to "1".

Subsequently, the MPU 8 switches to the recording side to set the third switching switch 24 and the first switching switch 20 of the high-speed image processing high-density integrated circuit 1 to the recording side, respectively. Set.

Next, the MPU 8 starts the media conversion start MDSTA of the high-speed integrated circuit 1 for high-speed image processing.
Set to 01H "and start the initial.

Subsequently, the high-density integrated circuit 1 for high-speed image processing
Generates a data request RDREQ for each byte to the decoder 6, and direct memory access DMA
The transferred binary image data is media-converted, and the media-converted image data is transferred to the recording buffer area of the media conversion second external additional memory 12. At this time, when the number of input bytes reaches the number of image input bytes MDISX of one line, it is determined that the input of one line is completed. If the reading of the other surface is completed at the time when the writing of the image data to the recording buffer area is completed, the surface switching is performed.

Next, the MPU 8 instructs the recording device 11 to start recording one page. In this case, since it is not known when the recording line start PLNST will be sent out, the high-density integrated circuit 1 for high-speed image processing is provided with a predetermined time or more from the start of recording processing to the start of recording. It is necessary to keep it.

Subsequently, the recording interface 31 causes the recording line start P to the high-density integrated circuit 1 for high-speed image processing.
Input LNST.

Next, a high-density integrated circuit 1 for high-speed image processing
Outputs the recording data PDATA in synchronization with the recording data transfer clock signal PCLK supplied from the recording device 11. At this time, when the output dot position becomes equal to or higher than the main scanning image reading start position MDBSX, the interpolation image is read from the recording buffer area of the second external additional memory 12 for media conversion until the main scanning image reading end position MDBEX is reached. The data is read and transferred to the recording device 11. The output dot position is the number of bytes in the left margin of the main scan MDM.
When it has not reached SX or when it has exceeded the main scanning right margin start position MDMEX, it is determined to be the margin of the document, and the recorded image data that becomes white is output. The setting of the read position and the margin is the same in the sub-scanning direction. When the reading of the image data is completed, a white output is generated in response to the recording data transfer clock signal PCLK supplied from the recording device 11.
The output dot position is the number of main scan output bytes MDO.
When it reaches SX, it is determined that the reading of one line is completed.

Next, the flower character addition control mode HMOD
Is "1", the image data read out from the recording buffer area is subjected to the pre-registered five types of character media at the designated position.

Next, at the end of the transfer of the image data to the recording device 11, if the writing of the image data after the media conversion is completed, the surface of the recording buffer area is switched.

The operation on and after the next line is the same as the operation on the first line.
The operations after the operation in which the high-speed image processing high-density integrated circuit 1 generates a data request RDREQ for each byte to the decoder 6 are repeated while changing the reading surface. When the number of sub-scanning image input lines MDISY is exceeded during the execution of this operation, the data request RDREQ supplied to the decoder 6 is stopped, and when the number of sub-scanning image transfer lines MDONY is exceeded, the recording buffer When the reading of the image data from the area is stopped and the number of sub-scanning output lines MDOSY is exceeded,
It is determined that the recording and outputting process for the image data is completed, and the MPU 8 is caused to generate the end interrupt RINTN.

Then, the decoder 6 outputs the page end to the high-speed image processing high-density integrated circuit 1 when the last image data of one page is transferred. This enables the decoder 6
The supply of the data request RDREQ supplied to is stopped.

During the processing of the image data, when the media conversion is not transferred in time for the output to the recording device 11, that is, before the transfer of the image data to the recording device 11 is started, the recording is performed. When the writing of the image data of the next line to be recorded in the device 11 is not completed, the high-speed image processing high-density integrated circuit 1 issues an interrupt RINTN to the MPU 8.

Finally, regarding the control procedure of the media conversion system, the MPU, decoder, encoder, and
Description will be made with reference to the operation explanatory diagram of FIG. 7 showing a signal transfer state between the high-density integrated circuits for high-speed image processing.

In this media conversion system, the relationship between parameters and registers is the same as that of the signal recording system shown in FIG.

First, the MPU 8 registers the registers 4D, 4E, 4F, 50, 48, 49, 4 built in the high-density integrated circuit 1 for high-speed image processing as in the case of controlling the signal recording system.
A, 4B, 53, 54, 51, 52, 55, 56, 5
9, 5A, 57, 58, 5B, 5C, 5D, 5E, 6
Based on the setting contents of 1, 62, 5F, 60, 63, 64, the number of image input bytes of one line MDISX, the number of sub-scan image input lines MDISY, the main scanning enlargement (reduction) ratio MD
RUX, MDRDX, sub-scanning enlargement (reduction) ratio MDRU
Y, MDRDY, main scanning output byte number MDOSX, sub scanning output line number MDOSY, main scanning left margin end position M
DMSX, main scan right margin start position MDMEX, sub scan upper margin end position MDMSY, sub scan upper margin start position MDMEY, main scan image read start position MDBSX, main scan image read end position MDBEX, sub scan image read start position MDBSY, Sub-scan image read end position MDBE
Set Y respectively.

Next, the MPU 8 sets the decoding process start bit of the decoder 6 to "1".

Subsequently, the MPU 8 sets the signal reading system and the signal recording system in the high-speed image processing high-density integrated circuit 1 to the non-use state, switches the first changeover switch 20 to the upper side, and the parallel-serial conversion unit. The media conversion route DAM is set to the route 21 and the recording device 11 is set to the output disapproval state.

Then, the MPU 8 sets the media conversion start bit MDSTA of the high-speed image processing high-density integrated circuit 1 to the operating state and the initial start mode MDCONT to the non-operating state.

Then, a high-density integrated circuit 1 for high-speed image processing
Generates a data request RDREQ for each byte to the decoder 6, and direct memory access DMA
The transferred image data is subjected to media conversion and transferred to the recording buffer area of the media conversion second external additional memory 12. Input byte count is 1 line Image input byte count MD
When ISX is reached, it is determined that one line input has been completed. If the reading of the image data of the other surface is completed at the time when the writing of the image data to the recording buffer area is completed, the surface switching is performed.

Next, the MPU 8 sets the encoding process start bit of the encoder 10 to "1".

Next, the high-density integrated circuit 1 for high-speed image processing
Generates a data request DREQ to the encoder 10, and starts transferring the image data in the recording buffer area of the second external medium for media conversion 12 to the encoder 10.

Subsequently, the high-density integrated circuit 1 for high-speed image processing
When the output dot position has not reached the main scanning left margin mask release position MDMSX, it determines that it is a margin and outputs image data showing white. When the output dot position becomes the main scanning left margin mask release position MDMSX or more and the main scanning image reading start position MDBSX or more, the main scanning right margin mask starting position MDMEX.
Alternatively, the image data is read from the recording buffer area of the second external additional memory for media conversion (interpolation memory) 12 to the position of the main scanning image read end position MDBEX, whichever is smaller, and the read image data is read. Transfer to the encoder 10. The read address from the recording buffer area can be designated in byte units in the cutout start address MDBNX. When the reading of the image data is completed, it is "0" after that.
Output (white). When the read address from the recording buffer area reaches the number of main scanning output bytes MDOSX, it is determined that the reading of one line is completed.

Next, the flower character addition control logic HM0LG-H
When M3LG is "2" or "3", for the read image data from the recording buffer area, four types of pre-registered character media of each channel are designated, a double angle designation, and a superposition logic. Expand processing with.

Further, when the transfer of the image data to the encoder 10 is completed and the writing of the image data after the media conversion is completed, the surface of the recording buffer area is switched.

Next, a high-density integrated circuit 1 for high-speed image processing
Stops the direct memory access DMA request to the encoder 10 when the image data input reaches the number of 1-line image input bytes. In this case, the number of 1-line image input bytes and the actual number of input data must be exactly the same.

Subsequently, the high-density integrated circuit 1 for high-speed image processing
Stops the direct memory access DMA request to the encoder 10 when the image data output reaches the number of 1-line image input bytes. Also in this case, it is necessary to exactly match the number of 1-line image output bytes with the actual number of output data.

The operation on and after the next line is the same as the operation on the first line.
The MPU 8 is used by the encoder 1 while changing the reading surface.
The operation after the operation of setting the encoding process start bit of 0 to "1" is repeatedly executed. At this time, when the number of sub-scanning image input lines MDISY is exceeded, the generation of the data request RDREQ to the encoder 10 is stopped, the reading of the image data from the recording buffer area is stopped, and the number of sub-scanning output lines MDOSY.
When it exceeds, it is judged that the output processing to the encoder 10 is completed, and an end interrupt RINTN to the MPU 8 is generated.

Next, the decoder 6 sends a page end R to the high-speed image processing high-density integrated circuit 1 during direct memory access DMA transfer of the last image data of the page.
PENDN is output, which causes the decoder 6 to stop supplying the data request RDREQ. Further, the high-speed image processing high-density integrated circuit 1 causes the encoder 10 to output the page end TPENDN at the time of direct memory access DMA transfer of the last image data of the page. In this case, the number of lines from the page end RPENDN to the page end TPENDN can be specified by the page end delay line number MDPENDL. By this designation, the media conversion process can be interrupted even if the number of lines is less than the set number.

In this case, even if the media conversion processing is completed due to the output of the set number of lines or the supply of the page end RPENDN, the media conversion start M
If DSTA is set to "01H" and a continuous start is generated, the media conversion process can be restarted.

It should be noted that at the time of media conversion, it is possible to edit the image data after the media conversion. If REACT is set to 0 at startup, it can be immediately interrupted when the input or output image data reaches a predetermined value. Therefore, if CHARAE is set to 1, access to image data after media conversion becomes possible. When performing the processing of the next line, the interrupted input or output end value is increased by one line, and the continuous start state MDCONT is set to 1.

Next, the flower character expansion control procedure will be described. In addition, the flower character expansion means that the flower character expansion data is registered in the flower character addition area in the second external additional memory (memory for interpolation) 12 for media conversion,
This is a function that can read the flower character at a predetermined position during recording or media conversion.

First, according to the image editing control procedure,
The flower character data is written in the flower character registration area (for example, after 1400H). There are up to 5 kinds of flower characters, 3 of which are 1024 bytes in the X direction and Y.
It is possible to register up to 16 lines in two directions.
Up to 16 bytes in the X direction and 16 lines in the Y direction can be registered.

Next, each flower character register 70, 71, 7A, 7B, 8 in the high-density integrated circuit 1 for high-speed image processing.
4, 85, 8D, and 8E, start addresses HM0SM, HM1SM, and HM2S of the interpolation memory 12 in the expansion area.
M, HM3SM, each flower character register 69, 6A, 73,
74, 7D, 7E, 87, 88 flower character expansion start X coordinates HM0SX, HM1SX, HM2SX, HM3SX,
Each flower character register 6D, 6E, 77, 78, 81, 8
Number of bytes of 1 line of flower letters in 2.8B, HM0NX, HM
1NX, HM2NX, HM3NX, each flower character register 6
B, 6C, 75, 76, 7F, 80, 89, 8A start Y-coordinates of flower characters HM0SY, HM1SY, HM2
SY, HM3SY, each flower character register 6F, 79, 8
Number of flower letter lines HM0NY, HM1NY in 3 and 8C,
HM2NY, HM3NY, flower character registers 72, 7
HM designation for double-width double-decoration in C, 86, 8F
0BK, HM1BK, HM2BK, HM3BK are specified, and the logic of flower character expansion HM0LG, HM1LG, HM2LG, HM3L is specified in each flower character register (not shown).
G, HM0HEN, HM1HEN, HM2HEN, HM
Specify 3HEN. The double-width designation of flower characters can be set independently in the X and Y directions,
It is possible to specify double, four, and eight times. As for the logic of flower character expansion, it is possible to specify the original image (without flower character expansion), overwrite, or exclusive or EOR.

In this case, when the media conversion is executed, the flower character is automatically expanded, and when the expanded coordinates overlap, the flower character number with the smaller number is prioritized.

Finally, FIG. 8 shows the image editing control procedure.
The data editing process will be described with reference to the explanatory diagram.

This image editing means the second external additional memory (interpolation memory) 12 for media conversion directly from the MPU 8.
Means that the image data after the media conversion is edited, that is, the characters and symbols are added, combined and deleted, and the flower character expansion data is registered.

First, the MPU 8 confirms that the media conversion function is stopped by looking at the status register STAR in the high-speed image processing high-density integrated circuit 1, and sets the interpolation memory access mode CMOD to the character addition state. Is set to "01H".

Next, the address to be accessed is set to the character addition address CADR. Since the high-speed image processing high-density integrated circuit 1 uses the surfaces of the media conversion area and the recording buffer area of the interpolation memory 12 by switching for each line, the address set in the character addition address CADR is the high-speed image. High-density integrated circuit for processing 1
It is automatically converted into the actual usage area within.

Then, when the contents of the designated address are to be read, the character read port CRDDAT is read, and when the contents of the address are to be written, the character write port CWRDAT is written. When such writing and reading are performed, the character addition address CADR is automatically incremented.

FIG. 9 is a block diagram showing an example of a small-scale system constructed by using one high-speed image processing high-density integrated circuit 1 according to the present invention.

In FIG. 9, the same components as those shown in FIG. 1 are designated by the same reference numerals.

Then, the high-density integrated circuit 1 for high-speed image processing
As described above, the signal reading system and the signal recording system are independently provided, and the signal reading process and the signal recording process as described above are performed by switching the first changeover switch (not shown). In addition, each operation of media conversion processing can be executed separately.

Since the operations of the signal reading process, the signal recording process, and the media conversion process have already been described, further detailed description of the operations will be omitted here.

Next, FIGS. 10 and 11 are block configuration diagrams showing an example of a large-scale system configured by using two high-speed image processing high-density integrated circuits 1 according to the present invention. FIG. FIG. 11 shows the processing and signal recording processing part, and FIG. 11 shows the media conversion processing part.

10 and 11, the same components as those shown in FIG. 1 are designated by the same reference numerals.

In this example, two high-speed image processing high-density integrated circuits 1 are used to simultaneously execute the signal reading process, the signal recording process, and the media conversion process. This high-speed image processing high-density integrated circuit 1 is used exclusively for signal reading processing and signal recording processing, and another high-speed image processing high-density integrated circuit 1 is used.
Is used only for media conversion processing.

Regarding the operation of this example, the signal reading process, the signal recording process, and the media converting process have already been described, so that the detailed description of the operation is omitted here.

As described above, according to this embodiment, the high-density integrated circuit 1 for high-speed image processing has the signal reading system and the signal recording system independently, and the separate bus structure. Since a large number of registers having various setting contents are built in, image data processing can be executed at high speed, high image quality, and high function.

[0093]

As described above, according to the present invention,
MP in each high-density integrated circuit 1 for high-speed image processing
U bus 34, input bus 32 to which input multi-valued image data is supplied, first image bus (output bus) 36 for sending output binary image data, and second input bus to which input binary image data is input The image bus (input bus) 37 and the output bus 38 for sending the image recording data are independently provided, so that the binarization processing of the image data in the signal reading system and the media conversion of the image data in the signal recording system are performed. There is an effect that processing and processing can be executed concurrently.

Further, according to the present invention, in addition to the above effects, the processing speed of the image data in the high-speed image processing high-density integrated circuit 1 is remarkably improved. Compared with, there is an effect that the speed of image data processing can be markedly increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a high density integrated circuit for high speed image processing according to the present invention.

2 is an explanatory diagram showing a part of each function of a plurality of write registers incorporated in each part of the high-speed image processing high-density integrated circuit shown in FIG. 1;

FIG. 3 is an explanatory diagram showing another part of each function of a plurality of write registers incorporated in each part of the high-speed image processing high-density integrated circuit shown in FIG. 1;

FIG. 4 is an explanatory diagram showing the remaining part of each function of a plurality of write registers and each function of a read register incorporated in each part of the high-density integrated circuit for high-speed image processing shown in FIG.

FIG. 5 is an operation explanatory diagram showing the relationship between the read parameter and the value of each register.

FIG. 6 is an operation explanatory diagram showing a relationship between a recording parameter and a value of each register.

FIG. 7 is an operation explanatory diagram showing a transfer state of each signal and image data at the time of pattern conversion.

FIG. 8 is an operation explanatory diagram showing a transfer state of each signal and image data during image data editing processing.

FIG. 9 shows a high-density integrated circuit for high-speed image processing shown in FIG.
It is a block configuration diagram showing an example of a small-scale system configured by using individual pieces.

FIG. 10 is a block diagram showing a part of an example of a large-scale system configured by using two high-speed image processing high-density integrated circuits shown in FIG.

FIG. 11 is a block diagram showing the rest of an example of a large-scale system configured by using two high-speed image processing high-density integrated circuits shown in FIG.

[Explanation of symbols]

1 High-density integrated circuit for high-speed image processing (S-FVP) 2 Analog-digital converter (A / D) 3 Document reading sensor composed of CCD (charge coupled device) 4 Document 5 Document mounting table 6 Decoder 7 Digital -Analog converter (D / A) 8 MPU (control device) 9 First external additional memory (FIFO) 10 Encoder 11 Recording device (LP) such as laser printer 12 Second external additional memory (media conversion processing Memory) 13 read distortion correction unit 14 read image quality improvement unit 15 basic clock signal generation unit 16 MPU interface (I / F) 17 sensor interface (I / F) 18 read timing setting unit 19 video memory interface (I / F) 20 1st changeover switch 21 Parallel-serial conversion part 22 2nd changeover switch 23 system Al - parallel converter 24 the third changeover switch 25 media conversion timing setting unit 26 media conversion unit 27 recording buffer readout unit 28 man readable addition control unit 29 media conversion reference clock signal generator 30 media conversion memory interface (I /
F) 31 recording interface (I / F) 32 input bus 33 sensor bus 34 MPU bus 35 first memory bus 36 first image bus 37 second image bus 38 output bus 39 second memory bus

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideaki Aoshima 180 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Within Hitachi Communication Systems Co., Ltd. (72) Inventor Kagehiro Yamamoto 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Address Company Information Technology Division, Hitachi, Ltd. (72) Inventor Yasuyuki Kojima Address: 216 Totsukacho, Totsuka-ku, Yokohama City, Kanagawa Prefecture Information Technology Division, Hitachi, Ltd.

Claims (7)

[Claims] 1. A signal reading system for outputting input multivalued image data as binary image data by binarization processing, and an input 2
A signal recording system for outputting value image data as image recording data by media conversion and an external MPU are coupled to M
A PU bus, an input bus to which the input multi-valued image data is supplied, an output bus for sending out image recording data from the signal recording system, and an output binary image data from the signal reading system. In a high-density integrated circuit for image processing, which comprises an image bus for inputting binary image data to a signal recording system and a memory bus for connecting an external memory, the image bus outputs from the signal reading system. It is composed of a first image bus for transmitting value image data and a second image bus for inputting binary image data to the signal recording system, and is built in each part of the signal reading system and the signal recording system. A high-density integrated circuit for high-speed image processing, characterized in that the signal reading system and the signal recording system are operated simultaneously and independently by the setting of the registered register. 2. The memory bus is used during binarization processing of the input multi-valued image data, and includes a first memory bus to which a first external memory is coupled, and the input binary image data. The high-density integrated circuit for high-speed image processing according to claim 1, characterized in that the high-density image processing integrated circuit comprises a second memory bus used for media conversion and having a second external memory coupled thereto. 3. The signal reading system includes a first direct memory access means on the output side thereof, and the first direct memory access means outputs the binary image data from the signal reading system and the signal recording system. 2. A high-density integrated circuit for high-speed image processing according to claim 1, further comprising switching means for selectively outputting the output image recording data from the. 4. The signal reading system has first switching means for selectively supplying the output data of the first direct memory access means to the first image bus and the MPU bus. The high-density integrated circuit for high-speed image processing according to claim 1, characterized in that. 5. The signal recording system includes a second direct memory access unit on an input side thereof, and the second image is provided between the second image bus and the second direct memory access unit. Input data from the bus or the M
2. The high-density integrated circuit for high-speed image processing according to claim 1, further comprising second switching means for selectively supplying input data from the PU bus to the second direct memory access means. 6. The signal recording system includes three circuit portions including a media conversion portion, a recording buffer reading portion, and a flower character addition control portion, and a second external memory is provided as a medium corresponding to these three circuit portions. 2. The high-density image processing high-density according to claim 1, wherein the high-speed image processing is divided into a conversion area, a recording buffer area, and a flower character addition area, and each of the divided areas is time-division multiplexed accessed. Integrated circuit. 7. After inputting a signal (RPEND) indicating the end of one page as an input terminal to the means for binarizing multivalued image data, the end of one page is indicated as an output terminal from the means for selecting the conversion result. The high-density integrated circuit for high-speed image processing according to claim 1, further comprising a register for designating the number of lines until a signal (TPEND) is generated.