JPH0697794B2 - Line interface circuit - Google Patents
Line interface circuitInfo
- Publication number
- JPH0697794B2 JPH0697794B2 JP59221915A JP22191584A JPH0697794B2 JP H0697794 B2 JPH0697794 B2 JP H0697794B2 JP 59221915 A JP59221915 A JP 59221915A JP 22191584 A JP22191584 A JP 22191584A JP H0697794 B2 JPH0697794 B2 JP H0697794B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- relay
- signal
- dial pulse
- line interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
Description
【発明の詳細な説明】 （産業上の利用分野） この発明は加入者線路を介して交換機と接続される回線
インターフェース回路で、特に、この回路より交換機へ
ダイヤルパルス信号送出時に発生する鳴音を抑制する回
路に関するものである。Description: TECHNICAL FIELD The present invention relates to a line interface circuit connected to an exchange through a subscriber line, and in particular, a ringing sound generated when a dial pulse signal is transmitted from the circuit to the exchange. It relates to a suppressing circuit.
（従来の技術） 第２図は従来の回線インターフェース回路の一構成例を
示す図で、通常トランクの空状態を示す。図において、
交換機OSから加入者線路SLを介して直信があった場合、
着信検出回路RDで着信検出を行ない、制御回路CC内の図
示しないB,Cリレーを動作させ、その接点b,cを切替えて
通話状態とする。また空トランクから交換機OSへ発信を
行なう場合、B,Cリレーを動作させて発信を行なう。発
信した後、交換機OSへ制御回路CCよりダイヤルパルス信
号の送出を行なうが、この場合、制御回路CC内の図示さ
れないA,A′リレーを動作させ、そのリレー接点a,a′を
抵抗RA,RB側へONしてＢリレーのON/OFFで低抵抗ルー
プ、高抵抗ループ状態としてダイヤルパルス信号の送出
を行なう。次に、ダイヤルパルス信号の送出後、交換機
OSから相手応答信号が送出され、それを受信して通話状
態となる。ここで通話状態とは内線電話機等の端末から
図示しない内線加入者回路を通り、ハイウエー−タイム
スイッチ（時分割スイッチ）−ハイウエー−トランスの
順に信号（音声等）が流れ、トランクではハイウエーHW
から符号復号器CODECを通り、・増幅器AMP1から２線−
４線交換ハイブリッドトランス（以下、トランスＴとい
う）の２次側を介して１次側へ、そして加入者線路SL−
交換機OSへ、また逆に交換機OSから加入者線路SLを通
り、トランスＴの１次側から２次側を通り、増幅器APM2
を通して符号復号器CODECからハイウエーHW−タイムス
イッチ−ハイウエーHW−内線加入者回路を通り端末へ信
号が伝えられる。なお図中Rlは交流高抵抗・直流低抵抗
回路、DECは回路選択信号用デコーダ、Selは回路選択信
号、BNWは整合インピーダンスを示す。(Prior Art) FIG. 2 is a diagram showing a configuration example of a conventional line interface circuit, showing an empty state of a normal trunk. In the figure,
If there is a direct communication from the exchange OS via the subscriber line SL,
The incoming call detection circuit RD detects an incoming call, and activates the B and C relays (not shown) in the control circuit CC to switch the contacts b and c to put them in a call state. When making a call from the empty trunk to the exchange OS, the B and C relays are operated to make the call. After the transmission, a dial pulse signal is sent from the control circuit CC to the exchange OS. In this case, the A, A'relays (not shown) in the control circuit CC are operated and the relay contacts a, a'are connected to the resistor RA. , low resistance ON / OFF of the B relay is turned ON to R B-loop, performs the transmission of the dial pulse signal as a high-resistance loop. Next, after sending the dial pulse signal, the exchange
The other party's response signal is sent from the OS, and it receives it and enters the call state. Here, the call state means that a signal (voice, etc.) flows in the order of highway-time switch (time division switch) -highway-transformer from a terminal such as an extension telephone through an extension subscriber circuit (not shown), and a highway HW in a trunk.
From the encoder / decoder CODEC to the amplifier AMP1 to 2 lines −
4-line exchange hybrid transformer (hereinafter referred to as transformer T) to the primary side through the secondary side, and subscriber line SL-
To the exchange OS, and vice versa, from the exchange OS through the subscriber line SL, from the primary side of the transformer T to the secondary side, and the amplifier APM2
A signal is transmitted from the code decoder CODEC to the terminal through the highway HW-time switch-highway HW-extension subscriber circuit. In the figure, Rl is an AC high resistance / DC low resistance circuit, DEC is a circuit selection signal decoder, Sel is a circuit selection signal, and BNW is a matching impedance.
ところで、Ａリレー、抵抗RAがなければダイヤルパルス
送出時にＢリレーがOFF状態になると、符号復号器CODEC
側から見たインピーダンスが大きくなり、インピーダン
スマッチングが崩れて増幅器AMP1から出た信号が増幅器
AMP2側へ反射して鳴音が発生するので、トランスＴの１
次側を抵抗RAで終端してインピーダンスマッチングを行
ない鳴音の発生を抑えていた。By the way, if there is no A relay and resistance R A , if the B relay is turned off during dial pulse transmission, the code decoder CODEC
The impedance seen from the side becomes large, the impedance matching collapses, and the signal output from the amplifier AMP1 is amplified.
Since the sound is generated by being reflected to the AMP2 side, 1 of the transformer T
Impedance matching was performed by terminating the secondary side with a resistor RA to suppress the generation of noise.
（発明が解決しようとする問題点） しかしながら、上記構成の回線インターフェース回路で
は、リレーＡ、抵抗RAで、タイヤルパルス送出時のみ終
端をする必要があり、専用にＡリレーとRA抵抗が必要と
なり、それだけ部品点数が増加し、装置が大きくなる等
の欠点があった。したがって、この発明はＡリレー及び
RA抵抗等を削除し、ハード（部品点数）を少なくして装
置を小型化することにある。(Problems to be Solved by the Invention) However, in the line interface circuit having the above configuration, the relay A and the resistor R A need to be terminated only when sending a tire pulse, and the A relay and the R A resistor are required exclusively. Therefore, there are drawbacks such as an increase in the number of parts and an increase in the size of the device. Therefore, this invention is
R A resistor is removed to reduce the hardware (number of parts) and downsize the device.
（問題点を解決するための手段） この発明は前記問題点を解決するため、回線インターフ
ェース回路において、符号復号器に供給する選択信号を
リレーの駆動信号と回路選択信号又はCODECに与えるCK
との論理積（AND条件）で作るようにしたものである。(Means for Solving Problems) In order to solve the above problems, the present invention provides a circuit interface circuit in which a selection signal to be supplied to a code decoder is applied to a relay drive signal and a circuit selection signal or CODEC.
It is made by the logical product (AND condition) with.
（作用） このようにするとダイヤルパルス送出時に選択信号を抑
制して符号復号器以降のディジタル信号を出さないため
鳴音の発生を抑える。(Operation) In this way, the selection signal is suppressed when the dial pulse is transmitted, and the digital signal after the code decoder is not output, so that the generation of ringing noise is suppressed.
（実施例） 第１図と第３図は、この発明の実施例を示す回路図であ
って、第２図と同一部分には同一の参照符号を付した。
図に示すように入力端子1,2は加入者線路SLを介して交
換機OSに接続される。そして交換機OSに対して先ず制御
回路CCのＤリレー及び図示しないＢリレーをONにして、
低抵抗ループ（直流的に）Rlを交換機OSに対して閉じ
（送出し）、その後ダイヤルパルスを送出する場合、制
御回路CC内のD,A′リレー（図示せず）をOFF（第１図の
状態）して、ＢリレーをON/OFFし、抵抗RBの抵抗ルー
プ、高抵抗ループを交互に送出する。その場合、高抵抗
ループ送出時トランスＴの１次側が開放状態となり、増
幅器AMP1側から増幅器AMP2への信号のリターンが大きく
なるがD,A′リレーをOFFするため、選択信号用デコーダ
DECの出力とＤリレー駆動信号RDV又はCKとＤリレー駆動
信号RDVとの論理積（AND）回路を設けＤリレー駆動信号
RDVを“O"にして符号復号器CODECの選択信号Sync又はCK
を抑制するので、符号復号器CODEC以降のディジタル信
号を出さない。そのため鳴音の発生を抑えることができ
る。また、選択信号Syncによるパワーダウンモード機能
付きの符号復号器CODECを使用した場合、リレー駆動信
号RDVと回路選択信号用デコーダDECの出力との論理積
（AND条件）で選択信号Syncを作っているのでＤリレー
が動作していない時（待機中）、符号復号器CODECのパ
ワーダウンを行なえ待機中の消費電力を軽減できる。(Embodiment) FIGS. 1 and 3 are circuit diagrams showing an embodiment of the present invention, in which the same parts as those in FIG. 2 are designated by the same reference numerals.
As shown in the figure, the input terminals 1 and 2 are connected to the exchange OS via the subscriber line SL. Then, for the exchange OS, first turn on the D relay and the B relay (not shown) of the control circuit CC,
When the low resistance loop (direct current) Rl is closed (transmitted) to the exchange OS and then dial pulses are transmitted, the D, A'relays (not shown) in the control circuit CC are turned off (Fig. 1). Then, the B relay is turned ON / OFF, and the resistance loop of the resistance R B and the high resistance loop are alternately sent. In that case, the primary side of the transformer T is opened when sending out the high resistance loop, and the signal return from the amplifier AMP1 side to the amplifier AMP2 becomes large, but since the D, A'relay is turned off, the selection signal decoder
A logical product (AND) circuit of the output of DEC and D relay drive signal R DV or CK and D relay drive signal R DV is provided.
R DV is set to "O" and the selection signal Sync or CK of the codec CODEC
Therefore, the digital signal after the codec CODEC is not output. Therefore, the generation of ringing noise can be suppressed. When the codec CODEC with the power down mode by the selection signal Sync is used, the selection signal Sync is created by the logical product (AND condition) of the relay drive signal R DV and the output of the circuit selection signal decoder DEC. Therefore, when the D relay is not operating (standby), the power of the codec CODEC can be reduced and the power consumption during standby can be reduced.
（発明の効果） 以上詳細に説明したように、本発明は符号復号器に供給
する選択信号をリレーの駆動信号との論理積をとる回路
を設けることによりダイヤルパルス送出時において、高
抵抗ループ送出時の鳴音を抑制することができ、従来の
ようにトランスの１次側にマッチングインピーダンスを
設ける必要がなく、それに必要な抵抗、リレー等の部品
点数が減少し、小型化できる効果がある。(Effect of the Invention) As described in detail above, the present invention provides a high resistance loop transmission at the time of dial pulse transmission by providing a circuit that logically ANDs the selection signal supplied to the code decoder with the drive signal of the relay. There is an effect that it is possible to suppress the ringing sound at the time, it is not necessary to provide a matching impedance on the primary side of the transformer as in the conventional case, the number of parts such as resistors and relays required for the matching impedance is reduced, and the size can be reduced.
第１図は本発明回線インターフェース回路の一実施例を
示す図、第２図は従来の回路図を示す図、第３図は本発
明回線インターフェースの一実施例を示す図である。 OS……交換機、SL……加入者線路、RD……着信検出回
路、CODEC……符号復号器、CC……制御回路、DEC……回
路選択信号用デコーダ、Rl……交流高抵抗・直流低抵抗
回路、BNW……整合インピーダンス。FIG. 1 is a diagram showing an embodiment of the line interface circuit of the present invention, FIG. 2 is a diagram showing a conventional circuit diagram, and FIG. 3 is a diagram showing an embodiment of the line interface of the present invention. OS: Exchange, SL: Subscriber line, RD: Call detection circuit, CODEC: Code decoder, CC: Control circuit, DEC: Circuit selection signal decoder, Rl: AC high resistance / DC low Resistor circuit, BNW ... Matching impedance.
Claims (1)
れ、交流高抵抗・直流低抵抗回路と、ダイヤルパルス信
号送信回路と、２線−４線交換ハイブリッドトランス
と、レベル調整用の増幅器と、アナログ／デジタル交換
用の符号復号器と、制御回路とからなる回線インターフ
ェース回路において、 ダイヤルパルス送出中および回線待機中に復旧するリレ
ーを設け、該リレー動作時は前記交流高抵抗・直流低抵
抗回路を、また、該リレー復旧時は抵抗を加入者線路間
に接続できるように該リレー接点を挿入し、回線インタ
ーフェース回路選択信号と、前記リレーの駆動信号との
論理積条件の信号で前記符号復号器のSYNC信号を抑制す
ることにより、該符号復号器をパワーダウンモードにし
て出力信号を停止させ、鳴音の発生ルートを切断して、
ダイヤルパルス送出中に発生する鳴音を抑えるととも
に、回線待機中および、ダイヤルパルス送出中の消費電
力を軽減することを特徴とする回線インターフェース回
路。1. An AC high resistance / DC low resistance circuit, a dial pulse signal transmission circuit, a 2-wire to 4-wire exchange hybrid transformer, and a level adjusting circuit, which are connected to a switch through a 2-wire subscriber line. A line interface circuit consisting of an amplifier, an analog / digital exchange code decoder, and a control circuit is provided with a relay that recovers during dial pulse transmission and line standby, and the AC high resistance / DC A low resistance circuit, and the relay contact is inserted so that a resistor can be connected between the subscriber lines when the relay is restored, and a signal of a logical product condition of the line interface circuit selection signal and the drive signal of the relay is used. By suppressing the SYNC signal of the encoder / decoder, the encoder / decoder is put into the power-down mode to stop the output signal and disconnect the sound generation route.
A line interface circuit that suppresses ringing noise generated during dial pulse transmission and reduces power consumption during line standby and during dial pulse transmission.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59221915A JPH0697794B2 (en) | 1984-10-24 | 1984-10-24 | Line interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59221915A JPH0697794B2 (en) | 1984-10-24 | 1984-10-24 | Line interface circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61101191A JPS61101191A (en) | 1986-05-20 |
| JPH0697794B2 true JPH0697794B2 (en) | 1994-11-30 |
Family
ID=16774150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59221915A Expired - Lifetime JPH0697794B2 (en) | 1984-10-24 | 1984-10-24 | Line interface circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0697794B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5469906A (en) * | 1977-11-15 | 1979-06-05 | Nippon Telegr & Teleph Corp <Ntt> | Analog-to-digital converter circuit |
-
1984
- 1984-10-24 JP JP59221915A patent/JPH0697794B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5469906A (en) * | 1977-11-15 | 1979-06-05 | Nippon Telegr & Teleph Corp <Ntt> | Analog-to-digital converter circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61101191A (en) | 1986-05-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |