CA1054276A - Telephone circuit to eliminate use of a hold button - Google Patents
Telephone circuit to eliminate use of a hold buttonInfo
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- CA1054276A CA1054276A CA262,639A CA262639A CA1054276A CA 1054276 A CA1054276 A CA 1054276A CA 262639 A CA262639 A CA 262639A CA 1054276 A CA1054276 A CA 1054276A
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Abstract
ABSTRACT OF THE DISCLOSURE
A circuit arrangement to enable one party to have a two-way con-versation simultaneously with an outside party and an internal party.
The circuit arrangement includes circuitry so that the outside party cannot hear anything that is said by the internal party or vice versa.
Thus, the one party has the ability to talk to both the outside and the internal party without them hearing each other while using one subset and not putting anyone on hold. In addition, the circuitry includes a button which when depressed enables all three parties to be put onto a two-way conference.
A circuit arrangement to enable one party to have a two-way con-versation simultaneously with an outside party and an internal party.
The circuit arrangement includes circuitry so that the outside party cannot hear anything that is said by the internal party or vice versa.
Thus, the one party has the ability to talk to both the outside and the internal party without them hearing each other while using one subset and not putting anyone on hold. In addition, the circuitry includes a button which when depressed enables all three parties to be put onto a two-way conference.
Description
1054Z76 R. E . HERLACHER - lX
Background of the Invention This invention relates to telephone systems and more particularly to telephone circuits employing key telephone systems.
Existing key telephone systems having the capabilities for outside as well as internal communications require the use of two subsets or placing the outside call on hold while the internal call is conducted. In either case, this requires depressinq many buttons or manipulating several subsets to perform the desired operation.
There are several shortcomings to the above operating procedures. If the two subset approach is used, there is always the inconvenience of holding the two subsets. If the single subset is used in conjunction with the hold button, the outside party who is calling for some type of assistance does not have the assurance that anything is being done to solve his problems since he does not hear any part of the conversation that transpires internally.
Summary of the Invention .: :
An object of the present invention is to provide a tele-phone circuit at the subset which will overcome the afore-mentioned difficulties.
The aforementioned difficulties are overcome in that with the new telephone circuit neither two subsets or the holding 25 button need to be used. When this new telephone circuit is used, one party using the new telephone circuit using one handset is able to have a two-way conversation with the outside party as well as with th~ internal party. At the same time, the outside party cannot hear anything that is said by 30 the internal party or vice versa. In short, this gives
Background of the Invention This invention relates to telephone systems and more particularly to telephone circuits employing key telephone systems.
Existing key telephone systems having the capabilities for outside as well as internal communications require the use of two subsets or placing the outside call on hold while the internal call is conducted. In either case, this requires depressinq many buttons or manipulating several subsets to perform the desired operation.
There are several shortcomings to the above operating procedures. If the two subset approach is used, there is always the inconvenience of holding the two subsets. If the single subset is used in conjunction with the hold button, the outside party who is calling for some type of assistance does not have the assurance that anything is being done to solve his problems since he does not hear any part of the conversation that transpires internally.
Summary of the Invention .: :
An object of the present invention is to provide a tele-phone circuit at the subset which will overcome the afore-mentioned difficulties.
The aforementioned difficulties are overcome in that with the new telephone circuit neither two subsets or the holding 25 button need to be used. When this new telephone circuit is used, one party using the new telephone circuit using one handset is able to have a two-way conversation with the outside party as well as with th~ internal party. At the same time, the outside party cannot hear anything that is said by 30 the internal party or vice versa. In short, this gives
- 2 -~054Z76 the party employing the new telephone circuit the ability to talk to both parties without them hearing each other while using one handset and not putting anyone on hold. As an additional benefit, by depressing a designated button all three parties can be put into a two-way con-ference.
A feature of the present invention is the provision of a telephone circuit to eliminate use of a hold button comprising: a subset having a receiver and a transmitter for use by one party; a plurality of central office lines connected to outside parties; a plurality of internal lines connected to internal parties; first means to couple the receiver and the transmitter to a selected one of the central office lines to enable a first two-way conversation between the one party and a selected one of the outside parties; second means to couple the receiver and the trans-mitter to a selected one of the internal lines to enable a second two-way conversation between the one party and a selected one of the internal parties; and third means coupled between the first means and the second means, the third means having a first state to enable the first and second conversations to be carried on simultaneously and to prevent the selected one of the outside parties and the selected one of the internal parties from hearing each other and a second state to selectively enable the one party, the selected one of the outside parties and the selected one of the internal parties to be placed in a two-way conference.
Brief Descrip~on of the Drawing Above-mentioned and other features and objects of this invention will become more apparent by reference to the following description taken in conjunction with the accompanying drawing, in which:
1054Z76 R. E. HERLACHER - lX
Fig. 1 is a block diagram of the telephone circuit in accordance with the principles of the present invention;
Fig. 2 is a schematic diagram partially in block form of the sub-set receiver and transmitter and their associated isolation amplifiers of Fig. l;
Fig. 3 is a schematic diagram partially in block form of the patch unit of Fig. l; and Fig. 4 is a schematic diagram partially in block form of the telephone impedance matching networks NTWl and NTW2 and their interconnection with patch unit 9 of Fig. 1.
rDescription of the Preferred Embodiment Referring to Fig. 1, when a call comes in from outside on the CO
(Central Office) lines, the signal is connected to a standard telephone impedance matching network NTWl by depressing the proper one of flashing buttons A-J of the CO line selector switch Sl. Network NTWl contains all of the components necessary to match the impedances of the transmitter and receiver to the selected CO lines. The received signal at the receive part of network NTWl passes through isolation amplifier A2 to the subset receiver REC. The slgnal from the subset transmitter TRANS passes through isolatîon amplifier Al back to net-work NTWl, thus completing the connection to an outside or CO line.
If at this same time it is desired to also talk to an internal party, the desired internal line is selected by depressing the appropriate one of buttons A-J on internal line selector switch S2. The transmitter signal of the subset goes through the isolation amplifier A4 to the telephone impedance matching network NTW2 and then through internal line selector switch S2 to the selected internal line. Network NTW2 1054Z76 R. E. HERLACHER - lX
contains all the components necessary to match the impedances of the subset transmitter and receiver to the selected internal line. The received signal comes in through select switch S2 through network NTW2 and through isolation amplifier A3 to the subset receiver REC.
In this condition, the party employing the subset can hold a two-way conversation with both the external and internal parties, but the in-ternal party cannot hear the outside party and vice versa.
If it is needed to patch all three parties together for a conference, this can be done by depressing a patch button and all parties are con-nected together via the patch unit 9.
Referring to Fig. 2, the transmit circuitry of the new telephone circuit will be described. Resistors R20 and R21 and capacitors C14 and C15 provide a filtered plus and minus 14 volts to power the opera-tional amplifiers 10, 11 and IC2. Resistors R10 and Rll provide the DC (direct current) current to operate the subset transmitter TRANS.
Capacitors C8 and C9 are used to couple the signal into operational amplifier 10. Resistors R12, R13, R14 and R15 set the gain and input impedance of amplifier 10. Amplifier 10 is an operational amplifier used with differential inputs in order to reduce the amplification of a common mode signal. Capacitor C7 couples the transmit signal to the matching transformer Tl. Transformer Tl and capacitor C6 provide isolation and couple the transmitter signal into the CO network NTWl.
The circuit including capacitors C10-C13, resistors R16-R19, operational amplifier 11 and transformer T2 perform the same functlon as above, but 2 5 for an internal call .
The receive circuitry of the new telephone circuit is shown in Fig. 2 and includes resistors R1 and R2 to provide a load on the telephone ~054276 R. E. HERII~CHER - lX
networks NTWl and NTW2, respectively. Varistors Vl and V2 provide voltage transient protection for the input of ampllfier IC2. Capacitors Cl, C2, C3 and C4 couple the received signal from the networks NTWl and NTW2 into amplifier IC2. Resistors R3, R4, R7 and R8 set the gain and input impedance for the received signal from the network NTWl.
Resistors R5, R6, R7 and R8 set the gain and input impedance for the received signal from the network NTW2. Amplifier IC2 is an opera-tional amplifier used as a summing amplifier with differential inputs.
The high input impedance of amplifier IC2 prevents any cross-talk be-tween the two input signals. Capacitor C5 couples the received signal through the impedance matching resistor R9 to the subset receiver REC, Referring to Fig. 3 there Is illustrated therein a schematic diagram partially in block form of the patch unit 9 of Fig. 1. A CMOS (clad metal oxide semiconductor) D-type flip flop IC3 is used to convert c o l~f ~ r ~ ~) c c ,4 15 the momentary action/switch S5 into an alternate action switch to con-trol patch relay RLl. Resistor R23 and capacitor C17 provide an RC
~ circuit to debounce the momentary switch S5. Anytime a positive go-; ing pulse is present at pin 3, the clock input of flip flop IC3, the output at pins 6 and 2, Q and D terminals, respectively, will change state.
Resistor R22 holds pins 1 and 4 at I0 volts DC when switches S3 and S4 are both open. When either switches S3 or S4 are closed, the output signal of Q and D terminals go to binary "0" . Switches S3 and S4 are located on the ends of line selector switches Sl and S2 of Fig. 1, re-spectively, and are closed when all buttons are up and are opened when at least one button is depressed. Diode Dl and capacitor C16 suppress any spikes present golng lnto switchlng transistor TRl. Reslstor R24 limits current into transistor TRl. Transistor TRl switches relay RLl 1054276 R, E, HERLACHER - lX
and the patch lamp on when the output of flip flop IC3 is high, a blnary "1", and off when the output of flip flop IC3 is low, a binary "0". Diode D2 provides spike protection. Reslstor R25 reduces the 28 volts DC to 10 volts DC to illuminate the patch lamp. Capacitors C18 and Cl9 are used to couple the tip and ring conductors of the outside and interna~ lines together when relay RLl is activated. Capacitors C20 and C21 provide DC isolation for network NTW2. Resistor R27 provides a load for the internal line. Reslstors R26, capacitor C22 and zener dlode D3 provide a regulated 10 volts DC to flip flop IC3 from the 28 volts DC supply.
Referring to Fig. 4 there is illustrated a schematic diagram of an implementation of networks NTWl and NTW2 and their interconnection to patch unit 9. Networks NTWl and NTW2 provide a two wire to four wire conversion by connecting the tip (T) conductor and the ring (R) conductor of switches Sl and S2, respectively, to the transmit and receive amplifiers of Fig. 2. The terminals labelled Ll, R, L2 arid B
of network NTWl are connected to similarly labelled terminals of Fig-.
2 labelled TO NETWORK NTWl and the terminals labelled Ll`, R', L2 and B of network NTW2 are connected to similarly labelled terminals of Fig. 2 labelled TO NETWORK NTW2.
Netwark NTWl includes four coils TAl, TA2, TB and TC of a transformer. The arrows associated with each of the coils indicates the direction of winding of its associated coil. Received speech currents pass via coils TAl, TB and TA2, each of which produces by induction an additive voltage ln coll TC. The recelved currents also produce a voltage across resistor R28 that opposes and is almost equal to that produced by the induced voltages in coil TC. There is, 1054Z76 R . E . HERLAC HER - lX
therefore, very little power loss in resistor R31 and varistor V3 and maximum power is present ln the receiver connected to termlnals Ll and R. The low impedance of the transmitter connected to terminals L2 and B
is matched to the loop by the turns ratio of coil TB to coils TAl and TA2.
Current variations due to the transmitter are in opposite phase in coils TA and TB. The induced voltages in coil TC are also in opposite phase and the resultant voltage is opposed by the voltage produced across resistor R28. The net effect is that very small signals are produced in the receiver due to transmitter current changes and sidetone is very low. Also, since there is little power loss in the receiver, maximum transmitting levels are attained. Both varistors V3 and V4 contribute to this condition by automatically compensating for various loop conditions to provide close matching of the loop impedance and the balancing network impedance with the transmitter circuit.
Resistor R31 and capacitor C23 provide a filter network to sup-press high frequency signal components of the dial pulses which might otherwise be radiated from the telephone line and cause local inter-ference with broadcast radio reception.
The implementation and operation of network NTW2 is identical with that of network NTWl except that the resistor and varistor series circuit and the capacitor associated therewith is replaced by resistor R29. This is possible since in the internal network NTW1 there is no DC present therein.
As can be seen from Fig. 4 patch unit 9 of Fig. 3 has a first state with switch arms SAl and SA2 in the positlon shown. In this first state patch unit 3 connects the internal lines to network NTW2 and prevents the internal lines to be coupled to the external lines. As a 1054Z76 R. E. HERI~CHER - lX
result the one party has the ability to talk to both the selected outside and selected inside party without them hearing each other. When switch S5 is depressed patch unit 9 assumes a second state. In this second state relay RLl is energized and switch arms SAl and SA2 are moved into their other position to contact switch contacts SCl and SC2. This results in the selected internal line being coupled directly to capacitors C18 and Cl9 and hence to the input of network NTWl. With ~his connection network NTW2 is bypassed, but network NTWl and its associated circuits of Fig. 2 are still in the circuit and operative. The two-way conference between the three parties is provided by network NTWl which is still in operation. Network NTWl passes the speech of the three parties in both directions and thereby establishes a two-way conference between all three parties.
During the patch mode or second state of patch unit 9 it is not required that both networks NTWl and NTW2 be in use since there is no longer isolation between the CO and internal lines.
The values and types of the components employed in Figs. 2,
A feature of the present invention is the provision of a telephone circuit to eliminate use of a hold button comprising: a subset having a receiver and a transmitter for use by one party; a plurality of central office lines connected to outside parties; a plurality of internal lines connected to internal parties; first means to couple the receiver and the transmitter to a selected one of the central office lines to enable a first two-way conversation between the one party and a selected one of the outside parties; second means to couple the receiver and the trans-mitter to a selected one of the internal lines to enable a second two-way conversation between the one party and a selected one of the internal parties; and third means coupled between the first means and the second means, the third means having a first state to enable the first and second conversations to be carried on simultaneously and to prevent the selected one of the outside parties and the selected one of the internal parties from hearing each other and a second state to selectively enable the one party, the selected one of the outside parties and the selected one of the internal parties to be placed in a two-way conference.
Brief Descrip~on of the Drawing Above-mentioned and other features and objects of this invention will become more apparent by reference to the following description taken in conjunction with the accompanying drawing, in which:
1054Z76 R. E. HERLACHER - lX
Fig. 1 is a block diagram of the telephone circuit in accordance with the principles of the present invention;
Fig. 2 is a schematic diagram partially in block form of the sub-set receiver and transmitter and their associated isolation amplifiers of Fig. l;
Fig. 3 is a schematic diagram partially in block form of the patch unit of Fig. l; and Fig. 4 is a schematic diagram partially in block form of the telephone impedance matching networks NTWl and NTW2 and their interconnection with patch unit 9 of Fig. 1.
rDescription of the Preferred Embodiment Referring to Fig. 1, when a call comes in from outside on the CO
(Central Office) lines, the signal is connected to a standard telephone impedance matching network NTWl by depressing the proper one of flashing buttons A-J of the CO line selector switch Sl. Network NTWl contains all of the components necessary to match the impedances of the transmitter and receiver to the selected CO lines. The received signal at the receive part of network NTWl passes through isolation amplifier A2 to the subset receiver REC. The slgnal from the subset transmitter TRANS passes through isolatîon amplifier Al back to net-work NTWl, thus completing the connection to an outside or CO line.
If at this same time it is desired to also talk to an internal party, the desired internal line is selected by depressing the appropriate one of buttons A-J on internal line selector switch S2. The transmitter signal of the subset goes through the isolation amplifier A4 to the telephone impedance matching network NTW2 and then through internal line selector switch S2 to the selected internal line. Network NTW2 1054Z76 R. E. HERLACHER - lX
contains all the components necessary to match the impedances of the subset transmitter and receiver to the selected internal line. The received signal comes in through select switch S2 through network NTW2 and through isolation amplifier A3 to the subset receiver REC.
In this condition, the party employing the subset can hold a two-way conversation with both the external and internal parties, but the in-ternal party cannot hear the outside party and vice versa.
If it is needed to patch all three parties together for a conference, this can be done by depressing a patch button and all parties are con-nected together via the patch unit 9.
Referring to Fig. 2, the transmit circuitry of the new telephone circuit will be described. Resistors R20 and R21 and capacitors C14 and C15 provide a filtered plus and minus 14 volts to power the opera-tional amplifiers 10, 11 and IC2. Resistors R10 and Rll provide the DC (direct current) current to operate the subset transmitter TRANS.
Capacitors C8 and C9 are used to couple the signal into operational amplifier 10. Resistors R12, R13, R14 and R15 set the gain and input impedance of amplifier 10. Amplifier 10 is an operational amplifier used with differential inputs in order to reduce the amplification of a common mode signal. Capacitor C7 couples the transmit signal to the matching transformer Tl. Transformer Tl and capacitor C6 provide isolation and couple the transmitter signal into the CO network NTWl.
The circuit including capacitors C10-C13, resistors R16-R19, operational amplifier 11 and transformer T2 perform the same functlon as above, but 2 5 for an internal call .
The receive circuitry of the new telephone circuit is shown in Fig. 2 and includes resistors R1 and R2 to provide a load on the telephone ~054276 R. E. HERII~CHER - lX
networks NTWl and NTW2, respectively. Varistors Vl and V2 provide voltage transient protection for the input of ampllfier IC2. Capacitors Cl, C2, C3 and C4 couple the received signal from the networks NTWl and NTW2 into amplifier IC2. Resistors R3, R4, R7 and R8 set the gain and input impedance for the received signal from the network NTWl.
Resistors R5, R6, R7 and R8 set the gain and input impedance for the received signal from the network NTW2. Amplifier IC2 is an opera-tional amplifier used as a summing amplifier with differential inputs.
The high input impedance of amplifier IC2 prevents any cross-talk be-tween the two input signals. Capacitor C5 couples the received signal through the impedance matching resistor R9 to the subset receiver REC, Referring to Fig. 3 there Is illustrated therein a schematic diagram partially in block form of the patch unit 9 of Fig. 1. A CMOS (clad metal oxide semiconductor) D-type flip flop IC3 is used to convert c o l~f ~ r ~ ~) c c ,4 15 the momentary action/switch S5 into an alternate action switch to con-trol patch relay RLl. Resistor R23 and capacitor C17 provide an RC
~ circuit to debounce the momentary switch S5. Anytime a positive go-; ing pulse is present at pin 3, the clock input of flip flop IC3, the output at pins 6 and 2, Q and D terminals, respectively, will change state.
Resistor R22 holds pins 1 and 4 at I0 volts DC when switches S3 and S4 are both open. When either switches S3 or S4 are closed, the output signal of Q and D terminals go to binary "0" . Switches S3 and S4 are located on the ends of line selector switches Sl and S2 of Fig. 1, re-spectively, and are closed when all buttons are up and are opened when at least one button is depressed. Diode Dl and capacitor C16 suppress any spikes present golng lnto switchlng transistor TRl. Reslstor R24 limits current into transistor TRl. Transistor TRl switches relay RLl 1054276 R, E, HERLACHER - lX
and the patch lamp on when the output of flip flop IC3 is high, a blnary "1", and off when the output of flip flop IC3 is low, a binary "0". Diode D2 provides spike protection. Reslstor R25 reduces the 28 volts DC to 10 volts DC to illuminate the patch lamp. Capacitors C18 and Cl9 are used to couple the tip and ring conductors of the outside and interna~ lines together when relay RLl is activated. Capacitors C20 and C21 provide DC isolation for network NTW2. Resistor R27 provides a load for the internal line. Reslstors R26, capacitor C22 and zener dlode D3 provide a regulated 10 volts DC to flip flop IC3 from the 28 volts DC supply.
Referring to Fig. 4 there is illustrated a schematic diagram of an implementation of networks NTWl and NTW2 and their interconnection to patch unit 9. Networks NTWl and NTW2 provide a two wire to four wire conversion by connecting the tip (T) conductor and the ring (R) conductor of switches Sl and S2, respectively, to the transmit and receive amplifiers of Fig. 2. The terminals labelled Ll, R, L2 arid B
of network NTWl are connected to similarly labelled terminals of Fig-.
2 labelled TO NETWORK NTWl and the terminals labelled Ll`, R', L2 and B of network NTW2 are connected to similarly labelled terminals of Fig. 2 labelled TO NETWORK NTW2.
Netwark NTWl includes four coils TAl, TA2, TB and TC of a transformer. The arrows associated with each of the coils indicates the direction of winding of its associated coil. Received speech currents pass via coils TAl, TB and TA2, each of which produces by induction an additive voltage ln coll TC. The recelved currents also produce a voltage across resistor R28 that opposes and is almost equal to that produced by the induced voltages in coil TC. There is, 1054Z76 R . E . HERLAC HER - lX
therefore, very little power loss in resistor R31 and varistor V3 and maximum power is present ln the receiver connected to termlnals Ll and R. The low impedance of the transmitter connected to terminals L2 and B
is matched to the loop by the turns ratio of coil TB to coils TAl and TA2.
Current variations due to the transmitter are in opposite phase in coils TA and TB. The induced voltages in coil TC are also in opposite phase and the resultant voltage is opposed by the voltage produced across resistor R28. The net effect is that very small signals are produced in the receiver due to transmitter current changes and sidetone is very low. Also, since there is little power loss in the receiver, maximum transmitting levels are attained. Both varistors V3 and V4 contribute to this condition by automatically compensating for various loop conditions to provide close matching of the loop impedance and the balancing network impedance with the transmitter circuit.
Resistor R31 and capacitor C23 provide a filter network to sup-press high frequency signal components of the dial pulses which might otherwise be radiated from the telephone line and cause local inter-ference with broadcast radio reception.
The implementation and operation of network NTW2 is identical with that of network NTWl except that the resistor and varistor series circuit and the capacitor associated therewith is replaced by resistor R29. This is possible since in the internal network NTW1 there is no DC present therein.
As can be seen from Fig. 4 patch unit 9 of Fig. 3 has a first state with switch arms SAl and SA2 in the positlon shown. In this first state patch unit 3 connects the internal lines to network NTW2 and prevents the internal lines to be coupled to the external lines. As a 1054Z76 R. E. HERI~CHER - lX
result the one party has the ability to talk to both the selected outside and selected inside party without them hearing each other. When switch S5 is depressed patch unit 9 assumes a second state. In this second state relay RLl is energized and switch arms SAl and SA2 are moved into their other position to contact switch contacts SCl and SC2. This results in the selected internal line being coupled directly to capacitors C18 and Cl9 and hence to the input of network NTWl. With ~his connection network NTW2 is bypassed, but network NTWl and its associated circuits of Fig. 2 are still in the circuit and operative. The two-way conference between the three parties is provided by network NTWl which is still in operation. Network NTWl passes the speech of the three parties in both directions and thereby establishes a two-way conference between all three parties.
During the patch mode or second state of patch unit 9 it is not required that both networks NTWl and NTW2 be in use since there is no longer isolation between the CO and internal lines.
The values and types of the components employed in Figs. 2,
3 and 4 of a successful reduction to practice are set forth herein-below .
R. E. HERLACHER - lX
~os4276 Rl & R2 150 ohms, 1/2 watt resistor R3, R4, R5, R6 150K ohms, 1/2 watt resistor R7 & R8 220K ohms, 1/2 watt resistor R9 100 ohms, 1/2 watt resistor R10, Rll, R20, R21 1.5K ohms, 1/2 watt resistor R12, R13, R17, R18 47K ohms, 1/2 watt resistor R14, R15, R16, Rl9 lM ohms, 1/2 watt resistor R22 lOK ohms, 1/2 watt resistor R23, R24 4.7K ohms, 1/2 watt resistor R25 390 ohms, 1/2 watt resistor R26 6.8K ohms, 1/2 watt resistor R27, R29 680 ohms, 1 watt resistor R28, R30 68 ohms, 1/2 watt resistor R31 180 ohms, 1/2 watt resistor Cl, C2, C3, C4, C8, C9, C10, Cll 0.1 ufd, lOOv capacitor C5, C6, C7, C12, C13, C16, C20, C21, C25, C27 2.2 mfd, 64v capacitor C14, C15 32 ufd, 50v capacitor C17 1 ufd 50v capacitor C18, Cl9 10 ufd, N.P. capacitor C22 6.4 mfd, 25v capacitor C24, C26 0.47 mfd, 64v capacitor Dl, D2 GR 22 diode D3 lOv zener diode ; Tl, T2 Transformer 30K ohms secondary, 200 ohms primary Vl, V2, V3, V4, V5 Varistor ICl, IC2 LM1458 integrated circuit IC3 M M74C74 dual D flip flop integrated circuit TRl 2N3568 NPN transistor RLl 2PDT relay, 24 volts TAl, TA2, TB, TC coils of a transformer, network NTWl TAl', TA2', TB', TC' coils of a transformer, network NTW2 While I have described above the principles of my invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of my invention as set forth in the objects thereof and in the accompanying claims.
ACH:vm/jn
R. E. HERLACHER - lX
~os4276 Rl & R2 150 ohms, 1/2 watt resistor R3, R4, R5, R6 150K ohms, 1/2 watt resistor R7 & R8 220K ohms, 1/2 watt resistor R9 100 ohms, 1/2 watt resistor R10, Rll, R20, R21 1.5K ohms, 1/2 watt resistor R12, R13, R17, R18 47K ohms, 1/2 watt resistor R14, R15, R16, Rl9 lM ohms, 1/2 watt resistor R22 lOK ohms, 1/2 watt resistor R23, R24 4.7K ohms, 1/2 watt resistor R25 390 ohms, 1/2 watt resistor R26 6.8K ohms, 1/2 watt resistor R27, R29 680 ohms, 1 watt resistor R28, R30 68 ohms, 1/2 watt resistor R31 180 ohms, 1/2 watt resistor Cl, C2, C3, C4, C8, C9, C10, Cll 0.1 ufd, lOOv capacitor C5, C6, C7, C12, C13, C16, C20, C21, C25, C27 2.2 mfd, 64v capacitor C14, C15 32 ufd, 50v capacitor C17 1 ufd 50v capacitor C18, Cl9 10 ufd, N.P. capacitor C22 6.4 mfd, 25v capacitor C24, C26 0.47 mfd, 64v capacitor Dl, D2 GR 22 diode D3 lOv zener diode ; Tl, T2 Transformer 30K ohms secondary, 200 ohms primary Vl, V2, V3, V4, V5 Varistor ICl, IC2 LM1458 integrated circuit IC3 M M74C74 dual D flip flop integrated circuit TRl 2N3568 NPN transistor RLl 2PDT relay, 24 volts TAl, TA2, TB, TC coils of a transformer, network NTWl TAl', TA2', TB', TC' coils of a transformer, network NTW2 While I have described above the principles of my invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of my invention as set forth in the objects thereof and in the accompanying claims.
ACH:vm/jn
Claims (19)
1. A telephone circuit to eliminate use of a hold button comprising:
a subset having a receiver and a transmitter for use by one party;
a plurality of central office lines connected to outside parties;
a plurality of internal lines connected to internal parties;
first means to couple said received and said transmitter to a selected one of said central office lines to enable a first two-way conversation between said one party and a selected one of said outside parties;
second means to couple said receiver and said transmitter to a selected one of said internal lines to enable a second two-way conversation between said one party and a selected one of said internal parties; and third means coupled between said first means and said second means, said third means having a first state to enable said first and second conversations to be carried on simultaneously and to prevent said selected one of said outside parties and said selected one of said internal parties from hearing each other and a second state to selectively enable said one party, said selected one of said outside parties and said selected one of said internal parties to be placed in a two-way conference.
a subset having a receiver and a transmitter for use by one party;
a plurality of central office lines connected to outside parties;
a plurality of internal lines connected to internal parties;
first means to couple said received and said transmitter to a selected one of said central office lines to enable a first two-way conversation between said one party and a selected one of said outside parties;
second means to couple said receiver and said transmitter to a selected one of said internal lines to enable a second two-way conversation between said one party and a selected one of said internal parties; and third means coupled between said first means and said second means, said third means having a first state to enable said first and second conversations to be carried on simultaneously and to prevent said selected one of said outside parties and said selected one of said internal parties from hearing each other and a second state to selectively enable said one party, said selected one of said outside parties and said selected one of said internal parties to be placed in a two-way conference.
2. A circuit according to claim 1, wherein said first means includes a line selector switch coupled to said plurality of central office lines to enable selection of said selected one of said central office lines, an impedance matching network coupled to said line selector switch, a receiver isolation amplifier coupled between said impedance matching network and said receiver, and a transmitter isolation amplifier coupled between said impedance matching network and said transmitter.
3. A circuit according to claim 2, wherein said receiver isolation amplifier includes a first operational amplifier employed as a summing amplifier with differential inputs.
4. A circuit according to claim 3, wherein said transmitter isolation amplifier includes a second operational amplifier with differential inputs to reduce the amplification of a common mode signal.
5. A circuit according to claim 2, wherein said transmitter isolation amplifier includes an operational amplifier with differential inputs to reduce the amplification of a common mode signal.
6. A circuit according to claim 1, wherein said second means includes a line selector switch coupled to said plurality of internal lines to enable selection of said selected one of said internal lines, an impedance matching network coupled to said line selector switch through said third means, a receiver isolation amplifier coupled between said impedance matching network and said receiver, and a transmitter isolation amplifier coupled between said impedance matching network and said transmitter.
7. A circuit according to claim 6, wherein said receiver isolation amplifier includes a first operational amplifier employed as a summing amplifier with differential inputs.
8. A circuit according to claim 7, wherein said transmitter isolation amplifier includes a second operational amplifier with differential inputs to reduce the amplification of a common mode signal.
9. A circuit according to claim 6, wherein said transmitter isolation amplifier includes an operational amplifier with differential inputs to reduce the amplification of a common mode signal.
10. A circuit according to claim 1, wherein said third means includes a source of direct current voltage, a momentary action switch coupled to said source, a D-type flip flop having a D terminal, a Q terminal and a clock terminal, said clock terminal being coupled to said switch, and a relay coupled to said D and Q terminals, said relay interconnecting said selected one of said central office lines and said selected one of said internal office lines when the output signal of said D and Q terminals are high.
11. A circuit according to claim 1, wherein said first means includes a first line selector switch coupled to said plurality of central office lines to enable selection of said selected one of said central office lines, a first impedance matching network coupled to said first line selector switch, a first receiver isolation amplifier coupled between said first impedance matching network and said receiver, and a first transmitter isolation amplifier coupled between said first impedance matching network and said transmitter, and said second means includes a second line selector switch coupled to said plurality of internal lines to enable selection of said selected one of said internal lines, a second impedance matching network coupled to said second line selector switch through said third means, a second receiver isolation amplifier coupled between said second impedance matching network and said receiver, and a second transmitter isolation amplifier coupled between said second impedance matching network and said transmitter.
12. A circuit according to claim 11, wherein said first and second receiver isolation amplifiers include a common operational amplifier employed as a summing amplifier with differential inputs.
13. A circuit according to claim 12, wherein each of said first and second transmitter isolation amplifiers includes an operational amplifier with differential inputs to reduce the amplification of a common mode signal.
14. A circuit according to claim 11, wherein each of said first and second transmitter isolation amplifiers includes an operational amplifier with differential inputs to reduce the amplification of a common mode signal.
15. A circuit according to claim 11, wherein said third means is connected between the output of said first and second line selector switches and to the input of said second impedance matching network.
16. A circuit according to claim 15, wherein said third means includes a source of direct current voltage, a momentary action switch coupled to said source, a D-type flip flop having a D terminal, a Q terminal and a clock terminal, said clock terminal being coupled to said switch, and a relay coupled to said D and Q terminals, said relay interconnecting said selected one of said central office lines and said selected one of said internal office lines when the output signal of said D and Q
terminals are high.
terminals are high.
17. A circuit according to claim 16, wherein said first and second receiver isolation amplifiers include a common operational amplifier employed as a summing amplifier with differential inputs.
18. A circuit according to claim 17, wherein each of said first and second transmitter isolation amplifiers includes an operational amplifier with differential inputs to reduce the amplification of a common mode signal.
19. A circuit according to claim 16, wherein each of said first and second transmitter isolation amplifiers includes an operational amplifier with differential inputs to reduce the amplification of a common mode signal.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/622,287 US4004107A (en) | 1975-02-11 | 1975-10-10 | Telephone circuit to eliminate use of a hold button |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1054276A true CA1054276A (en) | 1979-05-08 |
Family
ID=24493635
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA262,639A Expired CA1054276A (en) | 1975-10-10 | 1976-10-04 | Telephone circuit to eliminate use of a hold button |
Country Status (2)
| Country | Link |
|---|---|
| BR (1) | BR7606759A (en) |
| CA (1) | CA1054276A (en) |
-
1976
- 1976-10-04 CA CA262,639A patent/CA1054276A/en not_active Expired
- 1976-10-08 BR BR7606759A patent/BR7606759A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| BR7606759A (en) | 1977-08-30 |
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