JPH0697291A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device provided with a contact hole which is capable of connecting a lower wiring to an upper wiring in a self-aligned manner, suitable for micronization, restrained from increasing in contact resistance, free from a junction leakage current, and enhanced in wiring step coverage and reliability even if it is of high aspect ratio. CONSTITUTION:A conductive film 3 is selectively removed using a first resist pattern 4 formed on it as a mask, a part of the first resist pattern 4 is removed, a second resist pattern 5 is formed on the center of a part which is to serve as a contact hole forming region 10, the conductive film 3 is partially removed using the second resist pattern 5 as a mask for the formation of a lower wiring 6 and a projection 7, and an upper wiring 9 connected to the conductive film 3 is formed thereon through the intermediary of an interlayer insulating film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an upper layer wiring connected to a lower layer wiring.

[0002]

2. Description of the Related Art Conventionally, LSI (Large Scale Integration)
ated circuit) to achieve high integration and high density.
The device is being miniaturized. Due to the miniaturization of this device, MOS (Metal Oxide Semiconducto)
r) While the device has high performance and high speed, the influence of the resistance and capacitance of various parasitic elements on the circuit characteristics is increasing.

Since an LSI is a surface device, high integration is realized by reducing the planar size of the device. In order to increase the speed of the device, it is necessary to consider the parasitic resistance and the parasitic capacitance and to suppress the reduction of the vertical dimension (for example, thinning of the interlayer insulating film) as much as possible. However, suppressing the reduction in the vertical dimension of the device means increasing the aspect ratio of the contact hole for connecting the lower layer wiring and the upper layer wiring.
Therefore, there is a problem that the step coverage of the wiring in the contact portion is deteriorated. Therefore, there has been a problem that wiring resistance is increased in the contact hole portion, electromigration or stress migration occurs, and the wiring is broken.

As a countermeasure for solving such a problem, Hazuki et al., "Symp.VLSI Tech., Digest.
of Technical Papers, p18 (1982) ”, the contact hole is formed by combining isotropic etching and anisotropic etching to form a lower portion formed substantially perpendicular to the semiconductor substrate. The present invention provides a contact hole including a contact hole and an upper contact hole having a round shape and an opening wider than a connecting portion.

Further, an interlayer insulating film having a reflow property is formed on the lower layer wiring, a contact hole is opened in the interlayer insulating film, and then the interlayer insulating film is reflowed so that the edge of the contact hole is smoothed. It is also known how to do it.
Furthermore, in recent years, G. C. Smith says "Proc. 3r
d Int. IEEE VLSI Multilevel Interconnection Confer
ence, p403 (1986) ”.
By the (Chemical Vapor Deposition) method, tungsten was deposited on the entire surface of the interlayer insulating film in which the contact holes were opened (referred to as "blanket CVD tungsten").
After that, a method (buried tungsten method) of forming a tungsten plug in the contact hole by etching back the tungsten layer is known. This method
It is very effective in improving the step coverage of the wiring in the contact hole portion and improving the reliability of the wiring, and has an advantage that a tungsten plug can be easily formed even in a contact hole having an aspect ratio of 1 or more. Have

[0006]

However, in the conventional example in which the tungsten plug is formed in the contact hole, WF ₆ (tungsten fluoride) used in the blanket CVD tungsten growth process adversely affects the semiconductor substrate. There is a problem that the semiconductor substrate is damaged.

Therefore, in order to prevent the occurrence of this damage, it is essential to form an adhesion layer made of, for example, titanium nitride on the inner surface of the contact hole before growing the blanket CVD tungsten. There is. However, since the adhesion layer is currently formed by the sputter deposition method, when the aspect ratio of the contact hole is 1.4 or more, it is formed at the bottom of the contact hole (interface with the semiconductor substrate) by sputter deposition. There is a problem that the film thickness of the adhesion layer becomes thin. Therefore, even if the tungsten plug is completely buried in the contact hole in which the adhesion layer is formed, there is a concern that a junction leak may occur or contact resistance may increase. Therefore, even if the tungsten plug is formed by the CVD method, there is a problem that the upper limit of the aspect ratio is determined by the limit of the adhesion layer formed by the sputter deposition method.

An object of the present invention is to solve such a problem, and it is possible to connect the lower layer wiring and the upper layer wiring in a self-aligning manner and to provide a contact hole having a high aspect ratio. Also, to provide a method for manufacturing a semiconductor device having contact holes suitable for further miniaturization, which suppresses occurrence of junction leak, increase in contact resistance, etc., and improves wiring step coverage and reliability. To aim.

[0009]

To achieve this object, the present invention has a contact hole in an interlayer insulating film on a lower layer wiring formed on a semiconductor substrate, and the lower layer wiring is provided through the contact hole. In a method of manufacturing a semiconductor device for forming an upper layer wiring connected to, a first step of depositing a conductive film on an insulating film on the semiconductor substrate, and forming the contact hole forming region on the conductive film. A second step of forming a first resist pattern in which a width of a portion is larger than a width of another portion, a third step of selectively removing the conductive film using the first resist pattern as a mask, and the selection After the selective removal, a part of the first resist pattern is removed, and a fourth step of forming a second resist pattern on the central portion of the contact hole formation region; and a mask of the second resist pattern. Then, a fifth step of removing a part of the conductive film, a sixth step of removing the second resist pattern and then forming an interlayer insulating film on the entire surface, and an etching back of the interlayer insulating film, Manufacturing a semiconductor device, including: a seventh step of exposing a part of the conductive film; and an eighth step of forming an upper layer wiring connected to the conductive film on the interlayer insulating film. It provides a method.

[0010]

According to the present invention, by forming a first resist pattern on the conductive film in which the width of the portion to be the contact hole forming region is larger than the width of the other portion, the first resist pattern is formed in a later step. When a part of the first resist pattern is removed, the resist can be left on the central portion of the contact hole forming region, whereby the second resist pattern can be easily formed.

Next, a part of the conductive film is removed by using the second resist pattern as a mask, so that the lower wiring and the portion where the second resist pattern is formed are removed from the lower wiring. It is possible to obtain a protruding formation portion. Here, this protruding formation portion corresponds to a burying layer for burying the inside of the contact hole opened in the interlayer insulating film formed on the lower layer wiring. Then, the protrusion forming portion (portion corresponding to the embedded layer)
Unlike the conventional method of filling contact holes, since the deposited conductive film is selectively removed and formed, the film thickness can be arbitrarily determined, and even if the aspect ratio is high, It is possible to perform highly reliable connection without lowering coverage or disconnection. Moreover, since the film thickness of the interlayer insulating film can be increased according to the film thickness of the protrusion forming portion, the inter-wiring capacitance can be reduced.

Further, since the protrusion forming portion can be formed in a self-aligning manner without performing a photo process for forming itself, it is possible to form the protrusion forming portion with high accuracy without mechanical alignment (alignment) deviation. You can Then, after removing the second resist pattern, an interlayer insulating film is formed on the entire surface and is etched back to expose a part of the conductive film, and then the conductive film and the conductive film are formed thereon. By forming the upper layer wiring to be connected, it is possible to form the upper layer wiring to be connected to the lower layer wiring via the conductive film formed to project.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment according to the present invention will be described with reference to the drawings. 1 to 6 are partial cross-sectional views showing a part of a manufacturing process of a semiconductor device according to an embodiment of the present invention, FIG. 7 is a partial plan view of FIG. 1, and FIG. 8 is a partial plan view of FIG. is there. In the process shown in FIG. 1, on the semiconductor substrate 1,
The conductive film 3 is deposited with a thickness of about 1 to 2 μm through the insulating film 2. In this example, an aluminum film was used as the conductive film 3. Next, a photoresist film is applied on the conductive film 3 and is patterned, and as shown in the plan view of FIG. 7, the width 11 of the portion corresponding to the contact hole forming region 10 is changed to another value. A first resist pattern 4 having a width greater than 12 is formed. Here, the width 11 is about 1.4 μm, and the width 12 is
It was set to about 1.0 μm.

Next, in the step shown in FIG. 2, the conductive film 3 is anisotropically etched by using the first resist pattern 4 obtained in the step shown in FIG. 1 as a mask to form the first resist pattern. The conductive film 3 other than the formation region 4 is removed. In this way, the shape of the first resist pattern 4 was transferred to the conductive film 3. Next, in a step shown in FIG. 3, taper etching is performed on the first resist pattern 4 so that etching proceeds from the end portion of the first resist pattern 4, and particularly as shown in the plan view of FIG.
A second resist pattern 5 is formed on the center of the contact hole formation region 10.

Next, in the step shown in FIG. 4, the second resist pattern 5 obtained in the step shown in FIG. 3 is used as a mask to form the conductive film 3 other than the area where the second resist pattern 5 is formed.
Anisotropic etching is performed until the film thickness becomes 0.5-1 μm. In this way, the lower layer wiring 6 made of the conductive film 3 and the protrusion forming portion 7 made of the conductive film 3 formed on the lower layer wiring 6 were formed. The protrusion forming portion 7 corresponds to a buried layer that fills the contact hole opened in the interlayer insulating film on the lower layer wiring 6 to be formed later. Here, since the conductive film 3 is deposited with a sufficiently thick film thickness in the step shown in FIG. 1, the lower layer wiring 5 and the protrusion forming portion 7 can be obtained from the conductive film 3 without any problem. Further, as described above, the protrusion forming portion 7 (that is, the portion corresponding to the buried layer filling the contact hole) is
Unlike the conventional method of filling a contact hole, since the deposited conductive film 3 is selectively removed and formed, even if the projection forming portion 7 is made thicker and a high aspect ratio is achieved, It is possible to perform highly reliable connection without lowering coverage or disconnection. Furthermore, since the film thickness of the interlayer insulating film 8 formed in a later step can be increased corresponding to the film thickness of the protrusion forming portion 7, the inter-wiring capacitance can be reduced.

Next, in the step shown in FIG. 5, after the second resist pattern 5 is removed, an interlayer insulating film 8 is formed on the entire surface of the insulating film, the lower layer wiring and the protrusion forming portion 7.
Next, in the step shown in FIG. 6, the interlayer insulating film 8 obtained in the step shown in FIG. 5 is etched back to expose the surface of the protrusion forming portion 7. Next, an aluminum film is deposited as a conductive film on the entire surface of the interlayer insulating film 8 and the exposed protruding portion 7 after the etching back, and the aluminum film is patterned to form the lower layer wiring 6 through the protruding portion 7. An upper layer wiring 9 connected to is formed.

After that, desired steps are performed to complete the semiconductor device. Although an aluminum film is deposited as the conductive film 3 in this embodiment, the present invention is not limited to this, and a conductive film made of another conductive material such as an aluminum alloy film, a refractory metal film, or a silicide film is formed. Of course, it is okay. In the process shown in FIG. 1, the thickness of the conductive film 3 is set to
Although the thickness is about 1 to 2 μm, the thickness of the conductive film 3 is not limited to this, and may be arbitrarily determined according to the desired film thickness of the lower layer wiring 6 and the desired film thickness of the protrusion forming portion 7.

In the step shown in FIG. 3, the first resist pattern 4 was tapered, but the present invention is not limited to this, and the second resist pattern 5 is formed on the central portion of the contact hole forming region 10. If it can be formed, other methods such as ashing may be performed. Further, in the process shown in FIG. 4, the film thickness of the lower layer wiring 6 is 0.5 to
Although the conductive film 3 was selectively etched to 1 μm, the thickness is not limited to this, and the film thickness of the lower layer wiring 6 and the protrusion forming portion 7 are not limited thereto.
The film thickness of may be determined as desired.

[0019]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the width of the contact hole forming region is larger than the width of the other region on the conductive film.
By forming the resist pattern of
When removing a part of the resist pattern of, the resist is left on the central portion of the contact hole forming region,
A second resist pattern can be formed. Next, by using the second resist pattern as a mask, a part of the conductive film is removed to fill the contact hole opened in the lower wiring and the interlayer insulating film formed on the lower wiring. It is possible to obtain a protrusion forming portion corresponding to the buried layer. Unlike the conventional method of burying in the contact hole, this protrusion forming portion is formed by selectively removing the deposited conductive film, so that it can be formed with an arbitrary film thickness and has a high aspect ratio. However, it is possible to perform highly reliable connection without deterioration of step coverage or disconnection. Moreover, since the film thickness of the interlayer insulating film can be increased according to the film thickness of the protrusion forming portion, the inter-wiring capacitance can be reduced. Furthermore, since the protrusion forming portion can be formed in a self-aligned manner without performing a photo process for forming itself, it can be formed with high precision without mechanical misalignment. As a result, the lower layer wiring and the upper layer wiring can be connected in a self-aligning manner, and even in the case of a contact hole having a high aspect ratio, it is possible to suppress the occurrence of junction leak, increase in contact resistance, and the like, and It is possible to provide a semiconductor device having a contact hole which is improved in step coverage and reliability and suitable for further miniaturization.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view showing a part of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a partial plan view of FIG.

FIG. 8 is a partial plan view of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3 Conductive film 4 First resist pattern 5 Second resist pattern 6 Lower layer wiring 7 Projection forming part 8 Interlayer insulating film 9 Upper layer wiring 10 Contact hole forming area 11 Width 12 Width

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, comprising a contact hole in an interlayer insulating film on a lower layer wiring formed on a semiconductor substrate, and forming an upper layer wiring connected to the lower layer wiring through the contact hole. A first step of depositing a conductive film on a semiconductor substrate via an insulating film; and a first resist pattern in which a width of a portion to be the contact hole forming region is larger than a width of another portion on the conductive film. And a third step of selectively removing the conductive film by using the first resist pattern as a mask, and after the selective removal, a part of the first resist pattern is removed. A fourth resist pattern is formed on the center of the contact hole forming region,
A step, a fifth step of removing a part of the conductive film using the second resist pattern as a mask, and a sixth step of forming an interlayer insulating film over the entire surface after removing the second resist pattern. A seventh step of etching back the interlayer insulating film to expose a part of the conductive film, and an eighth step of forming an upper layer wiring connected to the conductive film on the interlayer insulating film. A method of manufacturing a semiconductor device, comprising: