JPH0695959A - Information processor - Google Patents

Abstract

PURPOSE:To increase picture elements to be plotted and to improve plotting performance by controlling an address and writing/non-writing for each chip and collectively writing data by a flexible format. CONSTITUTION:A CPU 1 executes instructions and data stored in a main storage 2 and executes various processing. In the case of executing plotting processing, a plotting processing mechanism 3 is instructed from the CPU 1 of what is plotted. At the time of receiving the instruction, the mechanism 3 instructs an image memory control mechanisms 4 to access an image memory 5. Receiving the instruction, the mechanism 4 writes data in the memory 5. When data from the CPU 1 or the mechanism 3 are continuously written in an area to be written by one access to the memory 5, the writing of the data can be collected to one image memory writing cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention controls writing of drawing data to an image memory storing data of each pixel of a display screen of a computer system or an image memory in which image data to be printed on a printer is developed. In particular, when writing figures,
Alternatively, the present invention relates to an information processing device that speeds up the expansion speed to the image memory when the background has transparent characters.

[0002]

2. Description of the Related Art Generally, computer screen information (information for each pixel) stored in a memory (image memory) such as a frame memory storing image data is accessed once on the memory. Then, take out multiple pixels,
Can be drawn on the screen.

However, in a memory system in which the area of pixels that can be accessed on the memory is fixed in a vertically or horizontally long shape, even if many pixels can be accessed at one time, one memory area is used. If you draw a straight line or curve that is long in the direction perpendicular to the direction that can be accessed once and has a thin line width (a line or curve with a line thickness of 1 pixel or a few pixels), you can access it once. There is a problem that only pixels with a line width can be drawn, and the drawing speed is reduced.

As a means for solving this problem, an image memory is composed of a plurality of memory chips, each pixel is made to correspond to a different pixel, and each chip is given a different address, whereby a fixed size at an arbitrary position is obtained. There has been devised a method capable of accessing an integer pixel × integer pixel area, or a method capable of accessing an integer pixel × integer pixel area having a variable size but limited in position.

As a memory management system capable of accessing a fixed size integer pixel × integer pixel area at an arbitrary position, Japanese Patent Application Laid-Open No. 60-198652 “image storage device” is known.
Is mentioned.

As a method for accessing an area of integer pixels × integer pixels having a variable size, although there is a limitation in position, "COMPUTER GRAPHICS HARDWARE Image Generation a
nd Display ", p.148.

[0007]

According to the above-mentioned conventional technique, it is necessary to decide which access method should be performed according to which direction the line is long. Further, in a straight line or a curved line having a line width of about 1 pixel, there are still many pixels that can be accessed at the same time but are not drawn, and the drawing performance is low.

It is an object of the present invention to provide an information processing apparatus which does not need to determine a memory access method regardless of the direction of a line to be drawn.
It is another object of the present invention to provide an information processing device having a high drawing performance because many pixels can be simultaneously accessed and drawn even if a line or a curve having a line width of about 1 pixel is used.

[0009]

In order to achieve the above object, according to the present invention, there is provided an image data storage device which is composed of a plurality of memory chips which respectively store information of different pixels on an image. In an information processing apparatus comprising an image memory, a unit for writing image data to a plurality of memory chips with one access to the image memory, and an output unit for outputting the image data stored in the image memory,
Each memory chip can store information of a plurality of pixels distributed in a plurality of rows and columns.

The image memory may be divided into at least two areas, and a plurality of memory chips may be arranged corresponding to each area.

Further, the image memory or the memory chip forming the area of the image memory is the number of the memory chip for storing the pixel information in the column (or row) direction of the image memory or the area of the image memory. However, the numbers of the memory chips that store the pixel information may be arranged in the order of the numbers of the memory chips in the row (or column) direction of the image memory or the area of the image memory. .

Further, the write request of the image data to the memory chip is monitored, and when the predetermined write start condition is satisfied, the write request of the image data to the chip until the condition is satisfied is summarized and the image is written. A write control means for instructing to write with one access to the memory can also be provided.

Further, the write control means is provided with a detecting means for detecting the occurrence of two write requests to the same chip and a timer, and the write start condition is the detection by the detecting means or a predetermined time by the timer. It can also be a detection of the passage of time.

Further, when a two-dimensional address consisting of x-coordinate and y-coordinate is given to the image memory, and the writing control means writes by the writing means in order from the smaller x-coordinate to the larger x-coordinate. It is also possible to collect the data from the smaller x coordinate. When writing is performed by the writing means in order from the larger x-coordinate to the smaller x-coordinate, the writing can be performed from the larger x-coordinate.

Further, the image memory is a dual port memory, and the information processing apparatus is provided with a conversion means for rotating the data serially read from the image memory according to a predetermined rule, and reading the data from the image memory. At that time, in the column (or row) direction of the image memory or the region of the image memory, the number of the memory chip that stores the pixel information can be converted and displayed in the bit reverse order. . In the image memory or in the row (or column) direction of the area of the image memory, the numbers of the memory chips that store pixel information can be converted and displayed so as to be arranged in the order of the numbers of the memory chips.

[0016]

Function: The address and the writing / not-writing control are performed for each chip instead of determining which type of access is to be performed in the area of an integer pixel × integer pixel having a variable size. I was able to write in one shape at a time.
For this reason, it is possible to write in a flexible shape with one access to the image memory, so that a straight line with a line width of about 1 pixel,
Alternatively, even with a curved line, many pixels can be simultaneously written in one image memory cycle.

Further, the above-mentioned flexible shape that can be written at once does not exceed the transition of the upper bit of the address corresponding to the x coordinate and the transition of the upper bit of the address corresponding to the y coordinate. Of the address signal lines from the means for controlling the image memory to access the image memory in a flexible manner, the x coordinate and
The address line corresponding to the upper bits of the y coordinate can be shared by all chips.

Further, it is possible to combine a plurality of write accesses from the means for drawing in the image memory into one and write the data by one access to the image memory.

Further, when a plurality of write accesses from the means for performing drawing in the image memory are combined into one in the means for controlling so that the flexible shape can be accessed, the write access is collected from the smaller x-coordinate or larger. It is possible to combine more pixels into one access to the image memory by changing whether to combine them from one side according to the drawing direction.

Further, the image memory is composed of a dynamic memory or a memory such as an image dual port memory which supplies an address separately to a ROW address and a COLUMN address.
By providing the LUMN address independently for each chip, it is possible to independently provide each chip with address information having a larger number of bits than the number of address signal lines independently connected to each chip.

[0021]

FIG. 1 is a block diagram showing an information processing system for carrying out the present invention.

In the information processing system shown in FIG. 1, a CPU 1, a main memory 2 and a drawing processing mechanism 3 are connected to a system bus 8. An image memory control mechanism 4 is connected to the drawing processing mechanism 3, and an image memory 5 is connected to the image memory control mechanism 4. Further, a display data control mechanism 6 is connected to the image memory 5, and the display data control mechanism 6 has
The display device 7 is connected.

The CPU 1 controls the entire system. The main memory 2 stores instructions and data for the CPU 1 to operate. The drawing processing mechanism 3 is a drawing processing support mechanism that is instructed by the CPU 1 what to draw and draws a graphic according to this instruction. The image memory control mechanism 4 controls the image memory 5. The image memory 5 is a memory that stores image data. The display data control mechanism 6 processes the display read data of the image memory 5. The display device 7 displays the image data.

In FIG. 1, the drawing processing mechanism 3 is a CP.
It is provided between U1 and the image memory control mechanism 4. However, the image memory control mechanism 4 may be provided on the system bus 8. In addition, the drawing processing mechanism 3 is not provided, and the CPU 1
However, it is also possible to configure it as a system that directly performs drawing processing.

The CPU 1 executes the instructions and data stored in the main memory 2 and performs various processes. When performing the drawing process, the CPU 1 instructs the drawing processing mechanism 3 what to draw. When this instruction is issued, the drawing processing mechanism 3 instructs the image memory control mechanism 4 to access (write) the image memory 5. When this instruction is issued, the image memory control mechanism 4 writes data to the image memory 5. Image memory 5
When the data is written to the display data control mechanism 6,
The data written in the image memory 5 is read out and displayed on the display device 7.

The figure drawn by the CPU 1 or the drawing processing mechanism 3 is, for example, a straight line, a rectangle whose vertical and horizontal sides are vertical and horizontal, an arbitrary polygon, an arc, an elliptic arc, or a figure created by a combination thereof. It is a letter or a letter. Among these, the objects to which the present invention effectively functions are thin straight lines (line width is about 1 pixel), vertical and horizontal vertical and horizontal elongated rectangles, and elongated polygons (line width 1
Thin arcs (of the order of pixels), elliptical arcs, and characters with thin lines and transparent background.

The structure of the image memory control mechanism 4 shown in FIG. 1 is shown in FIG.

In FIG. 2, the image memory control mechanism 4 includes a bus interface mechanism 41, an image memory interface mechanism 42, and a write coalescing mechanism 40.
Is provided.

The bus interface mechanism 41 interfaces with the system bus 8 or the drawing processing mechanism 3. The image memory interface mechanism 42 controls the image memory 5 so that data can be written in various areas in one memory cycle. The write coalescing mechanism 40 writes data to the image memory 5 once when data is continuously written from the CPU 1 or the drawing processing mechanism 3 to an area that can be written by one access to the image memory 5. Put it in a cycle.

The drawing processing execution instruction input from the system bus 8 or the drawing processing mechanism 3 to the image memory control mechanism 4 is input to the write coalescing mechanism 40 via the bus interface mechanism 41. In the write coalescing mechanism 40, the CPU 1 or the drawing processing mechanism 3
Therefore, when the data to be written to the image memory 5 are continuously written, it is determined whether or not the data can be written simultaneously by one access to the memory 5. If it is determined that the data can be written at the same time, a process for collectively writing the data in one image memory write cycle is performed. The data processed in this way is written to the image memory 5 via the image memory interface mechanism 42.

In order to be able to write to various areas of the image memory 5, the image memory is composed of a plurality of memory chips, and one address of one memory chip is one.
It is configured to correspond to pixels.

In the following, for simplification, one chip constitutes one pixel, and an address is independently given to each chip. However, for example, when a 4-bit memory chip is used as a memory chip forming an image memory and an image memory having an 8-plane structure is used to configure one pixel with two chips, one pixel is used. It is also possible to treat the two chips constituting the above as one set and give the same address to one set of chips, and configure the image memory so as to give different addresses between the sets of the memory chips.

FIG. 3 and FIG. 4 are views showing some examples of the correspondence between each chip and the position on the screen so that various types of areas of the memory can be simultaneously written.

On the entire screen, the rectangular area shown here is repeatedly applied. That is, a plurality of patterns shown in FIGS. 3 and 4 are collected to form the entire screen.

FIG. 3 shows an example in which the number of memory chips forming the image memory is a power of two. FIG. 4 is an example in the case where it is not a power of two. The numbers in the grids of FIGS. 3 and 4 indicate the numbers of the chips that form the pixel at that position.

When the number of memory chips is a power of 2, as shown in (a), (c), and (e) of FIG. Place in reverse order. When arranged in this way, the vertical and horizontal lengths are both 2
A rectangular region of power-of-pixels (for example, in FIG. 3A, the vertical and horizontal directions are 1 × 16, 2 × 8, 4 × 4, 8 × 2, 1
6 × 1 area) can be accessed simultaneously. The bit reverse order means that when the binary numbers are rearranged by rearranging the bits when the integers from 0 to (power of 2-1) are expressed in binary numbers, the bits are consecutive. It is the order that you do. FIGS. 3B and 3D are examples in the case where this is not done, and access is not possible in a form in which the chips are arranged in a vertical line.

If the number of memory chips is not a power of 2, there is no general arrangement. FIG. 4 gives some possible examples.

In the present invention, instead of deciding whether to perform access among various rectangles that can be accessed at the same time, it is possible to write in a more flexible form at one time.
In the present invention, writing to the image memory is performed in various forms. However, like the logical operation with the data originally at the writing position, the data at the same position as the writing position is read out. In the case of writing back after updating, the write access can be performed by using a read-modify-write cycle or by causing a write cycle after the read cycle for the same address.

The number of chips to which different address values are given determines the number of pixels that can be accessed simultaneously. Further, only a part is changed without changing all the address lines of each chip (for example, the entire screen is divided into regions of 16 × 16 pixels, and addresses are given to the divided regions. The number of address lines output from the image memory control mechanism 4 is reduced by configuring each bit with the upper 4 bits indicating the area and the lower 4 bits indicating the address in the area. You can Since a common address signal is given to each chip, it is possible to limit the range of the shape of the area that can be accessed at the same time. However, in drawing a figure, generally, the areas to which data is written at once are spatially adjacent to each other. Therefore, if the adjacent areas within a certain range can be accessed at once, even if the area range is limited, Has little impact on performance.

For example, considering the y-coordinate in the vertical direction on the screen and the x-coordinate in the horizontal direction, the address of each point on the screen is given by these x-coordinates and y-coordinates. , Y address). By changing only the lower 4 bits of the y-coordinate in each chip and making the y-coordinates more than that common, the region which can be simultaneously accessed in the vertical direction is limited within the 16 pixel boundary in the vertical direction. In general,
By making the lower n bits of the y-coordinate given to each chip independent and making them more common, the area that can be simultaneously accessed in the y-direction is limited to within 2 n. Also in the x direction, if the upper bits are made common to each chip, the area that can be simultaneously accessed in the x direction is similarly limited, but the lower bits of the x coordinate are handled differently. For example, in a 16-chip configuration, if the position on the image specified by the same address for each chip is a region in one column in the x direction, the lower 4 bits of the x coordinate are used to specify each chip. , Is not connected to the address line of each chip.

The following shows how to write at once.

(1) One chip can be written only at a position designated by one address, but different addresses can be given to different chips, so that writing can be performed at another address position. On the contrary, two or more pixels corresponding to one chip cannot be written simultaneously.

(2) In order to reduce the number of address signal lines from the image memory control mechanism 4, different values are not given to all the bits of the addresses of all the chips, and the high order of the addresses indicated by the x and y coordinates is given. The addresses of are common, and only the lower m bits of the x coordinate and the lower n bits of the y coordinate are separately provided. Therefore, the range of the region that can be accessed at one time is limited to within 2 m to the power of 2 in the x-axis direction (x direction) and within the n to the power of 2 in the y-axis direction (y direction). Hereinafter, an area within 2 m to the mth power in the x direction and within 2 to the nth power in the y direction is referred to as a write block. Of x and y addresses, a common part (higher address) is called a write block address.

Hereinafter, the image memory control mechanism 4 shown in FIG.
The connection method of the address signal line and the write enable signal between the image memory 5 and the image memory 5 will be described in more detail with reference to FIG.

In FIG. 16, the number of image memory chips is one.
An example in the case of six is shown. 16, 510, 511, ..., Of FIG.
51e and 51f are image memory chips 50, respectively.
Write enable signals (write_enable) for 0, 501, ..., 50e, 50f. 520 is a component (block) which is common to all chips among the addresses.
_Address). 530,531, ..., 53
e and 53f are components (sub_address) of the address that are independently given to the respective image memory chips 500, 501, ..., 50e and 50f.

Block_address52 in FIG.
0, sub_address 530, 531, ..., 53
e, 53f, and a component coa which is commonly given to all chips among the addresses created by the write coalescing mechanism (40 in FIG. 2 and FIG. 5) in the image memory control mechanism 4.
lossed_block_address58, a component coalesced_ that is given to each chip independently
FIG. 17 shows the relationship with sub_address 56.

FIG. 17 shows image memory chips 500, 5
In this example, a dynamic memory or an image dual port memory is used as 01, ..., 50e, 50f.

In these cases, as shown in FIG.
The addresses to the image memory chips are ras and c
It is given as an address row address and a column address on the address line A at the time of falling of two control signals called as. Figure 1
In the case of 7, the number of rows and the number of columns are both 512, and row address,
The number of bits of the column address is 9
An example in the case of a bit is shown.

Coalesced_sub_a in FIG.
FIG. 19 shows the positional relationship between the address 56 and the image. Coalesced_block_ad in FIG.
FIG. 20 shows the positional relationship between the dress 58 and the image.

FIG. 19 shows an example in the case where the write block has 16 pixels horizontally and 16 pixels vertically, as shown in FIG. Reference numeral 1040 in FIG. 19 represents one write block. In this block, coalesced_bl
The ock_address 58 is the same. In this, the number of pixels corresponding to each image memory chip is 1
There are 6 pixels each. coalesced_sub_a
The address 56 is used to specify one of the 16 writing positions (corresponding to one image memory chip). Co in one write block
Although the positional relationship on the image with the ordered_sub_address 56 can be assigned in any manner, from the viewpoint of feasibility, for example, an area of 16 pixels in the horizontal direction and 1 pixel in the vertical direction shown by 1041 in FIG. 19 is the same core.
It is easy to set it as sced_sub_address 56.

In FIG. 20, the write block 1040 is repeated over the entire image area 1042, and the coalesced_block_a of each write block is repeated.
The state where the x coordinate component (cbx) and the y coordinate component (cby) of the address 58 are assigned is shown. In this example, the size of the entire image area 1042 is 2048 pixels in the horizontal direction,
The vertical size is 2048 pixels.

Returning to the explanation of FIG. From the image memory control mechanism 4 to the image memory chips 500, 501, ..., 50e,
Address information coalesc that needs to be transmitted to 50f
The ed_sub_address 56 has 4 bits in this example. These 4 bits are assigned to the same address signal line of row address and column address. With this allocation, the image memory control mechanism 4 causes the image memory chips 500, 501 ,.
e, 50f, the number of signal lines sub_address that must be independently given to each image memory chip,
It can be halved. As a result, the increase in the number of signal lines of the image memory control mechanism can be suppressed.

Coalesced with a configuration different from this example
When the number of bits of _sub_address 56 is an odd number, the number of signal lines sub_address that must be independently applied to each image memory chip does not become half, but the increase can be suppressed by the same method.

When the image memory chip is composed of a memory which does not give a multiplexed address, the coalesc
ed_sub_address remains sub_ad
dressed, coalesced_block_ad
There is no particular point to devise because the address is directly connected to the block_address as it is.

Returning to the explanation of FIG. Hereinafter, the address signal lines and the data signal lines, which are represented by one line in the drawings, and one signal name given to each signal line, are handled as a group, not as a single signal line. It is a collection of a plurality of signal lines. Furthermore, "(0-f)" in the signal name is "(0)," after the signal line name before "(0-f)".
(1), (2), (3), (4), (5), (6), (7), (8), (9), (a), (b), (c),
16 represented by 16 signal names with "(d), (e), (f)" attached
This is a collective description of individual signals.

All signal values are clock clock1.
It is assumed that it is a so-called synchronous logic in which a value that changes in synchronization with 000 and that uses a signal value is sampled in synchronization with the clock clock 1000.

The bus interface mechanism 41 is a CPU
1 or write access from the drawing processing mechanism 3,
Write request stencil_chip (0-f) 51 for each chip, address chip_address (0-f) 52 for each chip, and
The data for each chip is converted to chip_data (0-f) 55.

The write coalescing mechanism 40 puts these write accesses together, writes a request for each chip coalesced_chip (0-f) 54, and a write block address coalesced_block_addres for the next image memory access.
s58, an address coalesced_sub_address (0-f) 56 indicating a position in the write block for each chip, data coalesced_data (0-f) 57 for each chip, and a write request write_coal to the image memory interface mechanism 42.
Convert to escing_request59.

The image memory interface mechanism 42 is
If access to the previous image memory is not completed, or if the image memory cannot be accessed immediately due to display read, display serial read transfer, or refresh, memory_busy60
Is output. In addition, the light coalescing mechanism 40
When the next write request from the bus interface mechanism 41 cannot be accepted, write_coalescing_bus
Output y53.

Further, normally, the image memory 5 has an address such as a ROW address (row address) and a COL, like a dynamic memory or an image dual port memory.
It is composed of a memory supplied separately from the UMN address (column address), and the ROW address and the COLUMN address are time-division multiplexed and given to one address signal line. Therefore, the image memory interface mechanism 42
Is an address coal indicating the position in the write block for each chip output from the write coalescing mechanism 40.
esced_sub_address (0-f) 56 to the image memory control mechanism 4
Can be time-division multiplexed and applied to address signal lines independently applied to each chip. As a result, the number of address signal lines of the image memory control mechanism 4 can be reduced.

The structure of the write coalescing mechanism, which is a mechanism for writing to the flexible area with one access, is shown in FIGS. 5 and 6. FIG. 5 shows a control system, and FIG. 6 shows an address and data system.

In this method, whether writing to the memory is possible is managed on a chip-by-chip basis, and pixels that can be written by one access are put together.

In FIG. 5, stencil_chip (0-f) 51
Is a signal indicating a write request to the image memory control mechanism 4 from the system bus 8 or the drawing processing mechanism 3,
It indicates whether or not a write request is issued for each of the chip numbers 0 to f. chip_address (0-f) 52 and chip_data (0-f) 55 indicate an address and data to be written for each chip for which stencil_chip (0-f) 51 is output, and stencil_chip (0 0-f) 51
It is undefined for chips that do not show.

The write data chip_data (0-f) 55 of the chip where the stencil_chip (0-f) 51 is output is not immediately written to the image memory 5. Data chip_data (0-f) 55
Are separately stored in the write coalescing mechanism 40 into chip data to be written when the next image memory cycle occurs and chip data not to be written in the next image memory cycle.

For the chip to be written the next time an image memory cycle occurs, coalescable_chip (0-
f) 421 is output. coalescable_chip (0-f) 421
Is a chip coalesce that is already stored in the write coalescing block 40 as a chip to be written next.
The address coalesced_sub_address (0-f) 56 indicating the position of the d_chip (0-f) 54 in the write block and the data coalesced_data (0-f) 57 are put together. The combined 421, 56, 57 are written in the next image memory cycle. A mechanism for bringing the parts 421, 56, 57 together is shown as 410, 411 in FIG. 6 and 4 in FIG.
04, 405, 402.

Reference numeral 401 in FIG. 5 and 429 and 430 in FIG.
It is a selector that operates in conjunction with each other. Reference numeral 401 is a selector for a control signal indicating whether or not writing is performed for each chip. Reference numeral 429 is a selector for the address. 43
0 is a selector for data. Selector 40
1,429,430 are the chips that have been kept waiting because they cannot be written in the next image memory write cycle qued_chip (0-f)
When there is no 424, the signal stencil_chip (0-f) 51, chip_addres coming from the bus interface mechanism 41
s (0-f) 52 and chip_data (0-f) 55 are selected. If there is even one, control signal for the chip that has been kept waiting
qued_chip (0-f) 424, address qued_address (0-f) 4
26, qued_data (0-f) 427 is selected. qued_chip (0-
f) The OR gate 407 determines whether or not there is even one 424. The outputs of the selectors 401, 429, 430 are write control signals write_chip (0-f) 42 for each chip.
0, address write_address (0-f) 431, data write_
It is data (0-f) 432. These 420, 431, 4
32 is used for the determination of the possibility of putting together in the next cycle.

Sa written next to the write data input signal of the data latch mechanism 410 of FIG. 6 is chip_address (0
-f) Indicates that the signal is a signal obtained by taking out an address indicating a position in the write block for each chip from 52.

A queing_chip (0-f) 422 signal is output to a chip which is not written in the next image memory write cycle, and the write coalescing mechanism 40 waits for writing to the image memory 5. Chip qued_chi
It is stored as an address qued_address (0-f) 426 of p (0-f) 424 and data qued_data (0-f) 427.
The mechanism for storing as 426 and 427 is shown at 408, 409 in FIG. 6 and 403 in FIG.

408, 409, 410 and 411 of FIG.
Are all composed of the data latch mechanism 9 shown in FIG. When the write signal 96 is output, the data latch mechanism 9 takes in the write data 95 in synchronization with the clock clock 1000 and outputs it to the output 97.

Returning to FIG. 5, coalesced_chip (0-f) 54
Is a signal indicating a chip to be written in the next image memory write cycle. Not all the chips in which stencil_chip (0-f) 51 is output are written in the image memory 5 in one write cycle to the image memory. coalesce
After the chip with d_chip (0-f) 54 is written, q
ued_chip (0-f) 424 is the new coalescable_chip (0-f)
421 and queing_chip (0-f) 422.

If any one of the queing_chip (0-f) 422 is output, the write coalescing mechanism 40 cannot accept the next write request from the system bus or the drawing processing mechanism. Signal_write_coalescing_busy 53 indicating queing_chip (0
-f) Whether or not there is any chip with 422,
It is determined by the OR gate 406.

Reference numeral 400 denotes a grouping possibility judgment circuit for dividing the stencil_chip (0-f) 51 or the qued_chip (0-f) 424 into a chip to be written in the next image memory write cycle and a chip not to be written. . Hereinafter, the input of the groupability determination circuit 400 will be referred to as write_chip (0-f) 420.

The configuration of the grouping possibility determination circuit 400 is shown in FIG.
Shown in.

In the grouping possibility determination circuit 400, the write block inside / outside determination circuit 4000 causes write_chip (0-
f) It is determined whether or not the writing to the chip in which 420 is output falls within the writing block. After this judgment, busy_chi among the pixels in one block of the write block
It is determined that only chips for which p (0-f) 423 is not output can be combined into one access. busy_chip (0-f) 423
Is the image memory interface mechanism 42 for the chip in which coalesced_chip (0-f) 54 of that chip is output.
Is output when writing is not completed at the next clock. The flush 428 of FIG. 5 is output when the write coalescing mechanism 40 issues a write access request write_coalescing_request 59 to the image memory interface mechanism 42 and the image memory does not issue memory_busy 60, and this request is accepted. ,
The write timing to the image memory is shown.

FIG. 9 shows the configuration of the write block inside / outside determination circuit 4000 for determining whether or not the write blocks can be combined into one block.

Reference numeral 40000 in FIG. 9 indicates write_chip (0-f) 4.
20 is a write block address determination circuit for selecting the write block address of one of the 20 chips. The reference numeral 40003 indicates a case where there is no data stored in the write coalescing mechanism 40 as data to be written in the next write cycle to the image memory.
Or when it disappears (these two timings are busy
_chip (0-f) 423 is the timing when all are not output)
Next write block address candidate coalescing_b
It is a write block address latch mechanism that takes in lock_address (0-f) 40011. Write block address held in 40003 coalesced_block_addres
s58 indicates the write block address of the next image memory write cycle.

Reference numeral 40004 is a comparator for detecting a match between the next write block address next_block_address 40010 and the write block address of each chip. Four
0005 is the next write block address 40010
And the write block address 52 of each chip match, and the next write request is issued from the system bus or the drawing support mechanism (write_chip (0-f) 42
0) only chips (chip_i
It is an AND gate for determining n (0-f) 4004). “Ba” written next to the input of the coincidence comparator 40004 indicates that the write block address is extracted from the chip address chip_address (0-f) 52 of each chip.

Next, two examples of the write block address determination circuit 40000 will be shown.

In the first embodiment, write_chip (0-
f) Of the chips with 420, the chip with the smallest chip number is selected, and the write block address 52 of this chip is set as the next write block address candidate caolescing_block_address (0-f) 40011.

In the second embodiment, write_chip (0-
f) Of the chips with 420, the write block address corresponding to the chip with the smallest x or the largest x coordinate is set as the candidate for the next write block address.

FIG. 10 shows an implementation circuit of the first embodiment. 400001 is a priority determination circuit. 40,000
Reference numeral 2 is an output of the priority determination circuit 400001, which is a selector for selecting one of the write addresses 431.

An implementation circuit of the second embodiment is shown in FIG. Reference numerals 400010 to 400040 are all two-chip selection mechanisms that select which address between two chips is to be the candidate for the next write block address. FIG. 12 shows the configuration of 400010 to 400040.

Reference numerals 40050 to 40065 in FIG. 11 are group signals g (n) (n = 0, 1, 2, ..., F). Group signal
g (n) is the write address of the nth chip write_addres
s (n) 431 and write signal write_ch for each chip
This is a signal that summarizes ip (n) 420.

The signals g0 (110) and g1 (11 in FIG.
X0 and x1 written next to 1) indicate that the write address of the group signal is the signal from which the x coordinate is further extracted. ca0 and ca1 indicate that they are signals from which the write address is extracted. w0 and w1 indicate that the chip write signal is extracted. Cao written next to the signal go (112) and w
The same applies to o.

Reference numeral 100 in FIG. 12 is a comparator which outputs "true" when x0 is smaller than x1. 100
1 is a signal dir that indicates that when w0 and w1 are both output, the one with the larger x coordinate is selected. Circuit 10
From 0 to 108, if the signal dir (1001) is not output among the chips for which the chip write signal is output, x
The chip with the smaller coordinate or the larger chip when the signal dir (1001) is output is selected.

A signal dir (1001) indicating whether the x-coordinates are to be collected from the smaller x-coordinate or the larger one is drawn from the x-coordinate to the x-coordinate when the long shape is drawn horizontally. When outputting in order from the one with the smallest coordinates and drawing in order from the one with the largest x coordinate,
Outputs are arranged in order from the largest x-coordinate.

Output of write block address determination circuit 40000 in FIG. 11 coalescing_block_address (0-f)
(40011) is a signal in which the write block address of the write address 431 of the output of the 2-chip selection mechanism 400040 is extracted.

Next, in the write coalescing mechanism 40,
Two triggers (triggers) for issuing a request for writing the collected data in the image memory 5 are shown below.

The first trigger is the time when the next write data from the higher order cannot be put together, and since it cannot be put together, it must be written inevitably.

The second trigger is when the image memory 5 is read from the CPU 1 or the drawing processing mechanism 3, and writing must be performed first in order to maintain the time series of writing and reading.

Here, the image memory 5 can be obtained only by the above trigger.
There is a problem that the last writing to the image memory is not written to the image memory 5 unless the image memory access is next performed, and is not reflected on the screen of the display device 7 forever. In order to avoid this, a trigger for writing to the image memory is provided in addition to the above trigger. Three examples of this opportunity are shown below.

In the first embodiment, there is no access from the CPU 1 or the drawing processing mechanism 3, and the image memory is
Writing to the image memory 5 is caused at any time in the idle state.

In the second embodiment, the image memory control mechanism 4
A register is provided to cause writing to the image memory 5 when there is data that has not been written to the image memory 5. Writing to this register from the CPU 1 explicitly causes writing to the image memory 5.

In the third embodiment, this occurs at the timing of periodical blanking from the controller of the display device 7 or at the time when the image memory 5 is regularly refreshed from outside, such as before or after refreshing.

Next, FIG. 21 shows the configuration of the display data processing mechanism for performing the processing when displaying the data read from the memory chip.

In FIG. 21, the number of image memory chips is 1.
An example is shown in FIG. 3A in which the number of writing blocks is six and the number of writing blocks is 16 pixels horizontally and 16 pixels vertically.

Reference numeral 600 denotes each image memory chip 500, 5
The display data rotating mechanism converts the read data for display, which is read simultaneously from 16 pixels from 01, ..., 50e, 50f, into the pixel unit data pixel_data 610 which is sequentially sent out in the display order.

Numeral 601 designates pixel_data 610 as the value of the color actually displayed on the display device (in the case of a color display device, the brightness of the three primary colors, in the case of a monochrome gray scale display device) pixel_color 611. It is a color lookup table to convert.

Reference numeral 602 denotes pixel_given as a digital value.
It is a digital-to-analog converter that converts color 611 into an analog value video_out 62 that can be received by the display device. Digital-to-analog converter 602
Is unnecessary when connecting a display device such as a liquid crystal display device which receives a digital display value as it is.

A display line number counter 603 counts the number of the current display line. The output line_number_mod16 of the display line number counter is used by the display data rotation mechanism 601 to determine the order of the image memory chips to start sending.

Next, the display data rotating mechanism 601 shown in FIG.
22 is shown in a time chart in FIG.

In FIG. 22, each image memory chip 50
The display read data 540, 541, ..., 54e, 54f from 0, 501, ..., 50e, 50f are all image memory chips at every time interval for displaying 16 pixels after the display period signal 61 becomes active. Are read at the same time. The display data rotation mechanism 600 converts the display read data read in units of 16 pixels into pixel_data 610 that is sequentially sent out in display order. However, since the correspondence between the position on the display screen and each image memory chip changes for each display line as shown in FIG. 19, the display data rotation mechanism 600 causes the display line number counter 603 to output the display line number. Is used to change which image memory chip the data is sent from, using line_number_mod16 612, which is the remainder.

Next, an operation example of the write coalescing mechanism 40 will be described with reference to FIGS. 13, 14 and 15 for the case of straight line drawing and the case of character drawing.

FIG. 13 is an example of line drawing. Position (4,
From 4), it is shown how many image memory cycles are generated when a straight line having a length of 16 dots is drawn in the direction of 45 degrees to the lower right, and which pixel is drawn in each image memory cycle. In this example, the pixel to write is 1 in the image memory.
It is assumed that writing is possible at the same time within a 6 × 16 pixel boundary (boundary is fixed at a position where the x coordinate and the y coordinate are multiples of 16) and different chips. Note that 0xa,
0xb, 0xc, 0xd, 0xe, 0xf, 0x10,0x11,0x12,0x13 are hexadecimal numbers a, b, c, d, e, f, 10, 11, respectively.
12, 13 (ie decimal numbers 10, 11, 12,
13, 14, 15, 16, 17, 18, 19).

In the first cycle, the coordinates (4,4), (5,5), (6,6), (7,7), (8,8), (9,9) surrounded by 1010 are used. ) Six points of chip 6 fc 5 9 2 are written, but the pixel at the next coordinate (0xa, 0xa) corresponds to chip f, and chip f is busy writing the pixel at coordinate (5,5). , I can't write at the same time.

In the second cycle, two points of coordinates (0xa, 0xa) and (0xb, 0xb) chip f 8 surrounded by 1011 are written for the same reason.

In the third cycle, four points of coordinates (0xc, 0xc), (0xd, 0xd), (0xe, 0xe), (0xf, 0xf) chips f 8 5 e surrounded by 1012 are written. However, the next coordinate (0x10,0x10) cannot be written at the same time because it is within another 16 × 16 pixel boundary.

Finally, the remaining four point coordinates (0x10,0x10), (0x11,0x11), (0x12,0x12), (0x13,0x13) chips 0 9 6 f surrounded by 1013 are written.

14 and 15 are examples of character drawing.

FIG. 15 shows an example of drawing a character A having a transparent background of 6 pixels and 6 pixels from the position (5, 2).

In this case, the character data stored in the main memory in a data format in which 1 bit represents 1 pixel is read by the CPU 1 or the drawing processing mechanism 3 and input to the image memory control mechanism 4. The image memory control mechanism 4 updates the pixel corresponding to “1” of the bit data written from the CPU 1 or the drawing processing mechanism 3 to the pixel value designated by the register in the image memory control mechanism 4, The pixel corresponding to “0” is not updated.

For example, it is assumed that the data in the main memory representing the character A is as shown in FIG. The order of inputting to the image memory control mechanism 4 is such that one line of a character is input once to the image memory control mechanism 4, and the entire character is from top to bottom.

In the first cycle, the coordinates surrounded by 1030 are (7,2), (8,2), (6,3), (9,3), (5,4), (0xa, 4 ), (5,5), (6,5), (7,5) Chips bc 2 5 7 7 cf 0 9 points are written, but the pixel at the next coordinate (8,5) is chip 2
Corresponding to, chip 2 is busy writing the pixel at coordinates (6,3), so it cannot write at the same time.

In the second cycle, for the same reason as above, the coordinates surrounded by 1031 are (8,5), (9,5), (0xa, 5), (5,6), (0xa, 6). 5 points of chip 2 3 4 b 0 are written.

And in the last cycle, 1032
The remaining two coordinates (5,7), (0xa, 7) chips 38 surrounded by are written.

In the above embodiment, the memory chips are associated with the pixels in the column direction on the image memory in the bit reverse order, but the memory chips are associated with the pixel in the row direction in the bit reverse order. May be.

[0117]

EFFECTS OF THE INVENTION Since the memory can be written in a flexible manner by accessing the image memory once, even if a straight line or a curve having a line width of about 1 pixel is used in one image memory cycle, It is possible to write to many pixels at the same time. As a result, the number of accesses to the image memory is reduced, and a graphic can be drawn at high speed.

Further, the above-mentioned flexible shape that can be written at a time is set so as not to exceed the transition of the high-order bit of the address corresponding to the x coordinate and the transition of the high-order bit of the address corresponding to the y coordinate. Of the address signal lines from the means for controlling the image memory to access the image memory in a flexible manner, the x coordinate and
The address line corresponding to the upper bits of the y coordinate can be shared by all chips. As a result, it is possible to suppress an increase in the number of address signal lines due to the implementation of the present invention.

Furthermore, since the write access from the means for drawing to the image memory to a plurality of pixels controlled by different chips is combined into one, the writing is performed by one access to the image memory. The means to do is x,
It suffices to write to the image memory space addressed by the y coordinate, and the processing of the means for performing drawing does not become complicated due to the implementation of the present invention, and the drawing processing can be performed at high speed.

Further, in the means for controlling the image memory so that it can be accessed in a flexible manner, when a plurality of write accesses from the means for drawing in the image memory are put together, they are put together from the smaller x coordinate. It is possible to combine more pixels into one access to the image memory by changing whether to collect from the larger one or according to the drawing direction of the graphic. As a result, the number of times the image memory is accessed is reduced, and graphics can be drawn at high speed.

Further, the image memory is composed of a dynamic memory or a memory such as an image dual port memory which supplies an address separately to a ROW address and a COLUMN address.
By providing the LUMN address independently for each chip, it is possible to independently provide each chip with address information having a larger number of bits than the number of address signal lines connected to each chip independently. As a result, it is possible to further suppress the increase in the number of address signal lines due to the practice of the present invention.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a computer system for implementing the present invention.

FIG. 2 is a diagram showing an internal configuration of an image memory control mechanism.

FIG. 3 is a diagram showing a spatial arrangement of an image memory (when the number of chips is a power of 2).

FIG. 4 is a diagram showing a spatial arrangement of an image memory (when the number of chips is not a power of 2).

FIG. 5 is a diagram showing a control system of a write coalescing mechanism.

FIG. 6 is a diagram showing an address / data system of a write coalescing mechanism.

FIG. 7 is a diagram showing a data latch mechanism.

FIG. 8 is a diagram showing a grouping possibility determination circuit.

FIG. 9 is a diagram showing a write block inside / outside determination circuit.

FIG. 10 is a diagram showing a first embodiment of a write block address determination circuit.

FIG. 11 is a diagram showing a second embodiment of the write block address determination circuit.

FIG. 12 is a view showing a selection mechanism between two chips.

FIG. 13 is a diagram showing an example of a writing operation to an image memory at the time of drawing a straight line.

FIG. 14 is a diagram showing an example of a storage format of character data on a main memory.

FIG. 15 is a diagram showing an example of a writing operation to an image memory at the time of drawing a character.

FIG. 16 is a connection diagram of address signal lines.

FIG. 17 is a diagram showing an address connection method in the image memory control mechanism.

FIG. 18 is a timing diagram of an address given to the image memory.

FIG. 19 is an address map diagram in a write block.

FIG. 20 is an address map diagram of the image memory.

FIG. 21 is a diagram showing a display data processing mechanism.

FIG. 22 is a timing chart showing the operation of the display data rotating mechanism.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... CPU 2 ... Main memory 3 ... Drawing processing mechanism 4 ... Image memory control mechanism 5 ... Image memory 6 ... Color lookup table 7 ... Display device 8 ... System bus 40 ... Light coalescing mechanism 41 ... Bus interface mechanism 42 ... Image Memory interface mechanism 400 ... Summary determination circuit 4000 ... Write block inside / outside determination circuit 40000 ... Write block address determination circuit

Front page continued (72) Inventor Hitoshi Kawaguchi, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Microelectronics Device Development Laboratory, Hitachi, Ltd. (72) Masataka Kobayashi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Address Company Hitachi Micro Software Systems (72) Inventor Hideo Haruta 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Address Hitachi Micro Software Systems (72) Incorporator Chihiro Tamura Yoshida, Totsuka-ku, Yokohama-shi, Kanagawa 292, Machi Incorporated Hitachi, Ltd. Microelectronics Device Development Laboratory (72) Inventor Nori Kurokawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Hitachi Ltd. Microelectronics Device Development Laboratory

Claims (7)

[Claims] 1. An image memory for storing image data, which is composed of a plurality of memory chips each storing information of different pixels on an image, and a plurality of the plurality of memory chips that can be accessed by a single access to the image memory. An information processing apparatus comprising: a unit for writing image data to a memory chip; and an output unit for outputting the image data stored in the image memory, wherein each of the memory chips has a plurality of rows and columns. An information processing device, which stores the information of the pixel. 2. The information processing apparatus according to claim 1, wherein the image memory is divided into at least two areas, and a plurality of memory chips are arranged corresponding to each area. . 3. The image memory, or the memory chip forming the area of the image memory according to claim 1, wherein the image memory or a column (or row) of the area of the image memory. In the direction, the numbers of the memory chips storing the pixel information are arranged in reverse bit order, and the pixel information is stored in the row (or column) direction of the image memory or the area of the image memory. An information processing device, wherein the numbers of the memory chips are arranged in the order of the numbers of the memory chips. 4. The method according to claim 1, 2 or 3, wherein a request for writing image data to the memory chip is monitored, and when a predetermined write start condition is satisfied,
An information processing apparatus, further comprising: a write control unit that collects image data write requests to a chip until the condition is satisfied and instructs to write the image data with one access to the image memory. 5. The write control means according to claim 4, further comprising detection means for detecting that two write requests to the same chip have occurred, and a timer, wherein the write start condition is the detection An information processing device, characterized in that the detection is performed by a means or the passage of a predetermined time by the timer. 6. The image memory according to claim 4, wherein a two-dimensional address consisting of x-coordinates and y-coordinates is given to the image memory, and the writing control means causes the writing means to change from the smaller x-coordinate to the larger one. When writing is performed sequentially, the compilation is performed from the smaller x-coordinate, and when the writing is performed sequentially from the larger x-coordinate to the smaller x-coordinate, the compilation is performed on the x-coordinate. An information processing device characterized by performing from the larger side. 7. The image memory according to claim 3, wherein the image memory is a dual port memory, and the information processing device stores data serially read from the image memory,
A conversion unit that rotates according to a predetermined rule is provided, and when reading data from the image memory, pixel information is stored in the image memory or in the column (or row) direction of the area of the image memory. The numbers of the memory chips to be arranged are arranged in a bit reverse order, and in the row (or column) direction of the image memory or the area of the image memory, the number of the memory chip storing pixel information is An information processing apparatus, characterized in that it is converted and displayed so as to be arranged in numerical order.