JPH0695751A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the output impedance to stably maintain the internal voltage by applying the difference voltage between the internal voltage and a reference voltage to the control input of a negative feedback amplifying means. CONSTITUTION:A transistor TR Q is used instead of the resistor or in a conventional technique and varies the resistance value and has a function to improve the current driving capability of input of an output voltage VL. A control terminal voltage VG of the TR Q supplied from a circuit RF has such characteristic that it is changed by the change of an external supply voltage VCC. That is, the voltage VG turns on the TR Q at a point VP of the voltage VCC when the voltage VCC is gradually increased from 0V. Since the TR Q is always turned on when the voltage VCC is higher than VP, the execution inpedance of the whole of a fundamental circuit BL is reduced, and the ratio to an effective impedance R is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a voltage limiter for dropping an external power supply voltage through a voltage limiter in a semiconductor integrated circuit chip and applying the voltage to a fine transistor in the chip.

[0002]

2. Description of the Related Art Due to the decrease in element withstand voltage due to the miniaturization of elements such as bipolar or MOS transistors, the operating voltage of integrated circuits has to be reduced accordingly. However, from the user's point of view, it is easy to use 5V
A single power supply is preferred. The external power supply voltage V _{CC is a} means for responding to the different demands of the integrated circuit maker and the user.
It is conceivable to lower the voltage within the chip and operate the fine element with the lowered voltage V _L.

FIG. 1 shows an embodiment of the circuit, for example, a circuit A'of the entire chip 10 including an input / output interface circuit.
Is an example of operating with the internal power supply voltage V _L dropped by the voltage limiter 13. In this example, the entire chip can be composed of elements having substantially the same size.

FIG. 2 was previously filed in Japanese Patent Application No. 56-57143, in which a fine element is used for the circuit A that determines the substantial integration density of the chip 10, and the external power supply voltage V _{CC is set} to the voltage limiter 13. This is an example of operating with the voltage V _L lowered by. On the other hand, this is an example in which a relatively large size element is used for the drive circuit B including an input / output interface, which does not contribute so much to the integration density, and V _CC is applied to it to operate. This enables a highly integrated circuit (hereinafter referred to as LSI) that operates at V _{CC when} viewed from the outside of the chip. still,
The circuits A, A'and B may be composed of bipolar transistors or MOS transistors such as C-MOS and N-MOS. Further, these two types of transistors may be mixed. Also, the normal operating point V
_It is not necessary to stick to 5V as _CC , V _CC =
Obviously, it is possible to arbitrarily set 3.5V, V _L = 2.5V, etc. depending on the design.

Here, the chip means a memory LSI and a logic L.
Shows a piece in which SI or other LSI is built. That is, in a memory LSI, the circuit A indicates a memory array and its related circuits, and in a logic LSI, an area formed by repeating a certain type of cell such as an area of various ROMs or RAMs such as a microcomputer. .

In the above voltage limiter system, a concrete example of the voltage limiter circuit is described in Japanese Patent Application No. 56-57143 or Japanese Patent Application No. 56-168698. However, the characteristics of the load seen from the voltage limiter, and
It is insufficient in the sense of a concrete example in which the voltage condition for preventing element breakdown, the relationship between the aging voltage condition and the normal operating voltage condition, and the power consumption are taken into consideration.

[0007]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit having an internal voltage generating means for supplying a stable internal voltage.

[0008]

The above object is to provide an internal circuit (A) including a MOS transistor and an external power supply voltage (V _CC ) supplied from the outside of the chip when the external power supply voltage increases. The external power supply voltage changes at a first rate of change up to a first voltage (Vp ₀ ), changes at a second rate of change from the first voltage to a second voltage (Vp ₁ ), and An internal voltage ( _VL ) that changes at a third rate of change that is greater than the second rate of change is output from the second voltage, and the internal voltage that changes at the third rate of change becomes the internal voltage during testing. Internal voltage generating means (13, BL, DCV1, DCV2) that can be applied to the circuit are provided inside the chip, and the internal voltage ( _VL ) of the internal voltage generating means and the reference voltage (Vth (1) + ... by applying a voltage based on Vth (n)) to the control input of the negative feedback amplifying means (Ql), This is achieved by generating with a relatively low output impedance from the output of the amplification means.

[0009]

[Operation] Internal voltage ( _VL ) and reference voltage (Vth (1) + ... Vth
By applying a voltage (difference voltage) based on (n)) to the control input of the negative feedback amplifying means (Ql), the output impedance can be reduced, and the internal voltage
It is possible to set ( _VL ) to a stable value. Other objects and features of the present invention will be apparent from the following examples.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a description will be given of voltage limiter circuit types for giving various V _L characteristics to V _CC and specific examples thereof. Next, a voltage limiter suitable for driving a voltage limiter and a large load. A specific example of the buffer circuit for use will be described.

3 to 6 show the basic concept of the voltage limiter circuit. That is, FIG. 3 shows, for example, R of FIG. 14 of Japanese Patent Application No. 56-168698 filed already.
_The transistor Q is used in order to make variable ₃ and to increase the current driving capability for the load to which the output voltage V _L is input. Here, the control terminal voltage V of the transistor Q
_G has a characteristic that it changes with a change in the external power supply voltage V _CC , which is the output voltage of the circuit REF. That is,
As shown in FIG. 4, when V _CC is gradually increased from 0 V, it is assumed that V _G turns on the transistor Q at a certain V _CC point V _P. In the V _P above V _CC, because Q is always turned on, the effective impedance of the entire basic circuit BL is reduced, thus the ratio of the effective impedance R is changed, the above V _P as shown in FIG. 4 It becomes a straight line having a different area at V _CC . Here, FIG. 4 shows an example in which V _G rapidly rises from 0 V to a certain voltage when V _CC is V _P or higher. However, when V _CC is changed from 0 V, V _G gradually rises from 0 V. , V _P may be a characteristic that the voltage level turns on the transistor Q at the points. In the case where V _G suddenly rises above a certain V _CC voltage, the circuit REF can be realized by cascading elements having a rectifying characteristic as shown in Japanese Patent Application No. 56-168698. In the example of gradually rising, the circuit REF can be realized by a simple resistance division circuit. The coefficient of V _L in FIG. 4L with respect to V _CC can be arbitrarily changed by the design of R and the transistor Q.

FIG. 5 shows another embodiment using the same basic circuit BL as that of FIG. FIG. 3 shows an example in which _VL is taken out from the V _CC side, whereas _VL is taken out from the ground side.
The characteristic of the output voltage V _G from the circuit REF is V _CC equal to or higher than V _P.
If the transistor Q is turned on at, the V _L is determined by the effective impedance of the entire basic circuit BL and the effective impedance R, so that V _L is as shown in FIG.

Incidentally, FIG. 3 and FIG.
Although S is taken as an example, a bipolar transistor may be used. Especially in the example of FIGS. 1 and 2, the entire chip is a MOS.
3 and FIG. 5, it is generally easier to design with MOS transistors, and when the entire chip is a bipolar transistor, it is better to use a bipolar transistor. However, in some cases, the chip may be composed of MOS transistors and bipolar transistors. In this case, it is clear that the circuits of FIGS. 3 and 5 can use MOS transistors, bipolar transistors, or a mixed type thereof, depending on the application. In addition, as an example of characteristics of the circuit REF, FIGS.
However, the present invention is not limited to this example, and V _L
The characteristics of the circuit REF may be determined according to the purpose of design. In addition V _P above V _CC, the purpose of changing the rate of change with respect to V _CC of V _L (the coefficients), as it is apparent in Japanese Patent Application Sho 56-168698, a load limiter circuit, or V _L is The purpose is to protect the applied fine elements from excessive voltage. The problem in this case is how to determine the normal operating voltage (nominal voltage) V _CC and, for example, the allowable maximum voltage V _CC that can be applied when measuring the voltage margin, with respect to V _P. See, for example in FIG. 4, the normal operating point V _CC below V _P, also it is possible to set the allowable voltage V _CC at the time of voltage margin measurement than V _P. As a result, V _L matches V _CC, and under normal operating conditions, the circuits A, A ′, and B of FIGS. 1 and 2 can be designed at a relatively high operating voltage, which facilitates the design. Further, as a result that the minute element is protected by the amount that the rate of change of V _L becomes small, the allowable voltage V _CC at the time of margin measurement can be made a large value. However, in some cases, it is possible to set the normal operating voltage V _CC to V _P or higher. In this case, since the change of V _L with respect to V _CC is small depending on the circuit, it is possible to design a circuit that operates more stably even if the external power supply V _CC changes. In the example of FIG. 6, it is obvious that the normal operating point V _P or higher must be set.

Next, referring to FIG. 3 as an example, an embodiment will be described in which the characteristics of V _L with respect to V _CC are variously changed based on the circuit of FIG. 7 and 8 are examples in which k basic circuits BL are connected in parallel to the effective impedance R of the circuit of FIG. However, BL ₀ turns on first at V _P0 , then BL ₁ turns on at V _P1 , and finally BL _K turns on at V _PK.
The internal circuit REF is set. Also, each V _L
Transistors in each BL manner coefficient change with respect to the V _CC is changed is designed. As V _CC becomes larger, impedance is successively added in parallel to R, so that the overall characteristic of V _L becomes concave at V _CC equal to or higher than V _P0 . This circuit is a concrete and general example of the example shown in FIG. 17 of Japanese Patent Application No. 56-168698, in which an impedance is inserted in parallel with R using a switch at the time of aging to increase the coefficient of V _L with respect to V _CC . It can be said that this is an example. However, in this embodiment, it has an advantage in that it occupies different coefficient of variation V _L at different V _P. This circuit is a practical circuit in terms of stability of operation during normal operation and effective aging in the method of FIG. For example, the normal V _CC operating point is set to a point where V _L does not change with respect to V _CC as much as possible, that is, a point where the change coefficient is small, for stable operation.
As described in No. 698, a large variation coefficient is set so that the stress voltage conditions of a large-sized transistor and a small-sized transistor are almost equal. For example, in FIG. 7, when using only BL ₀ and BL _1, 8, and reduce the change coefficient between the V _P0 (e.g. 2-3 V) and V _P1 (e.g. 6V), with respect to V _CC during which If the normal operating point (for example, 5V) is set, while the change coefficient is increased between V _P1 and V _P2 (for example, 7 to 9V), and the aging operating point (for example, V _CC = 8V) is set during this period. Good. It is obvious that a large number of BL ₂ and BL ₃ can be used to set the operating voltage point and the aging voltage point at arbitrary V _CC points depending on the purpose of design. Further, by using a large number of BLs, the V _L characteristic can be made smoother than V _CC , so that the operation of the internal circuit can be made more stable. Furthermore, since the V _CC voltage is high during aging, it is also effective to configure the voltage limiter circuit itself with high breakdown voltage transistors. For this purpose, for example, the voltage limiter circuit may be composed of large-sized transistors in the system shown in FIG.

9 and 10 show examples in which the basic circuit BL is connected in parallel to the ground side. By designing each BL as described above, the overall characteristic of V _L can be made convex with respect to V _CC . This characteristic is effective in protecting the circuit A'from an excessive V _L voltage in the system of FIG. 1, for example. Thus, when measuring the V _CC voltage margin of the entire chip, there is an advantage that a sufficiently high V _CC can be applied without destroying the fine elements.

It is possible to mix FIGS. 7 and 9 depending on the application. For example, the normal operating point is set to a point having a small change coefficient, and a point having a large change coefficient is set at the time of aging. These are realized by BL ₀ and BL ₁ of the circuit of FIG. Further, in order to prevent the permanent destruction of the element and reduce the coefficient of change again above V _{CC under} this aging condition, another BL is connected so as to operate in parallel with BL ₀ as in the circuit form of FIG. To do. By doing so, it is possible to design a circuit in which the element is not easily destroyed even when the aging condition is V _CC or more.

[0017] 11, 12, 'by connecting, certain V _CC voltage V' basic circuit BL in parallel with the circuit of FIG. 3 in _P or more is obtained by the rate of change of V _L negatively. That is, when V _CC is increased, first the circuit REF in BL is
When the output voltage V _G of V is higher than V _P , the transistor Q is turned on and the slope of V _L with respect to V _CC decreases. Then 'in _P, BL' is V _CC or V conductance of the transistor Q in advance to design 'is REF to turn on', and Q 'is set sufficiently larger design than the conductance of the Q For example, the V _L characteristic of the transistor Q ′ after conduction is B
Controlled by the characteristic of L ', V _L has a negative slope as shown in FIG.

The feature of this circuit is that if the V _L drop point is set below the breakdown voltage of the fine element, the fine element is completely protected from breakdown even if V _CC is boosted sufficiently. is there. In the circuit using the BL ₀ and BL ₁ in FIG. 7 as described above, V _CC or more V _CC corresponding to V _L at the time of aging
If the circuit is designed to operate in the area, even if V _CC rises above the aging condition, element destruction can be prevented.
Obviously, it is particularly effective.

Incidentally, also in FIG. 5, similarly to the example of FIG.
It is clear that an arbitrary V _L characteristic can be obtained by connecting BL in parallel.

Although the conceptual examples of the voltage limiter circuit have been described above, concrete circuit examples based on these concepts will be described below.

FIG. 13 is an embodiment of FIG. 3 using a bipolar transistor. The CVR is a fixed voltage circuit, and is a cascade connection of, for example, a Zener diode or a normal diode, whose both terminals have a substantially constant voltage regardless of V _CC . (A) is a well-known constant voltage circuit. For this, see Radio Science 19
1982, February issue, P.111 or Transistor Circuit Ana
lysis, Joyce and Clarke, Addison-Wesley Publish
For more information on ing Company, Ine., P.207. However, as it is, V _L is a constant voltage, which is inconvenient during aging. Therefore, (B) solves this drawback. Since the CVR and the resistor r are connected in series,
As shown in (C), V _L has a slope with respect to V _CC .

FIG. 14 shows another embodiment. (A) is a constant voltage power supply circuit using a well-known emitter follower,
Again, since V _L is a constant voltage, the resistor r is used as the solution in (B). As a result, the characteristic shown in FIG.

The examples shown in FIGS. 13 and 14 are particularly suitable for the system shown in FIG. That is, in FIG. 1, a large current normally flows through the input / output interface-related circuit, and accordingly, the voltage limiter is also required to have a large current driving capability. Clearly, a voltage limiter composed of bipolar transistors is suitable for this.

Next, based on FIGS. 3, 7, 9, and 11,
A specific example in which the voltage limiter is composed of MOS transistors will be described.

FIG. 15 is a specific characteristic example of FIG. 4 in which the characteristic of the slope m is provided at V _CC which is a certain voltage V ₀ or higher as V _L. Since the change in V _L is small at a voltage of V ₀ or higher,
The destruction of the fine element is less likely to occur.

[0026] It should be noted, are you with the V _L = V _CC at greater than or equal _to V ₀ of V _CC for the following reason. Generally, the speed of the MOST deteriorates as the operating voltage decreases due to the threshold voltage drop of the transistor. To prevent this, V greater than V ₀
It is desirable to make the voltage as high as possible on the low voltage side such as _CC . That is, V _CC is desirable.

FIG. 16 shows an embodiment of a specific circuit therefor and corresponds to the specific example of FIG.

The characteristic of this circuit is that the output voltage V _L is determined by the ratio of the conductances of the MOS transistors Q ₀ and Q _l.
The conductance of the OS transistor Q _l is controlled by V _L.

In this circuit, the control start voltage V ₀ and the slope m are obtained by changing the gate voltage V _G of Q ₀ to V _CC + V _th (o) (V
_{If th} (o) is the threshold voltage of MOSTQ ₀ ),

[0030]

[Equation 1]

Is represented as Where β (o) and β (l)
Is the channel conductance of Q ₀ and Q _l , V _th (i) (i
= 1 to n), V _th (l) is the MOS transistor Q _i (i
= 1 to n), the threshold voltage of Q _l , and n is the number of stages of Q _i .

Therefore, V ₀ , m is n, V _th (i),
It can be arbitrarily changed by V _th (l), β (l) / β (o). It was previously described that it is desirable to set V _L = V _{CC in} the case of V ₀ or more. However, in the case of V ₀ or less, since Q ₁ is off, V _L is determined by V ₀ . Therefore, for this purpose, V _G of Q ₀ must be a voltage higher than V _CC + V _th (o).

Note that FIG. 16 is slightly different from the actual circuit in order to simplify the calculation and improve the clarity of the description. That is, as a practical circuit, as shown in FIG. 27, which will be described later, it is necessary to connect the n-th transistor connected in cascade and a transistor having a similar connection to the ground. That is, a kind of diode is connected toward the ground. This is to prevent the nodes of the cascade-connected transistors from floating and leaving electric charges when V _CC is changed from a high voltage side to a low voltage law. It is omitted in the following embodiments for convenience of explanation.

FIG. 17 shows a characteristic example in which m '> m is set in order to effectively perform aging on a fine transistor at V ₀ ' or more, as described in Japanese Patent Application No. 56-168698. is there.

FIG. 18 shows an example of a specific circuit therefor. These correspond to the specific examples in FIGS. 7 and 8. The feature of this circuit is that by adding a circuit DCV2 similar to DCV1 between terminals 1 and 2 of the circuit shown in FIG. 16, the conductance of the load with respect to DCV1 is increased above V ₀ ′ and V _L To increase the slope of.

In this circuit, the second control start voltage V ₀ '
Is

[0037]

[Equation 2]

It is represented by The slope m 'is, MOS transistor Q ₀ and Q _l' is determined by the conductance ratio of the conductance of the sum and MOS transistor Q _l of. Here, V _th ′ (i) (i = 1 to n ′), V _th ′ (l)
Are MOS transistors Q _i ′ (i = 1 to
n '), _Ql ' threshold voltage.

Therefore, V ₀ ′, m ′ is n, n ′, β
(l), β ′ (l), V _th (i), V _th (l), V _th ′ (i), V
It can be changed arbitrarily by _th '(l). Here, β ′ (l) is the channel conductance of the MOS transistor Q _l ′.

FIG. 19 shows V ₀ ″ or more, or V ₀ ′.
To aged at two points "between the V ₀ which" more V _CC V ₀ as a characteristic example of the m '<m ".

FIG. 20 shows an embodiment of a specific circuit therefor. These correspond to the specific examples in FIGS. 7 and 8. The feature of this circuit is that by adding circuits DCV2 and DCV3 similar to the circuit DCV1 between the terminals 1 and 2 of the circuit shown in FIG. 16, the conductance of the load with respect to DCV1 is sequentially increased, and V ₀ ′ is increased. And V ₀ ″ are to increase the slope of V _L in two steps.

In this circuit, the second and third control start voltages V
₀ ′ and V ₀ ″ are respectively

[0043]

[Equation 3]

It is represented by Here, V _th ″ (i) (i =
1 to n ″) and V _th ″ (l) are the threshold voltages of the MOS transistors Q _i ″ (i = 1 to n ″) and Q _l ″, respectively, and the slope m ′ is the MOS transistor Q. ₀ and Q _l ′
, And the conductance of the MOS transistor Q _l , and m ″ is determined by the ratio of the sum of conductances of the MOS transistors Q ₀ , Q _l ′, Q _l ″ and the conductance of Q _l .

Therefore, V ₀ 'and m' are n, n ',
β (o), β (l), β '(l), V _th (i), V _th (l),
Depending on V _th ′ (i) and V _th ′ (l), also V ₀ ″ and m ″
Is n, n ', n ", β (o), β (l), β' (l), β"
(l), V _th (i), V _th (l), V _th ′ (i), V _th ′ (l),
It can be arbitrarily changed by V _th ″ (i) and V _th ″ (l). Here, β ″ (l) is the channel conductance of Q _l ″.

FIG. 21 shows an example of characteristics in which m> m 'in order to further enhance the effect of protecting the device at V ₀ ′ or more.

FIG. 22 shows an example of a specific circuit therefor. These correspond to the specific examples in FIGS. 9 and 10.
The feature of this circuit is that by adding a circuit DCV2 similar to DCV1 between the terminal 2 of the circuit shown in FIG. 16 and the ground, the conductance of the load with respect to the transistor Q ₀ is increased at V ₀ ′ and V _L To reduce the slope.

In this circuit, the second control start voltage V ₀ '
Is

[0049]

[Equation 4]

It is represented by The slope m 'has a conductance of Q _0, Q _l and Q _l' represented by the ratio of the sum of the conductance of.

Therefore, V ₀ 'and m' are n, n ',
β (o), β (l), β ′ (l), V _th (i), V _th (l), V
It can be arbitrarily changed by _th '(i) and _Vth ' (l). FIG. 23 shows a characteristic example in which m ′> m ″ is set again in order to give a protective effect to the element at V ₀ ″ or more.

FIG. 24 shows an embodiment of a specific circuit for this purpose. This corresponds to an example in which FIGS. 7 and 9 are mixed.
The feature of this circuit resides in that the gradient of V _L is increased or decreased at two points of V ₀ ′ and V ₀ ″ by mixing the examples of FIGS. 18 and 21.

In this circuit, the second and third control start voltages V
₀ ′ and V ₀ ″ are respectively

[0054]

[Equation 5]

It is represented by The slope m ′ is the ratio of the sum of the conductances of Q ₀ and Q _l ′ and the conductance of Q _l , and m ″ is the sum of the conductance of Q ₀ and Q _l ′ and Q _l
And the sum of the conductances of Q _l ″.

Therefore, V ₀ ′ and m ′ are n, n ′,
β (o), β (l), β '(l), V _th (i), V _th (l),
Depending on V _th ′ (i) and V _th ′ (l), also V ₀ ″ and m ″
Is n, n ', n ", β (o), β (l), β' (l), β"
(l), V _th (i), V _th (l), V _th ′ (i), V _th ′ (l),
It can be arbitrarily changed by V _th ″ (i) and V _th ″ (l).

In FIG. 25, the power source is lowered above V ₀ ′,
This is a characteristic example in which m '<0 in order to completely protect the element from a high voltage.

FIG. 26 shows an embodiment of a specific circuit therefor. These correspond to the specific examples in FIGS. 11 and 12.
The feature of this circuit is that DCV is applied to terminal 1 of the circuit shown in FIG.
2 by connecting the drain of Q ₁ ′, the drain of Q _l ′ to terminal 2 and the source of Q _l ′ to ground so that the conductance of Q _l ′ is controlled by V _CC , and Q _l ′.
Is larger than the conductance of the conductance Q ₀ of m ′ <0.

In this circuit, if the second control start voltage V ₀ ′ and the slope m ′ are β ′ (l) >> β (o),

[0060]

[Equation 6]

It is represented by

Therefore, V ₀ ′, m ′ is n ′,
It can be arbitrarily changed by V _th ′ (i), V _th ′ (l), β ′ (l) / β (o).

27 and 28 show a concrete example of this circuit and its characteristic example. The threshold values of the transistors are all 1 V, and V _G = V _CC + V _th (o). The numbers in parentheses show the values obtained by dividing the channel width of the transistor by the channel length, and FIG. 28 shows V _L with the value W _l / L _l of Q _l ′ as a parameter.

The gate voltage of Q ₀ is V
It has been assumed that _CC + V _th . This is because the calculation is simplified and the characteristics of the circuit are clearly described. However, this voltage does not essentially have to be V _CC + V _th, and can be arbitrarily set according to the design.

FIG. 29A is a specific circuit for boosting the gate voltage V _G to the power supply voltage V _CC or higher in the chip as described in FIG.

When the pulse φ _i of the amplitude V _CC from the oscillator OSC in the chip rises from 0 V to V _CC , the node _4'precharged to V _CC -V _th by Q ₁ '.
Is boosted to 2V _CC -V _th .

Along with this, the node 4 becomes the voltage 2 (V _CC -V _th ) dropped by V _{th due to} Q ₂ ′. Next, when φ _i becomes 0V and the node 2 rises to V _CC , the node 4 is further boosted to 3V _CC -2V _th . Therefore, the node 5 has a voltage 3 (V _CC -V _th ) which is lowered by V _th by Q ₂ . Since Q ₂ ′ and Q ₂ are a kind of diode, if this cycle is continued many times, V 2
_G is a DC voltage of 3 (V _CC -V _th ). CP1, C
A higher voltage V _G can be obtained by connecting a plurality of P2 circuits. Here, the reason for using two stages is as follows.
That is, _assuming that V _CC is as low as 2.5 V and V _th is 1 V, V _G = 2 (V _CC −V _th ) in one stage, so V _G =
It becomes 3V. However, in this case, the source voltage V _L of Q ₀ in FIG. 15 becomes 2 V which is lower than V _CC . On the other hand, when the number of stages is two, V _G = 3 (V _CC −V _th ), and thus V _G = 4.5V. Therefore, since V _L can be V _CC , V _L = V _CC can be _achieved at V ₀ or higher as shown in FIG.
However, conversely, the higher the voltage of V _CC , the higher the voltage of V _G, which may damage the associated transistor. Therefore, some V _G control circuit is required on the high voltage side of V _CC .

[0068] Figure 30, V _G ~ 3 at the low voltage side of the V _CC (V
The _CC -V _th) and high voltage, moreover, in order to protect the transistors associated with the high voltage side of V _CC, V _CC + 2V _th
It is an example. Here, the circuits described so far, for example, the entire circuits of FIGS. 16, 18, 20, 22, 24, and 26 are also indicated by LM1 as the load of V _G. Protection circuit CL1 is, V _G is fixed at the result V _CC + 2V _th current flows through Q _1, Q ₂ when trying to be more V _CC + 2V _th. In this circuit, V _CC is 3 CL1 is operated
The V _CC = 5 / 2V _th from _{(V CC -V th) = V} CC + 2V th.

FIG. 31 shows a concrete circuit of INV1 and INV2. The output pulse φ ₀ is applied to CP1 and CP2.

The oscillator circuit OSC can be constructed by a circuit built in the chip.
_This is an example in which the V _BB generating circuit built in the chip is used to provide _BB . This advantage is effective in reducing the chip area because it is not necessary to newly design an oscillator circuit.
Further, when the power supply voltage V _{CC is} turned on, V _BB is generated only when V _CC reaches a certain value and the oscillator in OSC 'oscillates. However, V _L is also generated almost at the same time, so that as a load of V _L Since V _L is applied to the connected transistor while V _BB is applied, the operation of each transistor is normally performed. If V _L is applied to each transistor when V _BB is 0 V, the V _th of each transistor is not a normal value, so an excessive current flows or the stress condition to the transistor becomes severe and the transistor is destroyed. There are also things to do.

Next, a concrete example of the buffer circuit will be described. As the load of the voltage limiter, there is a case where a large capacity or a load with large load fluctuation is attached. In this case, it is necessary to drive these large loads through a buffer circuit having a large driving capacity. As a means for realizing this, a usual method is conceivable in which the load is driven via one transistor having a large driving capability, that is, a large W / L as shown in FIG. However, in this method, as shown in FIG. 34, since there is a voltage drop of V _th on the low voltage side of V _CC , the performance deteriorates. FIG. 35 shows a specific example of a buffer circuit having a large driving capability without V _th drop. V _PP is V _L + V _th
If R _P is set to be much larger than the equivalent on-resistance of Q ₁ , the gate voltage of Q ₂ becomes V _L + V _th .
Therefore, the source voltage V _L1 of Q ₂ becomes equal to V _L. Q
_A desired buffer circuit can be obtained by increasing the W / L of ₂ . Here, since V _L becomes V _CC when V _CC is on the low voltage side, V _PP must be V _CC + V _th or more. The circuit shown in FIG. 29 can be used as a circuit for this purpose. As a connection, the node 5 in FIG. 29 may be connected to the drain of Q ₁ in FIG. Here, in order to make the effective output impedance viewed from the node 5 sufficiently larger than the equivalent ON resistance of Q ₁ in FIG. 35, for example, W / L of Q ₂ in FIG. 29, or the magnitude of C _B , or The oscillation frequency of the OSC may be adjusted appropriately.

Depending on the load, it may be necessary to apply V _L to the drain of the transistor forming a part of the load and V _L + V _th to the gate to prevent V _th drop and to operate at high speed. FIG. 36 shows an embodiment for this purpose. As LM ₁ , for example, in the circuit of FIG. 16, V _L1 becomes equal to V _L as described above, and the gate voltage of Q ₄ is V _L.
L + 2V _th So V _L2 becomes V _L + V _th. Where Q ₆ ,
The role of Q ₇ is to prevent unnecessary charges from remaining in V _L1 during transient changes in V _CC . Q ₆ is connected to operate at greater than or equal to V ₀ of V _CC, also Q ₇ illustrates the inside LM1 behave in V ₀ -V _th or on V _CC. Here, Q _6, W / L of Q ₇ are chosen sufficiently small as compared to Q _2, V due to the addition of Q _6, Q ₇
The effect on _L is minimized. Here, it was previously mentioned that Q ₇ operates in the region above V ₀ . In the region of V _{0 and} above, Q ₂ and Q ₄ are operating in the non-saturated region (V _GS −V _th > V
_{Since DS} and V _{GS are the} gate-source voltage and V _{DS is the} drain-source voltage, the excess charge is discharged to V _CC through Q ₂ and Q ₄ , so Q ₇ is theoretically Is unnecessary, but the ON resistance of Q ₂ and Q ₄ becomes unnecessarily large in the vicinity of V _CC to V ₀ , and the effect may not be expected. Therefore, by adding this Q ₇ , the stable value of V _L1 can be obtained in a wide range from the region where V _CC is V ₀ or more (V ₀ −V _th ) to the region where the limiter is operating normally. Can be obtained.

It should be noted that the role of Q ₅ is that when V _L1 tries to change negatively with respect to V _L2 , a current flows through Q ₅ and V _L2
And V _L1 are kept constant. Further, in this embodiment, an example of V _L and V _L + V _th has been described, but if the pair of Q ₁ and Q ₂ or the pair of Q ₃ and Q ₄ is connected in cascade, the voltage difference between V _L1 and A voltage that is an integral multiple of V _th can be generated.

FIG. 37 shows another buffer circuit connected to the output stage of FIGS. 35 and 36 in order to further improve the driving capability of the buffer circuit of FIGS. By connecting a buffer circuit having a larger driving capacity in this way, a large load capacity can be driven. First, V _L1 becomes V _L1 + 2V _th and V _L1 + V _th at the nodes 4 and 2, but eventually becomes V _DP at the level of V _{L1 at} the node 5 by Q ₄ . The problem here is the load driving capability of Q ₄ for charging the large capacity C _D in the load LC1 at high speed. In order to improve this capability, it is necessary to boost the voltage of the node 2 which is the gate of Q ₄ during the time period for charging the load. Transistors for this purpose are Q _{6 to} Q ₁₁ , and capacitors are C ₁ and C ₂ . Node 6, which is discharged by Q ₁₃ when φ ₂ is on,
The next φ ₁ is turned on and is charged by Q ₁₂ and Q ₄ . At this time, node 2 which is V _L1 + 2V _th and node 3 which is V _L1
Is boosted by turning on φ ₁ . By this, Q ₁₀ ,
Since the conductance of Q ₁₁ becomes large, the boosted voltage of node 2 is discharged to the level of V _L1 + V _th by Q ₁₀ and Q ₁₁ . Here, if the boosted time larger than the charging time of the C _D by Q _4, Q _12, C _D will be charged at a high speed. Note that Q ₆ is a transistor that disconnects the node 3 and the node 1 when the node 3 is boosted by φ ₁ . Further, when φ ₂ is on, Q _{7 to} Q ₉ are turned off if the condition of V _L1 ≦ 3V _th is satisfied, so the gate of Q ₁₁ is V _th or less and Q ₁₁ is turned off. Therefore,
Since no current flows through Q ₃ , Q ₁₀ and Q ₁₁ , power consumption can be reduced. Further, in order to reduce the power consumption in the case of V _L1 > 3V _th , the ON resistance of Q ₆ may be increased to reduce the current. The voltage of 3 at this time has a stable value of approximately 3 V _th . As a result, the boosting characteristic of the node 3 becomes stable, and as a result, the operation of the entire circuit can be stabilized.

Since the sources and gates of Q ₇ and Q ₁₀ are commonly connected, the bias conditions for the gates are exactly the same. Therefore,

[0076]

[Equation 7]

By doing so, the boosting characteristics of the nodes 2 and 3 can be made completely equal, and the circuit can be easily designed. That is, one of the features of this embodiment is that the boosting characteristic of the node 2 can be automatically controlled by the boosting characteristic of the node 3, and by doing so, the voltage from the node 2 to V _SS when the boosting is not performed is performed. It is possible to reduce the direct current path to and to reduce power consumption.

Here, Q ₅ has a function of discharging the extra electric charge of the node 2 when Q ₁₀ is OFF.

Various modifications can be considered for the embodiment shown in FIG. That is, the drain of Q ₆ in FIG. 37 is connected to V _L1 so as to stabilize the boosting characteristics of the nodes 2 and 3 as much as possible, but connected to V _CC to reduce the load on V _L1 . It is also possible. Similarly, in order to stabilize the boosting characteristics of the nodes 2 and 3, the same operating condition as Q ₇ is used.
_{Although 10} is provided, the configuration may be such that this is removed and nodes 2 and 9 are directly connected, and the source of Q ₇ and node 9 are disconnected. In this case, since the relationship between Q ₉ and Q _{11 is} the relationship between Q ₇ and Q ₁₀ described above, the boosting characteristic can be designed similarly, which is effective in reducing the circuit occupation area. Furthermore, here, a three-stage connection configuration of Q ₇ , Q ₈ , and Q ₉ is used, but this has the capacity of C ₂ for reducing the power consumption described above, for example, ISSCC72 Dig. Of Tech. Papers, This is a consideration for efficient formation in a small area by using the inversion layer capacitance between the gate and the source / drain of the MOST, which is known in P.14. That is, in order to use the inversion layer capacitance, it is necessary to apply a voltage higher than the gate voltage to the source and drain by V _th or more. Therefore, when C ₂ is formed using a MOST having a low V _th or a normal capacitance, the number of connections of Q _{7 to} Q ₉ can be reduced to two or one.

The buffer circuit shown in FIG.
It is particularly essential in the LSI system as shown in (4). That is, generally, the voltage limiter for generating V _L in FIGS. 1 and 2 is required to have a particularly large ability to supply the current because the circuit current in the circuits A, A ′ and B flows toward the ground. Therefore, if the entire circuit including the above-mentioned FIG. 37 is regarded as the voltage limiter of FIGS.
Can be used for I.

In the embodiment described so far, FIG.
As shown in FIG. 18, when operated at V _CC higher than V ₀ ,
Since the actual circuit is diode-connected as shown in FIG. 27, current flows through Q ₁ ′ to Q _S ′, which increases power consumption. This increase in power consumption becomes a problem when an LSI power supply, that is, an externally applied power supply voltage is backed up by a battery. That is, in a device that backs up with a battery when the normal external power is turned off,
If the power consumption of the battery itself is large, the current capacity of the battery is small, and the backup time is limited. Therefore, during the battery backup period, if V _{CC supplied} from the battery is set to V ₀ or less, Q _{1 to} Q _S
Since no current flows through the device, the backup time can be extended by this amount. Alternatively, the number of stages of Q _{1 to} Q _S can be determined so that V ₀ is higher than the battery power supply voltage V _{CC for} backup.

The normal operating power supply voltage V _CC is changed to V _CC > V
_Instead of selecting ₀ , V _CC <V ₀ can be set. By doing so, under normal V _CC conditions, current does not flow in Q _{1 to} Q _n , so that the power can be reduced and the design can be performed while avoiding the region where the relationship between V _CC and V _L is a broken line. It has the advantage of being easy. This is because when designing in the broken line region, for example, when V _L is used as a part of a certain circuit, an imbalance in the characteristics relating to V _CC occurs in the circuit that directly uses V _CC , resulting in unstable operation. Sometimes, V
This is because if _CC <V ₀ , this can be avoided.

The specific embodiments in which the voltage limiter is composed of MOS transistors have been described above. These are mainly examples in which the threshold voltage V _th is positive, that is, when an enhancement type MOS transistor is used. However, as disclosed in Japanese Patent Application No. 56-168698, FIG. 16, V _th is negative. That is, it is of course possible to use a depletion type MOS transistor. Figure 1
In the sixth embodiment, in order to set V _L = V _{CC in} the region of V _CC < V ₀ as shown in FIG. 15, the gate voltage of Q ₀ is V _G > V
_Although it is necessary to use _CC + V _th (O) and the circuit of FIG. 29 may be used as the V _G generating circuit for this purpose, the circuit can be further simplified by using the depletion type MOS transistor. FIG. 39 shows a concrete example thereof, in which Q ₀ is a depletion type MO as compared with FIG.
The difference is that the gate of the S transistor Q ₀ ′ is connected to the terminal 2. By doing this, V of Q ₀ ′
_{Since th} ′ (O) is negative, Q ₀ ′ is always in the ON state, and without using the V _G generation circuit as shown in FIG.
The desired characteristics shown in FIG. 5 can be realized. Not only can the circuit configuration and simplified as described above in this embodiment, Q ₀ 'the current I flowing through the (Q _0') is _{I (Q 0 ') = β'} (O) · V
_th (O) as ^{2/2, β'(O)} ( channel conductance), in order to be V _th '(O) (threshold voltage) only determined by the constant current, a feature capable of obtaining stable characteristics Have.
Although the present embodiment is based on FIG. 16, the Q
_It can be applied as it is by replacing ₀ with Q ₀ ′ as in the present embodiment and connecting the gate to the terminal 2.

FIG. 40 shows one depletion type MOS.
This is an example in which a buffer circuit is configured by using transistors, and FIG. 41 shows its characteristics. Figure 3 mentioned earlier
3 has the same circuit configuration, but is different in that the MOS transistor is changed from the enhancement type to the depletion type. As shown in FIG. 41, the output V _L ′ of this buffer circuit is bent from a point P at which the difference between V _CC and V _L becomes equal to the absolute value | V _thD | of the threshold voltage V _thD of the MOS transistor. After that, the voltage becomes higher than V _L by | V _thD |. Therefore, V _L may be set lower than the desired value by | V _thD |. In the present embodiment, with a simple circuit configuration, as in the characteristic of the embodiment of FIG. 33 shown in FIG. 34, within the range of V _CC < V ₀ , only an output lower by V _th than V _CC can be obtained. It has the feature that it can eliminate the problem.

[0085]

As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit having an internal voltage generating means for supplying a stable internal voltage.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention.

FIG. 2 shows an embodiment of the present invention.

FIG. 3 shows an embodiment of the present invention.

FIG. 4 shows characteristics of the embodiment of FIG.

FIG. 5 shows an embodiment of the present invention.

6 shows the characteristics of the embodiment of FIG.

FIG. 7 shows an embodiment of the present invention.

8 shows the characteristics of the embodiment of FIG.

FIG. 9 shows an embodiment of the present invention.

10 shows characteristics of the embodiment of FIG.

FIG. 11 shows an embodiment of the present invention.

FIG. 12 shows characteristics of the embodiment of FIG.

FIG. 13 shows an embodiment of the present invention.

FIG. 14 shows an embodiment of the present invention.

FIG. 15 shows characteristics of the embodiment of FIG.

FIG. 16 shows an example of the present invention.

FIG. 17 shows characteristics of the embodiment of FIG.

FIG. 18 shows an example of the present invention.

FIG. 19 shows characteristics of the embodiment of FIG.

FIG. 20 shows an example of the present invention.

FIG. 21 shows the characteristics of the embodiment of FIG.

FIG. 22 shows an example of the present invention.

FIG. 23 shows the characteristics of the embodiment of FIG.

FIG. 24 shows an example of the present invention.

25 shows the characteristics of the embodiment of FIG.

FIG. 26 shows an example of the present invention.

FIG. 27 shows an example of the present invention.

28 shows the characteristics of the embodiment of FIG. 27.

FIG. 29 shows an example of the present invention.

FIG. 30 shows an example of the present invention.

FIG. 31 shows an example of the present invention.

FIG. 32 shows an example of the present invention.

FIG. 33 shows an embodiment of the present invention.

FIG. 34 shows the characteristics of the embodiment of FIG. 33.

FIG. 35 shows an example of the present invention.

FIG. 36 shows an example of the present invention.

FIG. 37 shows an embodiment of the present invention.

38 shows the characteristics of the embodiment of FIG. 37.

FIG. 39 shows an example of the present invention.

FIG. 40 shows an example of the present invention.

41 shows the characteristics of the embodiment of FIG. 40.

[Explanation of symbols]

Q ₀ , Q ₁ , Q ₂ , Q ₁ ′, Q _S , Q _S ′, Q _l , Q _l ′, ... M
OS transistor, 13 ... Voltage limiter.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hitoshi Tanaka 1479 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Micro Computer Engineering Co., Ltd. In-house

Claims (2)

[Claims] 1. An internal circuit including a MOS transistor and an external power supply voltage supplied from outside the chip are applied, and when the external power supply voltage increases, the external power supply voltage changes to a first voltage up to a first voltage. The second voltage from the first voltage to the second voltage, and the second voltage from the first voltage to the second voltage.
Output an internal voltage that changes at a third rate of change that is greater than the second rate of change, and the internal voltage that changes at the third rate of change can be applied to the internal circuit during a test. Generating means inside the chip, and applying a voltage based on the internal voltage of the internal voltage generating means and the reference voltage to a control input of the negative feedback amplifying means to amplify the internal voltage. A semiconductor integrated circuit characterized in that it is generated from the output of the means with a relatively low output impedance. 2. The semiconductor integrated circuit according to claim 1, wherein the reference voltage is set by a total of threshold voltages due to cascade connection of a plurality of MOS transistors.