JPH0695364A - Mask for exposure and formation of pattern - Google Patents

Abstract

PURPOSE:To enable the good formation of patterns even if ruggedness exists in the perpendicular direction of a substrate by forming lancing parts or overhanging parts for correcting the pattern formation in accordance with the positive/negative characteristics of a resist on mask patterns in alignment to the positions of the rugged parts. CONSTITUTION:The semiconductor substrate which is a material to be worked has the ruggedness on the substrate in the direction perpendicular to the plane thereof. The material to be worked having such structure is required to be formed deep in apertures and the good patterns are not always obtainable with this material even by a self-alignment contact technique. The case of use of the positive type resist is shown in this embodiment. Namely, this mask for exposure is a chromium reticule of the structure having fine slit between the two mask patterns 1. The lancing parts 2 are put into the parts just corresponding to the recessed parts of the substrate of this slit and the point corresponding to the bottom parts of the level difference. As a result, even the parts of the recessed parts at the level difference of the substrate are cleanly blanked and the good patterning is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure mask and a pattern forming method. INDUSTRIAL APPLICABILITY The present invention can be used, for example, for forming a resist pattern when forming a wiring pattern of an electronic material (such as a semiconductor device) and other various patterns.

[0002]

2. Description of the Related Art For the formation of various patterns, finer patterns are required year by year. For example, in the field of semiconductor devices, the minimum processing dimension of semiconductor integrated circuits is approaching 0.35 μm. Along with this, a fine processing technique such as KrF excimer laser lithography has attracted attention. This is because a higher resolution can be expected by using light with a shorter wavelength.

On the other hand, the requirements for the overlay resolution as well as the minimum resolution have become strict. For example,
The reality is that high precision of 0.1 μm or less is being demanded.

On the other hand, there is a contact technique called self-aligned contact, in which the alignment is self-aligned. With this technique,
It is possible to accurately align a layer (processed layer) that requires superposition that is higher than the alignment accuracy of the stepper (projection exposure apparatus).

In this self-aligned contact technique, as shown in FIG. 3A, an offset oxide film 14a is previously formed on a gate forming film 12a made of poly-Si or the like, and patterned to form a gate electrode 12 and an oxide film. After forming the film 14 to form the structure of FIG. 3B, the side wall 15 is attached (FIG. 3C), and then the interlayer film 16 is attached, and then contacts are opened to form the film of the next electrode. It is attached and patterned.

[0006]

However, in the case of the self-aligned contact, the element spacing between the adjacent elements is narrowed, so that a pattern is formed just at right angles to the narrow slit, and a patterning defect is likely to occur. There is a problem. In particular, as shown in FIG. 3, the gate electrode 1
This problem is large when the silicide layer 13 made of tungsten silicide or the like is provided between the second layer 2 and the oxide film 14 so that the entire thickness is increased and vertical irregularities are formed on the substrate 11. For example, there is a case where a resist residue or the like is generated in a deep step portion caused by the unevenness, and good patterning cannot be achieved.

The present invention solves the above problems, and when unevenness in the vertical direction (the vertical direction in this specification means that it is perpendicular to the substrate surface) exists on the substrate, It is an object of the present invention to provide an exposure mask that can perform good pattern formation and a pattern formation method.

[0008]

According to the invention of claim 1 of the present application, there is provided a step of forming an opening on the surface of a semiconductor substrate, depositing a thin film on the surface of the semiconductor substrate, forming a resist, and patterning. In the exposure mask to be used, the mask pattern is provided with a notch or protrusion for correction of the pattern shape in accordance with the positive / negative characteristics of the resist in accordance with the position of the vertical unevenness due to the opening of the semiconductor substrate. An exposure mask characterized by being formed,
This achieves the above object.

According to the invention of claim 2 of the present application, in a pattern forming method of patterning by exposure on a semiconductor substrate having an uneven portion in the vertical direction on the surface, a mask for exposure is formed on the surface of the semiconductor substrate in the vertical direction. The pattern forming method is characterized by using an exposure mask in which a correction notch or a protrusion for pattern formation is formed as a mask pattern according to the positive / negative characteristics of a resist in accordance with the position of the uneven portion. Thus, the above object is achieved.

In the present invention, even when the difficult work of patterning a fine portion having a deep step is performed (for example, when it is necessary to pattern the second-layer polysilicon in the deep portion), the processing position becomes deep. A notch (positive type) or a protrusion (negative type) is formed in the portion of the mask pattern corresponding to (3), which enables good patterning.

With the above-mentioned structure of the present invention, it is possible to pattern a slit having a minimum dimension orthogonal to a large step with good resolution.

In the present invention, it is preferable that the size of the cut or protrusion is 1/3 to 3/4 of the minimum pattern rule. In the example of FIG. 1, the cut length of the cut portion 2 is t ₁ , and in the example of FIG. 2, the projected lengths t ₃ , t ₅ , and t ₈ of the projecting portion 31 are 1 of the minimum pattern rule.
It is good that it is / 3 to 3/4. If it exceeds 3/4, the pattern may be transferred as it is to the notch or protrusion. If it is 1/3 or less, the effect of cutting or protruding is small.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. However, as a matter of course, the present invention is not limited to the following examples.

Example 1 In this example, the present invention was applied to pattern formation in a work material (semiconductor substrate) having a shape shown in FIGS. 4 and 5.
A semiconductor substrate, which is a material to be processed, has irregularities on the substrate in a direction perpendicular to the plane. FIG. 4 is a view of this from above, and in particular, the hatched portions 1a, 1b, 1c are shown.
The portion indicated by is the bottom (concave portion), and the other portion is the top (convex portion). In this example, the width L of the convex portion
₁ , L ₂ is 2 μm, and the width L ₃ of the recess is 0.2 μm.

FIG. 5 is a sectional view of a semiconductor substrate which is a material to be processed. As shown in FIG. 5, a semiconductor substrate 1 made of silicon or the like
On top of the gate electrode 12 of polysilicon or polysilicon / tungsten silicide structure.
000 Å) is formed, and as a result, irregularities perpendicular to the substrate surface are formed on the substrate. In FIG. 5, 16 is plasma TE
It is a SiO ₂ film (2000 Å thickness) formed by OS or the like. Reference numeral 17 denotes a second-layer polysilicon film, which has a thickness of 500 Å. The total film thickness D on the semiconductor substrate 11 is
It is 3000Å. Reflecting the step due to the gate electrode 12 which is the first-layer polysilicon, the convex portion (width W ₁
And a concave portion (also referred to as W ₂ ).
W ₁ is 2 μm and W ₂ is 0.2 μm.
It corresponds to ₁ , L ₂ and L ₃ .

In the material to be processed having such a structure, it is necessary to form the opening deeply, and it is not always possible to perform good patterning even by the self-aligned contact technique.

In this example, patterning was performed using a positive resist. Here, the positive type as shown in FIG. 1 (here, the type used when a positive type resist is used)
Was used.

That is, this exposure mask is a chrome reticle having a structure having a thin slit between two mask patterns 1 and 1 as shown in FIG. 1, and this slit corresponds to the concave portion of the substrate. A notch 2 was formed by making a notch at a portion corresponding to the bottom of the step. The portion to which the cutout portion 2 corresponds corresponds to the concave portion 1b in FIG. FIG. 6 is an image diagram showing an overlapping state of the exposure mask and the material to be exposed. As shown in the figure, the notch portion of the mask pattern is just formed at the portion where the concave portion 1b crosses the mask pattern P (pattern 1 in FIG. 1). 2 is formed.

In the present example, the size of the notch 2 is 0.25 μm in terms of the size on the wafer (material to be exposed). That is, t ₁ and t _{2 in} FIG. 1 were set to 0.25 μm. On an actual reticle (mask), it is 5 times this.
This is because the reduction projection exposure is performed to ⅕. t ₁ and t ₂ do not necessarily have to have the same size.

In terms of the overlay image diagram, the dimensions are
The mask pattern length A was 4 μm, the inter-pattern slit width B was 0.4 μm, and the distance C between the mask pattern and the adjacent recess 1c was 1.5 μm. All are the dimensions on the wafer (exposed material).

In this example, the exposure mask is formed in the form of a so-called chrome reticle in which a pattern is formed by chrome on a quartz substrate.

In this embodiment, the contacts are formed in self alignment with respect to the substrate having the sectional shape shown in FIG. To obtain the shape shown in FIG. 5, the steps shown in FIG.

In this example, a substrate (5-inch silicon wafer) having a step shown in FIG. 5 was baked at 200 ° C. for 1 minute and then treated with HMDS (hexamethyldisilazane) at room temperature for 1 minute. On top of this, a diazonaphthoquinone-based positive resist for excimer, FH-EX1
(Manufactured by Fuji Hunt Techlogy Co., Ltd.) was spin-coated at a film thickness of 0.7 μm and then baked at 90 ° C. for 90 seconds. This was exposed through a reticle having the above mask pattern. The apparatus used is the KrF reduction projection exposure apparatus NSR150.
5EX (manufactured by Nikon, NA: 0.42, σ: 0.5). The exposure amount was 130 mJ / cm ² . 110 this
After PEB (post-exposure bake) at 90 ° C. for 90 seconds, 1 with a dedicated developer HPRD-402X for the resist.
Developed for minutes. Here, paddle (liquid pour) development was used.

As a result of the above, the portion (bottom portion) of the stepped concave portion of the substrate was also removed neatly and was well resolved. As a result, good patterning could be realized.

Comparative Example 1 A mask similar to that shown in FIG. 1 was used, but a reticle in which the notch 2 was not formed in the mask pattern 1 was used, and exposure was performed in the same manner as in Example 1 to form a pattern.

As a result, the bottom was not completely removed, and good patterning could not be achieved.

Example 2 In this example, patterning was performed using a negative resist. The mask used in this example is a negative type mask (here, it means the type used when using a negative type resist).

In the mask of this example, the mask pattern 1 has a protrusion 31 as shown in FIG. Since it is a negative type here, the mask pattern 1 is a blank except for chrome, and has a shape in which chrome surrounds it. The protrusion 31 was formed outside both patterns 1 and 1. Also, a small protrusion 32 was formed in the slit direction between the patterns 1 and 1.

Here, the dimensions of the protrusions 31 and 32 are t
₃ = t ₄ = t ₆ = 0.4 μm, and t ₅ = 0.1 μm of the small protrusion 32.

FIG. 2B shows the smaller protrusion 3
In the example without 2, t ₇ = t ₈ = 0.4 μm.

In this example, the mask shown in FIG. 2A is used, and after the same processing as in Example 1, the negative resist SA is used.
L601 (Chipley's chemically amplified resist) 0.7
The film was formed with a thickness of μm to form a pattern. The developer is
Development was performed for 10 minutes using MF622 corresponding to the resist.

As a result, the resist comes off in a good shape,
It was possible if patterning with an excellent shape was possible.

When the same process was performed using the exposure mask of FIG. 2 (b), it was observed that there was a tendency for the resist to slightly elute in the recesses corresponding to the slits between the mask patterns 1 and 1. The same patterning as that using the exposure mask of 1 (a) could be performed.

COMPARATIVE EXAMPLE 2 The same mask as that of FIG. 2 was used, but the protrusions 31 and 32 were not formed. As a result, the pattern was excessively removed at the bottom portion, that is, the resist was developed in the concave portion. There was a large tendency to dissolve and disappear due to too much, and too much was removed, and good patterning could not be achieved.

[0035]

According to the exposure mask and the pattern forming method of the present invention, a good pattern can be formed even when vertical irregularities are present on the substrate which is the workpiece.

[Brief description of drawings]

FIG. 1 is a diagram showing a mask pattern according to a first embodiment.

FIG. 2 is a diagram showing a mask pattern according to a second embodiment.

FIG. 3 is a sectional view showing a process of forming a substrate to which the present invention is applicable.

FIG. 4 is a diagram showing an upper surface of a material to be processed in the example.

FIG. 5 is a view showing a cross section of a material to be processed in an example.

FIG. 6 is an image diagram showing the superposition of the exposure mask and the workpiece in the example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Mask pattern 2 Cut part 31,32 Projection part 1a, 1b, 1c Recessed part

Claims (2)

[Claims] 1. An exposure mask used in the step of forming an opening on the surface of a semiconductor substrate, depositing a thin film on the surface of the semiconductor substrate, and then forming a resist and patterning the film. An exposure mask, characterized in that a notch or protrusion for correction of the pattern shape is formed in the mask pattern in accordance with the position of the uneven portion in the direction according to the positive / negative characteristics of the resist. 2. A pattern forming method for performing patterning by exposure on a semiconductor substrate having a vertical uneven portion on a surface thereof, wherein a mask for exposure is provided in accordance with the position of the vertical uneven portion on the semiconductor substrate surface. A pattern forming method characterized in that an exposure mask in which a correction notch or protrusion for pattern formation is formed according to the positive / negative characteristics of a resist is used as a mask pattern.