JPH0695317B2 - Prefetch control method for cache memory - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a prefetch control method for loading a requested block data and a next block data when a requested block data is not found in a cache memory.

"Prior Art" By installing a small-capacity, high-speed buffer memory between the processor and the main memory, it is possible to speed up the effective access time of the main memory by computing survey (Computing Survey) Vol. 14 3 It is generally well known as detailed in Issue No. 1982, pages 473-530.

This method is generally called a cache memory and is widely used in computer systems. This is because the memory access of the program executed on the computer system has the property of locality. When accessing the main memory from the processor, a continuous memory of a certain size including the accessed word is used. By fetching the contents of the specified memory location (usually called a block) from the main memory into the cache memory, most of the memory access is done by accessing the cache memory at high speed and reducing the access to main memory at low speed. be able to.

"Problems to be Solved by the Invention" The size of a block in a cache memory (hereinafter referred to as a block size) is fixed by a device in a conventional large computer or mini computer. This is because each device was designed from the CPU (Central Processing Unit) to the cache memory and main memory, and it suffices to select the optimum value for that device.

However, when considering a general-purpose cache memory chip that is externally used in a general-purpose microcomputer, this cache memory chip is used in various devices, and thus it is difficult to set the optimum value of the block size. . For example, a larger block size improves the hit rate, but on the other hand, the number of bus cycles during the block transfer from the main memory to the cache memory increases and the bus usage rate increases, so the performance of the entire device does not improve. Such a surface comes out.

In addition, when the data transfer speed from the main memory to the cache memory is slow, the waiting time of the CPU due to the block transfer increases, and the average access time does not improve.

In this case, set the block size small,
It is known that a method of performing prefetch to fetch the next block to increase the apparent block size is effective for highly local access (for example, instruction fetch).

Since a general-purpose cache memory chip is used in various devices, what kind of access has a prefetch effect depends on the device. Therefore, it is preferable to dynamically switch the access to the processor for each access of the processor as to whether or not to perform the prefetch.

"Means for Solving Problems" The present invention relates to, as a one-chip cache memory, a directory for managing blocks held by the chip on the same chip, a data memory for holding block data, and a processor. Built-in prefetch circuit (adder) for calculating the next block address of the block accessed from, and related control circuit, and memory access as input / output terminal for communication of memory access request from processor to cache memory Request of
Processor access control signal terminal for completion signal etc.,
Memory access as a processor address signal terminal for a memory address from the processor, a processor data signal terminal for exchanging data with the processor, and an input / output terminal for communication of a memory access request from the cache memory to the main memory Control signal terminal, memory address signal terminal, memory data signal terminal, if there is no block for which a memory access is requested in the cache memory chip, control whether to load the block up to the next block It has a prefetch pin, and when the memory access request from the processor finds the requested block data in its own chip, it makes an access in the own chip and the requested block data is not found in the own chip. And the pre When the fetch terminal is applied, the requested block data and the next block data are loaded, and when the prefetch terminal is not applied, only the requested block data is loaded. To do.

[Embodiment] The configuration of a cache memory chip in an embodiment of the present invention will be described with reference to FIG. In this embodiment, the cache memory chip is not shown in the figure as a terminal, but it is provided with terminals for power supply, ground, clock, etc., and further, as a terminal for communication with the processor, an access request to the memory from the processor. Has a processor access pin PC for notification of access to the cache memory and completion of access to the cache memory, a processor address pin PA for notifying memory addresses, a processor data pin PD for exchanging data, and communication with the main memory. Similarly, as a terminal for memory access terminal MC, memory address terminal
It has MA and memory data terminal MD. In addition to this, the cache memory chip, if a block does not exist in this cache memory chip, prefetch pin PRF for controlling whether to load the block next to the block that does not exist from the main memory. have.

The processor address terminal PA is connected to the input of the address register 11, and the output of the block address part of the address register 11 is applied to the prefetch circuit 12 as well as to the directory 14 and the memory address terminal MA through the multiplexer 13. Has been done.

Matching address output of directory 14 FBA is data memory 1
It is applied to 5 as a block address and also applied to the replacement circuit 16. The block address on the data memory 15 to be replaced, which is generated by the replacement circuit 16, is applied to the directory 14 as a write address. The coincidence detection signal F from the directory 14 is applied to the control circuit 7. Prefetch terminal
The input from the PRF is also applied to the control circuit 17.
The read data register 18 is connected to the processor data terminal PD.
The output side of and the input side of the write data register 19 are connected. The read data from the data memory 15 is applied to the input of the read data register 18, the output of the write data register 19 is applied to the data memory 15 as write data, and the memory data terminal MD is at the input side of the write data register 19. It is connected to the.

The control circuit 17 is a control circuit for performing corresponding processing in response to commands such as a cache memory initialization request, memory write, and read request applied from the processor access terminal PC, and the main memory generated here. The access request to the memory access terminal MC is applied to the memory access terminal MC.

Next, the operation of this cache memory chip will be described. When a memory access command is applied to the control circuit 17 from the processor via the processor access terminal PC, the control circuit 17
Sets the memory address applied to the processor address terminal PA in the address register 11, and then searches the directory 14 by the value of the block address portion. At the same time, the prefetch circuit 12 calculates the next block address. When a match is detected by searching the directory 14 and the match detection output F of the directory 14 outputs the value “1”, that is, when the block including the address requested to be accessed exists in its own cache memory. The placement circuit 16 is updated by the match detection address FBA output by the directory 14, and the block address FBA output by the directory 14 and the word address in block of the address register 11 are also used as addresses to access the data memory 15. . That is, if the access request is a read request, the data memory 15
Is read, the read value is stored in the read data register 18, this output is applied to the processor data terminal PD, and then a signal indicating that the access is completed is applied to the processor access terminal PC. If the access request is a write request, set the write data on the processor data terminal PD in the write data register 19,
This value is written in the data memory 15 and a signal for notifying access completion to the processor access terminal PC is applied.

If no match is detected in the directory 14, that is, if the block including the address requested to be accessed does not exist in the own cache memory, the following process is performed to load the block. First, the replacement circuit
In 16 the block on the data memory 15 to be replaced is determined, and the value of the block address part of the address register 11 is registered in the corresponding entry of the directory 14.
Next, the main memory is read by applying the output of the block address part of the address register 11 and the word address in the block generated by the control circuit 17 to the memory address terminal MA and the memory read request to the memory access terminal MC. The data read to the data terminal MD is written in the data memory 15 via the write data register 19. After doing this for all words belonging to the block,
By registering that this block is valid in the directory 14, the process of loading the block is completed.

After loading the block requested by the processor,
When the signal is applied to the prefetch terminal PRF, the directory 14 is searched by the next block address calculated by the prefetch circuit 12. directory
If no match is detected in 14, the block loading process described above is performed. After this, the processor is accessed by re-executing the above-mentioned read or write processing of the data memory 15. If a match is detected in the directory 14, that is, if the next block already exists in the data memory 15, the block load process is not performed. Prefetch pin PR
When the signal is not applied to F, these processes are not performed, and the processor is immediately re-executed due to completion of loading of the block requested by the processor.

"Effects of the Invention" The embodiments of the present invention have been described above. As is clear from this description, the gist of the present invention is that the directory 14 for managing the blocks held by the chips and the block data are provided on the same chip. Memory access from the processor to the cache memory, with a built-in data memory 15 for holding data, a prefetch circuit (adder) 12 for calculating the next block address of the block accessed by the processor, and an associated control circuit 17. As an input / output terminal for request communication, a processor access control signal terminal for a memory access request, a completion signal, etc., a processor address signal terminal for a memory address from the processor, a processor for exchanging data with the processor Mainly from data signal terminals and cache memory When there is no memory access control signal terminal, memory address signal terminal, memory data signal terminal as the input / output terminal for communication of the memory access request between the cache memory chip and the block that requested the memory access. Has a prefetch pin that controls whether to load the next block together with that block, and when the requested block is found in the own chip when a memory access request from the processor is found, When the requested block is not found in the own chip and the prefetch terminal is applied, the requested block and the next block are loaded and the prefetch terminal is applied. If not, only the requested block It is possible to perform a prefetch only to necessary blocks by performing over de.

In this way, whether or not to perform prefetch for processor access can be dynamically switched and controlled for each processor access.

In the description of this embodiment, since it is not directly related to the gist of the invention, the operation including the specific implementation method and timing of the control circuit 17, for example, a memory access request, a gate for applying a completion signal to the terminal. Control, read,
Although detailed description of applying and receiving write data to the data terminal is omitted, it is obvious that these can be realized by the conventionally known technology. Further, in this embodiment, a single processor system in which one processor is connected to the main memory is assumed, but in a multiprocessor system including a plurality of processors each having a cache memory according to the present invention, each processor is It is necessary to consider to ensure the matching of the contents between the cache memory and the main memory of the above, and various conventionally known methods may be applied to this as well.

[Brief description of drawings]

The drawing is a block diagram showing an embodiment of the present invention. 11: address register, 12: prefetch circuit, 13: multiplexer, 14: directory, 15: data memory, 16:
Replacement circuit, 17: control circuit, 18: read data register, 19: write data register.

Claims (1)

[Claims] 1. A directory for managing blocks held by the chip on the same chip, a data memory for holding block data, and a block address next to a block accessed by a processor. Built-in prefetch circuit and related control circuit. As input / output terminal for communication of memory access request from processor to cache memory, processor access control signal terminal for memory access request, completion signal, etc. A processor address signal terminal for a memory address, a processor data signal terminal for exchanging data with the processor, and a memory access control signal terminal as an input / output terminal for communication of a memory access request from the cache memory to the main memory. , Memory address signal It has a pin, a memory data signal pin, and a prefetch pin that controls whether or not to load the block up to the next block if the block for which the memory access is requested does not exist in the cache memory chip. When the requested block is found in the own chip when the memory access request is made, access is made in the own chip, the requested block data is not found in the own chip, and the prefetch pin is applied. If so, the requested block data and the next block data are loaded, and if the prefetch terminal is not applied, only the requested block data is loaded. control method.