JPH0691420B2 - Adaptive Digital Filter - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive digital filter that performs adaptive control.

(Prior Art) Recently, due to rapid progress of digital signal processing technology, an adaptive digital filter (adaptive digital filter)
(Hereinafter referred to as ADF) is attracting attention because of its wide range of application. This ADF is composed of, for example, a delay element, an adder, and a multiplier, and its typical application is application to system identification. Here, the system identification is to estimate a parameter that determines the characteristic of the unknown system based on the input / output data of the unknown system whose characteristic is unknown.

Conventionally, as a technology in such a field, a collection of lecture papers of the IEICE General Conference in 1985 [9] (Sho 60-3-
5) There was something described in "2038 Digital Filter Configuration" P.28. Hereinafter, those configurations will be described with reference to the drawings.

FIG. 2 is a general explanatory diagram for explaining identification of an unknown system using ADF.

In FIG. 2, 1 is With ADF, 2 is an unknown system with transfer function H (Z). When the input X (k) at time k is given to ADF1 and unknown system 2, ADF1 becomes And the unknown system 2 sends the output y (k) at the same time k. The former negative And the latter positive output y (k) are added by the adder 3, and the estimation error E (k) at time k is sent from the adder 3.

In FIG. 2, for example, the evaluation function J = {E (k)} ² May be used. − Indicates a time averaging operation. ) Is 0, the transfer function H (Z) of the unknown system 2 and ADF1
of Can be considered equal. That is, it is considered that the parameters of the unknown system 2 are correctly estimated by ADF1.

An echo canceller is a specific application example of ADF1 for system identification. As shown in FIG. 3, for example, as shown in FIG. 3, an electronic conferencing system, which has recently received attention, has a pair of ADF 1 and an adder 3 and a pair of unknown system 2 having a speaker and a microphone, which are connected by transmission lines 4 and 4. Have a composition. In addition, between ADF1 and adder 3 and unknown system 2,
A plurality of analog / digital converters (A / D) 5 and digital / analog converters (D / A) 6 are connected between the ADF 1 and the adder 3 and the transmission lines 4 and 4, respectively. .

In this type of electronic conference system, howling may occur due to acoustic coupling between the speaker and the microphone in the unknown system 2, which may make communication difficult. for that reason,
The echo canceller ADF1 functions to identify the acoustic coupling path between the speaker and microphone and prevent howling.

Typical ADFs for echo cancellers that have been conventionally studied are shown in FIGS. 4 to 6.

FIG. 4 shows what is called a FIR type ADF, which comprises a plurality of unit delay elements 10 _{1 to} 10 n connected in series, a plurality of multipliers 11 _{1 to} 11 n having parameters A _{0 to} An, and an adder 12. It is composed of.

In this FIR type ADF, the transfer function H (Z) of the unknown system is set to the transfer function of the ADF. Parameter i (i = 0, 1, ..., N) is adaptively adjusted and estimated.

However, when applying the FIR type configuration to the electronic conference system as described above, the required parameter number P = n + 1 is 10 ³ to 1
Since it is on the order of 0 ⁴ , the circuit scale and power consumption become very large, which is not practical. Therefore, the fifth relationship, which can estimate the transfer relationship H (Z) of the unknown system with a small number of parameters
The application of IIR type ADF as shown in Fig. 6 and Fig. 6 is being studied.

The IIR type ADF shown in FIG. 5 is provided with a unit ADF in the front stage and a unit ADF in the rear stage which constitutes a fieldback system. The unit ADF in the previous stage is composed of multiple unit delay elements 2 connected in series.
0 _{1 to} 20n, a plurality of multipliers 21 _{1 to} 21n having parameters _{0 to} n, and an adder 22. Similarly, the unit ADF in the subsequent stage, which is cascade-connected to the unit ADF in the previous stage,
Multiple unit delay elements 30 _{1 to} 30 m connected in series and parameters It is composed of a plurality of multipliers 31 _{1 to} 31 m each having the above and an adder 32.

The transfer function of this ADF is Becomes

The IIR type ADF in Fig. 6 is the unit ADF in the previous stage in Fig. 5.
And a plurality of k second-order cyclic digital filters 40 _{1 to} 40 k that are connected in series. Each digital filter 40 _{1 to} 40 k is a unit delay element ₁₁ , 41 _{12 to} 41k ₁ , 41k ₂ , and a parameter. 42 ₁₁ , 42 _{12 to} 42k ₁ , 42k ₂ and adder 4 having
It is composed of 3 ₁₁ , 43 _{12 to} 43k ₁ and 43k ₂ .

The transfer function of this ADF is Is.

In the ADF of FIG. 5, the parameter i (i = 0,1, ..., n), In the ADF of FIG. 6, the parameter i (i = 0, 1, ...,
n), Are adaptively adjusted to estimate H (Z).

The IIR type configuration is, as is clear from the equations (2) and (3),
The root of the denominator polynomial If exists outside the unit circle Γ on Z plane, ADF becomes unstable. In order to avoid such a state and always operate the ADF stably, a calculation for stability determination is necessary. In the configuration of FIG. 5, the stability determination is to find the root of an m-th order algebraic equation as can be seen from the equation (2), and when m becomes large, it is difficult to realize in terms of processing time and arithmetic circuit scale. . Therefore, the structure shown in FIG. 6 is usually used because the stability can be easily determined. In this configuration, as can be seen from the equation (3), the roots of the quadratic equations of the denominator of the K quadratic cyclic digital filters (quadratic sections) 40 _{1 to} 40 k connected in cascade are the units on the Z plane. Circle Г
It will be determined whether it exists in. Therefore, it is possible to reduce the required hardware scale as compared with the FIR ADF shown in FIG.

(Problems to be Solved by the Invention) However, in the IIR type ADF of FIG. 6, each parameter _{0 to} n to be adaptively adjusted, Since there is a strong correlation between the input signals to, each parameter may not converge to the optimum value. In addition, each parameter _{0 to} n, An adaptive control circuit (not shown) for calculating and controlling
It became more complicated than the R-type ADF, and in the end, compared to the FIR-type ADF, the hardware (circuit) scale was not sufficiently reduced, and the IIR configuration characteristics were not fully utilized.

In order to eliminate this problem, the inventor of the present application proposed a so-called orthogonal function type digital filter and published it in the above-mentioned document.

In this orthogonal function type digital filter, a quadratic recursive digital filter and a quadratic acyclic digital filter having a zero at the mirror image position on the Z-plane unit circle of its pole are cascaded to form a basic section. A plurality of the basic sections are cascade-connected, and a basic section including only the secondary cyclic digital filter is cascade-connected to the final stage. Further, a primary acyclic digital filter is connected to the output side of the secondary cyclic digital filter in each basic section, and a plurality of basic blocks are formed by the primary acyclic digital filter and the basic section. The circuit configuration is such that the output sum of the primary acyclic digital filters in each of these basic blocks is output.

If adaptive control is performed using such an orthogonal function type digital filter, it is possible to improve the estimation accuracy, but on the other hand, the problem that the adaptive control circuit becomes complicated and the circuit scale becomes larger is solved. No, there were still inadequacies.

The present invention provides an orthogonal function ADF that solves the problems of the estimation accuracy and the miniaturization of the circuit scale among the problems that the orthogonal function digital filter has.

(Means for Solving Problems) In order to solve the above problems, the present invention provides a conventional orthogonal function type digital filter with a plurality of first arithmetic circuits 82i.
(I = 1, 2, ..., K), an adaptive control circuit including a differential coefficient detection circuit 80i and a second arithmetic circuit 81i is added.

Here, the plurality of first arithmetic circuits 82i are respectively connected to the output side of the secondary cyclic digital filter 50i in each basic section provided in the conventional orthogonal function digital filter, and the output of the digital filter 50i. From the output y (k) of the unknown system 71, the orthogonal function type digital filter The first parameter for determining the numerator polynomial in the rational function realized by the orthogonal function type digital filter based on the value E (K) Is a circuit for The plurality of differential coefficient detection circuits 80i are
A second parameter of each basic section which is connected to the output side of the first-order acyclic digital filter 52i in each basic block and determines the denominator polynomial in the rational function. This is a circuit for obtaining a differential coefficient for. Further, the plurality of second arithmetic circuits 81i are respectively configured to output the second parameter based on the value E (K) and the differential coefficients. Is a circuit for

(Operation) According to the present invention, since the orthogonal function type ADF is configured as described above, the first arithmetic circuit 82i uses the normally used steepest descent method or the like for the first parameter for a certain period of time. The first parameter for determining the numerator polynomial of the rational function Works so as to be adaptively controlled. Differential coefficient detection circuit 81i
Is the second parameter that determines the denominator polynomial in the rational function The differential coefficient for is calculated and given to the second arithmetic circuit 81i.
The second arithmetic circuit 81i outputs the output y (k) of the unknown system 71.
Of the orthogonal function type digital filter The second parameter based on the value E (K) For a certain period of time, the second parameter To act as an adaptive control. These first parameters Adaptive control of the second parameter And the adaptive control of are alternately repeated at regular intervals to set parameters. Adaptive control of. As a result, the structure can be simplified and highly accurate parameter estimation can be performed. Therefore, the above problems can be eliminated.

(Embodiment) FIG. 1 is a configuration block diagram of an orthogonal function type ADF showing an embodiment of the present invention, and FIG. 7 is a basic configuration block diagram of an orthogonal function type digital filter which is the basis of FIG.

First, the orthogonal function type digital filter of FIG. 7 is composed of a plurality of quadratic cyclic type digital filters. Among these digital filters, 50 _{1 to} 50k
_{-1 in} the subsequent stage, a plurality of secondary acyclic digital filters 51 _{1 to} 5 ₁ having zeros at positions that are mirror images of the unit circle Γ on the Z plane with respect to the poles of the digital filters 50 _{1 to} 50 k _-1.
1k _-1 it is connected in cascade, respectively, each of these pair of digital filters 50 _1, 51 ₁ ~50k _-1, are respectively constituting the basic period 51k _-1 are successively cascaded. However, the basic section at the final stage is composed of only the secondary cyclic digital filter 50k. Further, between the secondary recursive digital filters 50 _{1 to} 50 k _-1 and the secondary acyclic digital filters 51 _{1 to} 51 k _-1 in each basic section, the primary acyclic digital filters 52 _{1 to} 52 k _-1 are respectively provided. Is connected to the 2nd cyclic digital filter 50k in the basic section of the final stage.
A secondary acyclic digital filter 52k is connected to each of these basic sections and a primary acyclic digital filter connected thereto. And form a plurality of basic blocks. Where each 2
Next cyclic digital filter Each second-order acyclic digital file 51 _{1 to} 51 k _-1 has a coefficient Multiplier 63 _11-63 having the _{(k -1) 1,} the multiplier 63 ₁₂ ~63 _{(k -1) 2} with coefficients ₁ to k _-1, and the adder 64 _11, 64 ₁₂ to 64 ₍
It is composed of k _{-1) 1} and 64 ₍ k _{-1) 2} . In addition, the primary acyclic digital filter 52 ₁ It consists of 66k.

Each first-order acyclic digital filter The adders 70 _{1 to} 70 k _-1 are connected to the output side of and are added by these adders 70 _{1 to} 70 k _-1 . There is sent from the adder 70 _1. This negative And an unknown system 71 for estimating the transfer function H (Z).
And the positive output y (k) are added by the adder 72, and the estimation error E (k) is sent from the adder 72.

In the above configuration, this orthogonal function type digital filter Becomes Where Ψi (Z) is Is. If the inverse Z transformation of Ψi (Z) is Ψi (k),
From the above literature, Is established. That is, the pattern in the i-th basic block The inputs are orthogonal to the corresponding inputs in the other basic blocks. For the input X (k) of this orthogonal function type digital filter Is Is. When using this as an ADF, Is a variable parameter. The estimation error E (k) for an unknown system 71 whose output is y (k) is It is represented by.

Next, an adaptive control method of parameters in each basic block will be described.

The transfer function H (Z) of the unknown system 71 is given by a rational function such as the following equation.

Equation (8) is a rational function of (2k-1) th order / (2k) th order. αi, βi and k are determined by the characteristics of the unknown system 71. Therefore, the expression (8) is a general expression of the transfer characteristic in the unknown system 71.

The unknown system 71 whose transfer characteristic is expressed by equation (8) is used as a parameter of the orthogonal function type digital filter as shown in FIG. Is estimated by adaptive control.

First, the parameters in the basic section Consider the adaptive control method of. The algorithm shown by the following equation is used as the adaptive control algorithm.

here, Represents the amount of correction once, and is calculated by the following equation.

But it's okay.

In equations (9a) and (9b) Is the parameter of the mth basic block The value after ν times is updated. Also, (10a) ~ (10
d) in the formula When is calculated, it becomes as follows.

FIG. 1 is a block diagram of an orthogonal function type ADF using the adaptive control algorithm of equations (9a) and (9b).

This orthogonal function type ADF is the same as the orthogonal function type digital filter shown in FIG. 7, except that it is a differential coefficient detection circuit of a quadratic cyclic digital filter 80 _{1 to} 80 k, second arithmetic circuits 81 _{1 to} 81 k, and a _first arithmetic circuit. Circuits 82 _{1 to} 82k are provided.

Each secondary cyclic digital filter 80 ₁ ~80k is connected to the output side of the basic blocks, each basic block By inputting parameters _{1 to} k, which belong to each basic interval, Is a circuit for obtaining the differential coefficient for the unit delay element 90 ₁₁
˜90k ₁ , unit delay elements 90 _{12 to} 90k ₂ , multipliers 91 _{11 to} 91k ₁ having coefficients _{1 to} k, coefficients 90 _{12 to} 91k ₂ and an adder 92 ₁₁ , 92 _{12 to} 92k
_1, and a 92k _2.

The arithmetic circuits 81 _{1 to} 81 k are connected to the output side of the adder 72,
A single parameter correction amount based on the estimation error E (k) and the differential coefficient obtained by the second-order cyclic digital signals 80 _{1 to} 80 k Is a circuit for obtaining four multipliers 93 ₁₁ , 93 _{12 to} 93k ₁ ,
It is composed of 93k ₂ , 94 ₁₁ , 94 _{12 to} 94k ₁ , 94k ₂ . Here, the multipliers 93 _{11 to} 93 k ₁ are the second-order cyclic digital filters 80 ₁
The output of the unit delay elements 90 _{11 to} 90 k ₁ at ˜80 k is multiplied by the estimation error E (k), and the multiplication result is multiplied by the multiplier 94 ₁₁ ˜.
Give to 94k ₁ . Multiplier 93 ₁₂ ～93K ₂ receives the output of the delay element 90 ₁₂ ～90K ₂ in the secondary cyclic digital filter 80 ₁ ~80k, the estimated error E (k) is multiplied, the multiplier 94 ₁₂ the multiplication result Give to ~ 94k ₂ . Multipliers 94 _{11 to} 94k ₁ are multipliers
93 ₁₁ 〜 93k ₁ output multiplied by a constant α, and the amount of parameter modification once To calculate. In addition, the multipliers 94 _{12 to} 94 k ₂ are the multipliers 93 ₁₂ to 94 k _2.
93k ₂ output is multiplied by a constant α and the amount of parameter modification is once Is a circuit for

The arithmetic circuits 82 _{1 to} 82 k are connected to the output side of the adder 72 and are connected to the estimation error E (k) and the second-order cyclic digital filter.
_One parameter modification amount based on the output of 50 _{1 to} 50k Is a circuit for obtaining four multipliers 95 ₁₁ , 95 _{12 to} 95k ₁ ,
It is composed of 95k ₂ , 96 ₁₁ , 96 _{12 to} 96k ₁ , 96k ₂ . Here, the multiplier 95 ₁₁ ~95k ₁ multiplies the output of the adder 62 ₁₁ ~62k ₁ in the estimation error E (k) and a secondary cyclic digital filter 50 ₁ ~50k. The multiplication result is multiplied by a constant β by the multipliers 96 _{11 to} 96k ₁ and the amount of parameter modification is performed once. To get Similarly, the multipliers 95 _{12 to} 95 k ₂ have the estimation error E
(K) and multiplies the output of the delay unit 60 ₁₁ ~60k ₁ in the secondary cyclic digital filter 50 ₁ ~50k. The multiplication result is multiplied by a constant β by the multipliers 96 _{12 to} 96k _2, and the amount of parameter correction once To get

In the orthogonal function ADF configured as above, (9a),
When the adaptive control algorithm of Eq. (9b) is used, the basic block parameters are as follows. Is set to an optimum value when converges.

(1) First, the transfer function H (Z) of the unknown system 71 expressed by the equation (8) is set to the convergence value of the parameter in the orthogonal function type ADF. It can be expressed as

In equation (12), Is the convergence value of the parameters of the orthogonal function type ADF, and m = k
Values after +1 are arbitrary values. Transfer function H of equation (8)
The reason why (Z) can be expressed as in equation (12) is that H (Z) is expanded in an orthogonal function system as shown in equation (12).

When the algorithms of equations (9a) and (9b) converge, Has been established. Using equations (11a) and (11b),
Expressing a) and (13b) in the Z domain, Becomes here, Is. If the expressions (13a) and (13b) are satisfied, (14
Whether the integrand in a) to (14c) has no pole in the unit circle Γ is Is zero. As is clear from the equations (14a) to (14c), since the unit circle Γ has poles, Is 0. As described above, the parameter value of the unknown system 71 matches the parameter value of the orthogonal function ADF.

(2) In (1) above, parameters The adaptive control method of The normal steepest descent method may be used for the adaptive control of. That is, Is.

(3) When the above (1) and (2) are arranged, the parameter control procedure is as follows.

Parameters for a certain period using Eqs. (15a) and (15b) To update.

Next, parameters for a certain period To update.

 Return to the above and repeat the above procedure.

Since such adaptive control is performed, the parameter estimation accuracy is high and the configuration of the adaptive control circuit is simple.
The circuit scale becomes smaller.

The present invention is not limited to the illustrated embodiment, and various modifications can be made. The following are examples of such modifications.

(A) Parameter correction amount Was calculated by the steepest descent method using the first arithmetic circuits 82 _{1 to} 82k. However, the parameter correction amount could be obtained by using a circuit having a different configuration from the arithmetic circuits 82 _{1 to} 82k, or by a method different from the steepest descent method. It is also possible to ask

(B) Parameter modification amount In the second arithmetic circuit 81 ₁ ~81k seeking, each multiplier 93
_After obtaining the time average value (correlation calculation value) of the multiplication results in ₁₁ , 93 _{12 to} 93k ₁ and 93k ₂ , the value is calculated by each multiplier 94 ₁₁ , 94 _{12 to} 9
Even if the parameter correction amount is obtained by inputting into 4k ₁ and 94k ₂ , almost the same effect as in the above embodiment can be obtained. Thus, the second arithmetic circuit 81 ₁ ~81k, the more differential coefficient detecting circuit or the like, and various modifications may be made to the other circuit configurations.

(Effect of the Invention) As described in detail above, according to the present invention, the parameters of each basic block that determine the denominator polynomial of a rational function realized by an orthogonal function ADF Of the ADF from the output y (k) of the unknown system 71 And the parameter of the output signal of the first-order acyclic digital filter 52i in each basic block. Since it is possible to perform adaptive control by using the differential coefficient and, it is expected that the parameter estimation accuracy is high and that the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an orthogonal function type adaptive digital filter (ADF) according to an embodiment of the present invention, FIG. 2 is an explanatory diagram for identifying an unknown system by the ADF, FIG. 3 is a block diagram of an echo canceller, and FIG. FIG. 4 is a configuration diagram of a conventional FIR type ADF, FIGS. 5 and 6 are configuration diagrams of a conventional IIR type ADF, and FIG. 7 is a configuration of an orthogonal function type digital filter for explaining an embodiment of the present invention. It is a figure. 50 _{1 to} 50k …… 2nd recursive digital filter, 50 _{1 to} 50k
_-1 …… Secondary acyclic digital filter, 52 _{1 to} 52k ……
First-order cyclic digital filter, 70 _{1 to} 70k _-1 …… Adder, 71 …… Unknown system, 72 …… Adder, 80 _{1 to} 80k ……
Second-order cyclic digital filter (differential coefficient detection circuit), 81
_{1 to} 81k ... second arithmetic circuit, 82 _{1 to} 82k ... first arithmetic circuit, X (k) ... input, y (k) ... Output of unknown system, E (k) ... Estimation error.

Claims (1)

[Claims] 1. A second-order cyclic digital filter 50i (i =
, 2, ..., K) and a secondary non-recursive digital filter 51j (j = 1, j) connected in cascade to the digital filter 50i and having a zero at the mirror image position with respect to the unit circle on the Z plane of the poles of the digital filter 50i. , ..., K-1) and a plurality of basic sections connected in cascade, and a basic section composed of a secondary cyclic digital filter 50 _K is connected in cascade to the final stage of the basic section. Secondary cyclic digital filter in each of the basic sections
A plurality of primary acyclic digital filters 52i, each of which is connected to the output side of 50i and constitutes a plurality of basic blocks together with each of the basic sections, are provided. By adaptively controlling the output sum of the first-order acyclic digital filter 52i in each of the basic blocks. In the adaptive digital filter, the second-order cyclic digital filter in each of the basic sections is provided.
Output y (k) of the unknown system 71, which is connected to the output side of 50i and is estimated by the output of the digital filter 50i and the transfer function H (z) given by a rational function realized by the adaptive digital filter. Of the adaptive digital filter The first parameter for determining the numerator polynomial in the rational function based on the value E (K) And a plurality of first arithmetic circuits 82i for obtaining the following, and second parameters of the basic section which are respectively connected to the output side of the primary acyclic digital filter 52i in each of the basic blocks and which determine the denominator polynomial in the rational function. A plurality of differential coefficient detection circuits 80i for obtaining differential coefficients for
From the output y (k) of the unknown system 71, the adaptive digital filter On the basis of the value E (K) obtained by subtracting An adaptive digital filter having a plurality of second arithmetic circuits 81i for determining