JPH0691254B2 - Thin film transistor integrated circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor integrated circuit used in a liquid crystal display, an image pickup device or the like.

2. Description of the Related Art In recent years, thin film transistors and integrated circuits thereof have been widely used for selecting pixels of liquid crystal displays, as peripheral circuits including shift registers, or as image pickup devices for image reading.

An example of the above-described conventional thin film transistor integrated circuit will be described below with reference to the drawings.

Conventionally, for example, for pixel selection of a liquid crystal display, a second
Thin film transistors as shown in the figure are used by arranging them in a matrix form. As its operation method, when a sufficient voltage is applied to the gate of a field effect transistor (hereinafter referred to as FET) and the resistance between the drain and source of the FET decreases, current flows into the pixel electrode connected to the source and the liquid crystal rises. He used the method of climbing. For example,
Nikkei Electronics, December 20, 1982, 105-179
page.

Problems to be Solved by the Invention However, in the above configuration, in order to reduce the ON resistance of the FET, it is necessary to increase the ratio of the gate width to the gate channel length, that is, the W / L ratio. There is a high risk of a drain short circuit, and when this phenomenon occurs, both the gate bus line and the drain bus line are defective. In addition, the increase in drain current when the gate voltage is increased is relatively gradual, and the drain current ratio required to turn on / off the liquid crystal is 10 ⁴
In order to obtain, it was necessary to change the gate voltage widely.

In view of the above problems, the present invention is unlikely to cause a short circuit between the gate bus and the drain bus, and is capable of turning on / off the drain current.
Provided is a thin film transistor integrated circuit having a narrow variation range of a gate voltage for obtaining a ratio.

Means for Solving the Problems In order to solve the above problems, the thin film transistor integrated circuit of the present invention uses three FETs, and the drain of the first FET,
The gate and the source of the second FET are connected to the gate of the third FET, the drain of the second FET is connected to the drain of the third FET, and the source of the first FET is connected to Third
It has a configuration that connects the source of the FET.

Action According to the present invention, in order to short-circuit the gate of the first FET and the drain of the third FET with the above-described configuration, the gate and drain of the first FET and the gate and drain of the second FET are simultaneously disconnected. It is necessary to short-circuit or the gate and drain of the 1st FET and the gate and drain of the 3rd FET at the same time, so short circuit failure is less likely to occur than in the case of a single FET like the conventional example. Become. Further, in order to reduce the ON resistance, only the W / L ratio of the third FET can be increased, and the W / L ratio of the first and second FETs can be decreased to some extent.
The short circuit between the gate and the source of the FET is less likely to occur.

Next, the gate potential of the third FET is set to the first FET and the second FET.
Since it is controlled by the output voltage of the inverter composed of FET, the gate voltage of the first FET causes the drain-source current of the third FET to have a sharp transition between ON and OFF,
Therefore, the drain current can be turned on and off with a narrow gate voltage width.
it can.

Embodiment Hereinafter, a thin film transistor integrated circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a thin film transistor integrated circuit of the present invention. In FIG. 1, Q ₁ is the first FET and Q ₂ is the second FE.
T and Q ₃ are the third FET, and A is the intermediate node point. In one embodiment of the present invention, the W / L ratios of Q ₁ , Q ₂ and Q ₃ are 0.75,0.
Designed to 75,15, an amorphous silicon thin film as an active layer,
It was composed of a thin film transistor using a silicon nitride thin film as a gate insulating film.

The operation of the thin film transistor integrated circuit configured as described above will be described. When the gate voltage of Q ₁ has a sufficiently large negative value, Q ₁ is in the OFF state, and the voltage at the point A is Q ₃ The drain voltage is the potential divided by the OFF resistance of Q _{1 and} the resistance of Q ₂ . Since the gate of Q ₂ is in the source and the same potential, OFF resistance for Q ₁ gate potential is a negative value, Q ₂
Greater than the resistance of. In this embodiment, since the W / L ratios of Q ₁ and Q ₂ are the same, the OFF resistance of Q ₁ is high by about one digit, and the potential at point A is a value sufficient to turn ON Q _3. . Next, when the gate potential of the Q ₁ is increased to the positive side to the extent that turning ON the Q _1, the potential at the point A becomes rapidly smaller, Q ₃ is turned OFF. Furthermore, when the gate voltage of Q ₁ becomes negative again, Q ₁ turns off,
Q ₃ because the voltage rises at the point A becomes ON again.

FIG. 3 is a characteristic diagram of gate voltage vs. drain current of a thin film transistor integrated circuit according to an embodiment of the present invention.

The figure shows the case where 20 Volt is applied as the drain voltage of Q ₃ , but the drain current is turned on and off at a gate voltage of about ± 2V.
A ratio of about 10 ⁴ is obtained, but for a single FET with only Q ₃ , 10 ⁴ O
A gate voltage width of about 10V is required to obtain the N / OFF ratio.

Although the MIS type FET made of the amorphous silicon thin film is used as the thin film transistor in the above-described embodiment, the thin film transistor may be made of polycrystalline silicon, CdSe, Te or the like in addition to amorphous silicon.

EFFECTS OF THE INVENTION As described above, since the present invention is configured by three thin film transistors, a short circuit between the gate and the drain is less likely to occur than in the case of a single thin film transistor, and the drain current is turned on. The excellent effect that the displacement width of the gate voltage for controlling the OFF can be small is obtained.

Therefore, the present invention is also used as a flat panel display such as a liquid crystal display or an electroluminescence display, a switching circuit for pixel selection in an image pickup device for image reading, or a control circuit around a pixel. be able to.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a thin film transistor integrated circuit of the present invention,
FIG. 2 is a circuit diagram of a conventional thin film transistor, and FIG. 3 is a characteristic diagram of gate voltage vs. drain current of a thin film transistor integrated circuit according to an embodiment of the present invention. _{Q 1, Q 2, Q 3} , Q 4 ...... FET, A ...... intermediate nodes.

Claims (2)

[Claims] 1. A drain of a first field effect transistor, a gate and a source of a second field effect transistor, and a gate of a third field effect transistor are connected to each other, and a drain of a second field effect transistor. , The drains of the third field effect transistors are connected, and the first
2. A thin film transistor integrated circuit, characterized in that the source of the field effect transistor is connected to the source of the third field effect transistor. 2. The W / L ratio of the first and second field effect transistors is smaller than the W / L ratio of the third field effect transistor by one digit or more. Item 3. A thin film transistor integrated circuit according to item.