JPH0690696B2 - Buffer management method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data processing system, and more particularly to a buffer management system in a device that performs retransmission processing.

[Conventional technology]

As the conventional buffer management method in the data storage area, as in Japanese Patent Publication No. Sho 61-18786, there is a chaining method that manages the buffers by connecting them like a chain, and a buffer address is written in a fixed table to manage the buffers. The table method is generally used.

[Problems to be solved by the invention]

In the above-mentioned conventional technique, in the chaining method, all of the buffer updating, the buffer searching, and the like are performed by the address chaining. Therefore, the address rewriting is required when performing the updating and searching, which is complicated.

On the other hand, in the table method, when updating the buffer, such as setting the latest data to the end of the already stored data, the entire table is rewritten, so it takes time to update the buffer. was there.

It is an object of the present invention to provide a simple and quick buffer management scheme.

[Means for solving problems]

The above object is achieved by using a system in which a cyclic buffer management counter is provided, a ring-shaped management table is formed, and a buffer address is written in this management table.

[Action]

The transmission processing device transmits the transmission data for each frame based on transmission synchronization. Along with this, the transmission interrupt signal generation circuit indicates that the transmission of one frame of data has been completed.
The central processing unit is notified by generating an interrupt signal. The central processing unit which has received the transmission interrupt buffers the transmission data in order to store a predetermined number of the transmission completed data in preparation for the retransmission processing. At this time, the central processing unit sets the address of the transmission data to the storage number indicated by the cyclic counter, thereby ending the registration of the buffer. When the registration is completed, the cyclic counter value is incremented in preparation for the next data transmission.

The reception operation is performed asynchronously in parallel with the transmission operation.

The reception processing device receives the serial digital data and forms the data for one frame. The reception interrupt signal generation circuit
When the reception of the data for one frame is completed, the fact is notified to the central processing unit by an interrupt signal. The central processing unit which has received the reception interrupt starts the reception processing. In the reception process, the received data is analyzed, and in the case of the retransmission request frame reception, the requested transmission data is searched from the buffer stored at the time of transmission and the transmission process for retransmission is performed. At this time, since the storage number indicated by the cyclic counter is the oldest data registered in the buffer, the central processing unit sequentially searches from this data.

By having such a cyclic counter,
It is possible to easily perform the update of the transmission completion data and the data search at the time of the retransmission request.

As a result, it is possible to solve the complexity of address rewriting in the chaining method and the long processing time at the time of updating the table method, and perform simple buffer management.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings. Second
FIG. 1 is a block diagram of a data processing device showing an embodiment of the present invention. Reference numeral 1 is a central processing unit, reference numeral 2 is a transmission interrupt signal generation circuit, reference numeral 3 is a reception interrupt signal generation circuit, reference numeral 4 is a transmission processing device, reference numeral 5 is a reception processing device, and reference numeral 6 is a storage device. Reference numerals 7 and 8 are interrupt signal lines, reference numerals 10 and 11 are reception data lines, and reference numerals 20 and 21 are transmission data lines.

The data having the frame structure shown in FIG. 3 is transmitted and received by the device having such a structure. In FIG. 3, reference numeral 30 is a transmission data section,
Reference numeral 40 is a sequence number portion that gives a sequence to the frames, and performs resending processing and the like according to the sequence number. 4 and 5
The figure is a flow chart showing the operation of the central processing unit 1 upon completion of transmission and completion of reception.

The features of the operation in one embodiment of the present invention will be described below with reference to FIG.

When the transmission processing device 4 completes the transmission of the transmission data, it notifies the central processing unit 1 that the transmission interrupt signal generation circuit 2 has completed. The central processing unit 1 performs post-transmission processing based on the sequence shown in FIG.

The transmission completion buffer is stored in the ring-shaped table 15 managed by the cyclic counter 9 as shown in FIG. At this time, the storage number pointed to by the cyclic counter 9 stores the buffer 30a having the oldest sequence number among the stored transmission completion buffers. When the transmission completion buffer is registered as indicated by 101 in FIG. 4, the oldest buffer 30a becomes the ring table 15.
Buffer 30 that has gone off and completed the transmission instead
z is re-registered. Thereafter, as indicated by 102 in FIG. 4, the cyclic counter 9 is incremented in preparation for the next registration. By repeating this process, one fixed number of transmission completion buffers that have been determined are always stored.

On the other hand, the reception process is performed in the sequence shown in FIG.

When one frame is received, the reception interrupt signal generation circuit 3 notifies the central processing unit 1 of that fact. The central processing unit 1 analyzes the received data and determines whether it is normal data or resend request data. Only when a retransmission request frame related to the present invention, which is indicated by 200 in FIG. 5, is received will be described below.

When a resending request is received, resending is performed from the requested sequence number, so it is necessary to search the frame of the sequence number concerned from the stored transmitted buffer. Therefore, the central processing unit 1 reads the cyclic counter 9 as indicated by 201 in FIG. As described above, since the value indicated by the cyclic counter 9 at this time is the oldest transmission completion buffer 30a stored, the search is started using this as the search counter value, as indicated by 202. The search is performed by comparing the sequence number in the buffer with the sequence number requested to be retransmitted, as indicated by 203. As a result of this comparison, it is determined whether or not the search is completed depending on whether or not they are equal. If the comparison results are not equal, the search counter value is incremented as indicated by 206 and 207 to search the next buffer. By repeating the operations of 203 to 207, the search can be performed in order from the stored oldest transmission completion buffer to the newest transmission completion buffer. When the search is completed in the above comparison, the transmission completion buffer is retransmitted as indicated by 205 to prevent data loss.

〔The invention's effect〕

As described above, according to the present invention, the buffer can be easily updated and searched by only providing the cyclic counter, so that there is an advantage that the processing speed is fast and the simple buffer management can be performed.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a diagram showing an example of a format of transmission / reception data, and FIG. 4 is a buffer after transmission. FIG. 5 is a flowchart of the ring processing, and FIG. 5 is an operation flowchart of the central processing unit when the retransmission request frame is received. 1 ... Central processing unit, 2 ... Transmission interrupt signal generation circuit, 3 ... Reception interrupt signal generation circuit, 4 ... Transmission processing device, 5 ... Reception processing device, 6 ... Storage device, 9 ... Cyclic Counter, 15 ... Ring table, 30 ... Transmission data, 40 ... Sequence number part.

Claims (1)

[Claims] 1. A reception processing device for receiving data of one frame from an external device, a reception interrupt signal generation circuit for generating an interrupt signal each time reception of one frame is completed, and a transmission processing device for transmitting one frame. Data transmission including a transmission interrupt signal generation circuit that notifies completion of transmission of one frame, a central processing unit that analyzes received data and performs retransmission processing depending on the quality of the transmission path, and a storage device that holds the data In the device, a cyclic buffer management counter and a ring-shaped management table in which buffer addresses by the buffer management counter are written are provided, and when a retransmission request is received, retransmission processing should be performed according to the order of the buffer addresses in the management table. A buffer management method characterized by searching data.