JPH0690658B2 - Operating clock generator for microprocessor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system using a plurality of microprocessors, and to a motion clock generation device for generating a motion clock which is a standard of motion of the microprocessors. .

[Conventional technology]

In recent years, downsizing of electronic devices is progressing due to the large scale and high performance of ICs. In particular, portable devices have been developed for word processors, personal computers, car phones, etc. that have a built-in microprocessor. Since portable devices mainly use batteries as power sources, it is important to reduce the power consumption of the entire device.

Among the components of these devices, the microprocessor has a large circuit scale and needs to be constantly operating. Therefore, the microprocessor has a high share in the power consumption of the entire device. In addition, with the higher functionality of the device,
When using a plurality of microprocessors, the power consumption becomes a problem.

Therefore, in order to reduce the power consumption of the above portable device, a CMOS (complementary metal oxide semiconduc
tor) process microprocessors are often used. The power consumption of this CMOS microprocessor is proportional to the frequency of its operating clock. Therefore, focusing on this property, a technique for suppressing the power consumption by changing the frequency of the operating clock of the microprocessor is disclosed in JP-A-61-136115, JP-A-61-136116, and JP-A-61-136116. A method of controlling the operating frequency in the case of a multiprocessor configuration composed of a plurality of microprocessors is disclosed in Japanese Patent Laid-Open No. 61-122733.

[Problems to be solved by the invention]

Among the above-mentioned conventional techniques, JP-A-61-1361
No. 15, JP 61-136116, JP 60-23522
The technologies described in the publications are all related to a single microprocessor, and in a system using a plurality of microprocessors, the frequency of the operating clock of those microprocessors is variable. He was not considered.

Further, the technology disclosed in JP-A-60-122733,
In the case of a multiprocessor composed of multiple microprocessors, which is also composed of a master processor and a slave processor, in a device in which the slave processor controls the operating frequency of the main processor,
It is configured such that the main processor can control the operating frequency of the slave processor.

According to this technique, the operating frequency of the slave processor, which has been constant in the past, can be lowered from that of the main processor, so that the overall power consumption can be reduced. However, it is necessary to detect the processing amount of the other party and control the processor operating frequency of the other party according to the detected processing amount, which may complicate the control operation. In addition, when performing fine control such as increasing the frequency only during the period from the reception of data to the end of processing of that data, it is necessary to always understand each other's processing contents. It can be said that creating a program is very difficult.

That is, in a system using a plurality of microprocessors, a processing request is issued to a certain microprocessor from another microprocessor which is different from the microprocessor. In this case, if the frequency of the operating clock of the microprocessor receiving the request is low, the processing for the request may not be in time. Therefore, the frequency of the operation clock is set to be high over the entire period when there is a possibility that a processing request from another microprocessor will arrive at that microprocessor. However, doing so causes a problem because the power consumption is increased this time.

The object of the present invention is to solve the above-mentioned problems of the prior art,
At least for a certain microprocessor, so that the microprocessor can process at high speed in response to the generation of a processing request from another microprocessor or the like without increasing power consumption in the microprocessor. It is an object of the present invention to provide a motion clock generation device capable of generating motion clocks.

[Means for solving problems]

In order to achieve the above-mentioned object, in the present invention, in a system composed of a plurality of equal microprocessors that exchange data with each other, a clock generating means for generating a reference clock, and the reference clock are divided. Of the plurality of microprocessors, at least an operation clock serving as an operation reference of the first microprocessor is output, and a frequency division ratio of the operation clock is variable, and the first microprocessor controls its own processor. A first frequency division ratio setting signal that is output according to the processing state and a second frequency division ratio that is output from a device other than the first microprocessor in association with data exchange between the plurality of microprocessors. A setting signal and are input, one of them is selected, and the dividing ratio of the variable dividing means is set by the dividing ratio setting signal. Frequency division ratio setting means, wherein the frequency division ratio setting means outputs the frequency of the operation clock output from the variable frequency division means among the first and second frequency division ratio setting signals. The frequency division ratio setting signal having a higher frequency is selected to set the frequency division ratio.

[Action]

In the present invention, the variable frequency division means sets the frequency division ratio according to the frequency division ratio setting signal that is input, and as a result, the frequency of the operation clock that is output is set. The frequency division ratio setting means selects one of the first and second frequency division ratio setting signals having a higher frequency of the operation clock and inputs the selected one to the variable frequency division means. Therefore, at least the frequency of the operating clock of the first microprocessor is always set to the higher one of the frequencies set by the first and second frequency division ratio setting signals.

Therefore, for example, when a processing request is issued from another microprocessor or the like to the first microprocessor, the second frequency division ratio setting signal is sent from the microprocessor or the like which issues the processing request. By outputting and setting the frequency division ratio set by the second frequency division ratio setting signal so that the frequency of the operating clock becomes higher, the first microprocessor speeds up its processing. Can be executed.

Further, when a processing request such as a data signal is sent from the other microprocessor or the like to the first microprocessor, the first microprocessor from the microprocessor or the like which issues the processing request. Detecting means for detecting the data signal to be transmitted to the second dividing ratio setting signal is used as the second dividing ratio setting signal, and the detecting signal from the detecting means is used as the second dividing ratio setting signal. By setting the frequency division ratio thus set so that the operating clock has the highest frequency, the first microprocessor can process the transmitted data signal at high speed.

〔Example〕

 Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the first embodiment of the present invention.

In FIG. 1, reference numerals 1 and 2 denote microprocessors (hereinafter abbreviated as CPU), which perform asynchronous communication between them using signals g1 and g2. Further, 3 and 8 are oscillating circuits which generate reference clocks for the operation clocks of the CPUs 1 and 2, and 4 and 9 variably divide the reference clocks from the oscillators 3 and 8 to output the operation clocks of the CPUs 1 and 2. It is a variable frequency divider circuit, and its frequency division ratio is signal g4, g5 and signal g12, g13, respectively.
Is determined by. Further, 7 and 12 monitor the signals g1 and g2 to detect whether or not communication is performed between the CPUs 1 and 2,
A data detection circuit that outputs detection signals g8 and g9. In addition, 5,6,10,11 are OR gates.

In this embodiment, the output frequency of the oscillator circuits 3 and 8 is 16
The output frequency of the variable frequency dividing circuits 4 and 9 is set to MHz as shown in Table 1 below.

Further, both the data detection circuits 7 and 12 are composed of a monostable multivibrator, and detect the start bit added to the head of the asynchronous serial data output as the signals g1 and g2, which is longer than one word of data. The detection signals g8 and g9 are set to High level for a certain period.

The operation of this embodiment will be described below with reference to FIGS.

FIG. 2 is a timing chart showing the operation timing of the main signal in FIG.

First, the operation regarding the CPU 1 will be described.

In FIG. 2, the CPU1 was initially in a dormant state, and the signal g
Set both g5 and g5 to low level and set the operating clock g3 to the minimum of 500 kH
It is set to z. When the data is output from the CPU 2 as the signal g2 at the point A, the data detection circuit 7 detects the start bit of the data and sets the detection signal g8 to the high level. As a result, the output signals g4 and g5 of the OR gates 6 and 5 are both at the high level.

As a result, the setting value of the frequency division ratio of the variable frequency dividing circuit 4 changes,
From the point of A'point, the operating clock g3 of CPU1 is
At 4MHz, CPU1 can respond to the data sent from CPU2 at high speed. Here, the reason why the change of the frequency of the operation clock g3 is delayed with respect to the change of the signals g4 and g5 is that the pulse that causes the malfunction is not output to the operation clock of the CPU, which will be described later.

Next, FIG. 3 is a timing chart showing the operation timing of the main signal in FIG. 1, which is shown over a longer period than FIG. In FIG. 3, point A is the same as point A in FIG.

As described above, at the point A, the data detection circuit 7 detects the data output as the signal g2, and the detected signal g8
Becomes High level. As a result, the signals g4 and g5 become High, and the operating clock of the CPU1 becomes 4 MHz.

Then, when the data ends at the point B, the CPU1 shifts to the process of analyzing the data. First, in order to set the operation clock of the CPU1 to 4 MHz, the signals g6 and g7 are set to the high level at the point C. To do. Since the data detection circuit 7 is a monostable multivibrator as described above, the detection signal g8 remains constant for a certain period of time.
After it goes high, it goes low at point D.

However, at this point, the signals g6 and g7 are already at high level, so the signals g4 and g5 do not change and the operating clock is 4 MHz.
It remains z, and the CPU1 can execute the analysis processing at the maximum speed.

Then, at the point E, the CPU 1 finishes the data analysis process and starts the process instructed by the received data with the operation clock lowered to 2 MHz.

As described above, in the operation example shown in FIG. 3, the operation clock of the CPU1 is lowered to 2 MHz at the point E, but this frequency may be set to another frequency according to the degree of the instructed processing. good.

Next, a specific example of the variable frequency dividing circuit 4 in FIG.
Shown in the figure.

In FIG. 4, reference numeral 21 is a frequency dividing circuit, which divides the input clock signal g20 by 1/2, 1/4, 1/8, 1/16 and outputs it. 22 is a selection circuit, which selects SELE from the four types of input clock signals.
Select and output the signal specified by the CT signal. Reference numerals 23 and 24 are clutch circuits, which hold the signals g4 and g5,
The signal is output to the selection circuit 22. Reference numeral 25 is an AND gate, which gives timing for latch circuits 23 and 24 to fix data.

The operation of the variable frequency dividing circuit shown in FIG. 4 will be described below.

The AND gate 25 causes the latch circuits 23 and 24 to hold the signals g4 and g5 at the time when the outputs of the frequency divider circuit 21 are all at the high level. Therefore, in the selection circuit 22, all the clock signals input at the time when the SELECT signal changes are always High.
It becomes a level.

Therefore, the operation clock g3 does not output a pulse with a short width that causes a malfunction of the CPU. Also, the signal g
Since 4, g5 are not retained in the latch circuits 23, 24 except at the timings described above, the signals g4, g as described in the explanation of FIG.
With respect to the change of 5, the change of the frequency of the operation clock g3 is delayed.

Next, regarding the operation related to CPU2, this operation is the same as the operation related to CPU1 described above, and CPU1 signals data.
When output as g1, the data detection circuit 12 and OR gates 10,1
By the action of 1, the operation clock g14 of the CPU 2 output from the variable frequency dividing circuit 9 is set to the highest frequency.

As described above, in this embodiment, when one CPU outputs data, the CPU that detects the data and receives the data
Since the operating clock of is set to the highest frequency, its CP
Even if the U is operating at a low speed, the response processing for the transmitted data can be processed at a high speed. Further, in this embodiment, since each CPU is provided with the variable frequency dividing circuit, there is an effect that the optimum operating frequency can be set independently for each CPU.

In this embodiment, as described above, monostable multivibrators are used as the data detection circuits 7 and 12, and the start bit added to the asynchronous data is detected. It may be possible to detect that one word of data has been sent. For example, as the data detection circuits 7 and 12, peripherals that output a data ready signal to an external terminal that receives one word of asynchronous data
This can be realized by using an LSI (Intel 8251 or the like) and using this data ready signal as the detection signal g8 described above.

In this case, the frequency of the operating clock of the CPU does not change during data reception, and the frequency of the operating clock becomes high immediately after the end of data reception, that is, immediately before the received data is analyzed. The period in which the frequency is high becomes short, and the power consumption can be further reduced.

Furthermore, the data detection circuits 7 and 12 may be provided with a determination circuit for determining whether or not the received data is a specific code (for example, bit7 is High).

In such a case, the frequency of the operation clock becomes high only when the data requiring the high-speed response is received, so that the power consumption can be further reduced.

In the first embodiment described above, each CPU is provided with a variable frequency dividing circuit, but as in the second embodiment described below, a plurality of CPUs are provided with a single variable frequency dividing circuit. It may be configured.

The second embodiment of the present invention will be described below with reference to FIGS.

FIG. 5 is a block diagram showing the second embodiment of the present invention, and FIG.
The figure is a timing chart showing the operation timing of the main signal in FIG.

5, the same components as those in the first embodiment shown in FIG. 1 are designated by the same reference numerals. In addition, 30 is an AND gate.

In this embodiment, the operation clocks of the CPU1 and CPU2 are both supplied from the variable frequency dividing circuit 4 as the signal g3. Further, the frequency dividing ratio of the variable frequency dividing circuit 4 is configured to be controlled by the port output signals g6 and g7 of the CPU 1 through the OR gates 5 and 6. Further, the reset signal g22 and the communication g2 as communication data from the CPU2 to the CUP1 are input to the data detection circuit 7 through the AND gate 30.

The operation of this embodiment will be described below with reference to the timing chart of FIG.

In this embodiment, since the same operation clock g3 is input to both CPU1 and CPU2, the frequency of the operation clock of CPU2 can be freely set from CPU1. Therefore, when sending data from CPU1 to CPU2, the response of CPU2 will not be delayed if the operating clock is set to an appropriate frequency.

Next, consider a case where a processing request from CPU2 to CPU1 occurs.

In FIG. 6, before the processing request from the CPU2 occurs (A
(Before the point), it is assumed that the operating clock g3 is set to the minimum of 500 kHz. So, the data from CPU2 as signal g2
When the data is sent to the CPU 1, the data detection circuit 7 detects the generation of this data and outputs a detection signal g8. As a result, the signal g
Both 4, g5 become High, and the operating clock g3 of CPU1,2 becomes the maximum 4MHz at the point A.

Then, when the data ends at the point B, the CPU 1 shifts the signals g6 and g7 to Hig at the point C in order to analyze the received data.
Set the operating clock to 4MHz as h. So D
The detection signal g8 becomes Low at the point, but the signals g6 and g7 have already
Since it is High, the frequency of the operating clock g3 does not change and CPU1
Can perform data parsing at maximum speed.

Then, at the point E, the CPU 1 processes the data analysis process, and executes the process instructed by the received data with the operation clock g3 set to 2 MHz.

As described above, in the operation example described above, the CP
Although the case where the U1 executes the processing has been described, the above data may be the content in which the CPU 2 specifies the frequency of the operation clock. For example, it is conceivable that the CPU 2 sends a change request of the operation clock to the CPU 1 when the CPU 2 performs a process in response to a signal from the outside.

In this case, in this embodiment, the data detection circuit 7 detects the clock change request data sent from the CPU2 to the CPU1 and once sets the operating clock to the maximum frequency, so that the CPU2 can execute the processing at the maximum speed. effective.

By the way, in this embodiment, as shown in FIG. 5, the reset signal g22 is inputted to the data detection circuit 7 through the AND gate 30. This is the CPU when the reset signal g22 is input.
This is an additional circuit for fixing the frequency of the operation clock g3.

In FIG. 6, when the reset signal g22 becomes Low at the point F, the CPU1 and CPU2 are reset and the port of CPU1 becomes the input state or the high impedance state. Therefore, the signals g6 and g7 are in an uncertain state.

On the other hand, since the reset signal g22 is input to the data detection circuit 7 through the AND gate 30, the data detection circuit 7 detects it and outputs the detection signal g8, and fixes the signals g4 and g5 to High. As a result, the operating clock g3 is not unstable even during reset and is fixed at the highest frequency.

As described above, as an effect peculiar to this embodiment, when the reset signal g22 is input, the frequency of the operation clock g3 is fixed to 4 MHz, so that the CPU port output is in the high impedance state. The effect is that a stable operation clock can be obtained.

Of course, also in this embodiment, as in the first embodiment, the operating clock can be set to the highest frequency in response to the request from one of the CPUs, so that even if the CPU is operating at a low speed, There is an effect that a high speed response can be made to the transmitted data.

Furthermore, in this embodiment, since one CPU can be configured with one variable frequency divider circuit for two CPUs, there is an effect that the scale of hardware can be reduced.

In the embodiment described above, the operation clock is changed by detecting the communication data between the CPUs, but the operation clock is set according to the requests from a plurality of CPUs as in the third embodiment described below. It may be done.

FIG. 7 is a block diagram showing the third embodiment of the present invention.

In FIG. 7, the same circuits as those in the second embodiment shown in FIG. 5 are designated by the same reference numerals. In addition, 13 is a comparison circuit that compares the signals g6 and g7 from the CPU1 with the signals g10 and g11 from the CPU2 and outputs the signal that sets the frequency of the operation clock higher. A monostable multivibrator 14 detects the reset signal g22 and outputs a detection signal g8.
In this embodiment also, the output g3 of the variable frequency dividing circuit 4 is the CPU1
It is supplied as an operating clock to both CPU and CPU2.

The operation of this embodiment will be described below.

CPU1 and CPU2 use the signals g6 and g that set the operating clock g3.
7 and signals g10 and g11 are output. The comparator circuit 13 outputs the signals g6, g
7 and the signals g10 and g11 are compared, and the signal that requires the higher operating clock frequency is output. Based on this output, the variable frequency dividing circuit 4 sets the frequency dividing ratio and outputs the operation clock g3 of the CPU. Therefore, the operating clock g3 is always set to the higher frequency of the frequencies required by the CPUs 1 and 2.

For example, when both CPUs 1 and 2 are idle and the operating clock is set to the lowest frequency, the operating clock g3 becomes the lowest frequency. In this state, when the signal g7 from the CPU 1 becomes high level, the output g23 of the comparison circuit 13 also becomes high level.
As a result, the frequency of the operating clock g3 is set to 1 MHz. After this, the CPU 2 outputs a request to set the operation clock g3 to 2 MHz, and when the signal g10 is High and the signal g11 is Low level, the comparison circuit 13 compares the signals g6, g7 with the signals g10, g11,
Output signals g10 and g11 requesting 2MHz. As a result, the CPU operating clock g3 becomes 2 MHz.

Further, when the reset signal g22 is input, the monostable multivibrator 14 detects this and raises the signal g8 to the high level, so that the operation clock g3 of the CPU is fixed to 4 MHz during the reset. This operation is similar to that of the second embodiment.

As described above, in the present embodiment, the operation clock frequency setting request output from the CPU1 and CPU2 is compared by the comparison circuit 13, and the higher frequency is always set, so that it is necessary for the processing. There is an effect that the operation speed can always be secured. Furthermore, even when sending data from one CPU, the data receiving CPU processes the received data at the maximum speed by sending the data after setting the frequency of the operating clock g3 to the maximum frequency. The effect is that you can do it.

〔The invention's effect〕

As described above, according to the present invention, in a system using a plurality of microprocessors, when a processing request is issued to another microprocessor from another microprocessor, the second frequency division is performed. By the ratio setting signal,
If the frequency of the operating clock of the microprocessor is set to, for example, the highest frequency, the microprocessor can execute the processing in response to the request at high speed. Further, in other cases, the first or second
If the frequency of the operating clock of the microprocessor is set as low as necessary by the frequency division ratio setting signal of
The microprocessor consumes less power.

Moreover, since each of the plurality of microprocessors is equal and there is no relationship between the master and the slave, it is not necessary to know the processing amount of each other, so that the operating program does not have to be complicated. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention, and FIG.
FIG. 3 and FIG. 3 are timing charts showing the operation timing of the main signal in FIG. 1, FIG. 4 is a circuit diagram showing a concrete example of the variable frequency dividing circuit in FIG. 1, and FIG. FIG. 6 is a block diagram showing the second embodiment, FIG. 6 is a timing chart showing the operation timing of the main signal in FIG. 5, and FIG. 7 is a block diagram showing the third embodiment of the present invention. Explanation of symbols 1,2 …… CPU, 3,8 …… oscillation circuit, 4,9 …… variable frequency dividing circuit,
5,6,10,11 …… OR gate, 7,12 …… Data detection circuit, 13
…… Comparison circuit, 14 …… Monostable multivibrator, 30 ……
… And gate.

Claims (3)

[Claims] 1. A system comprising a plurality of equal microprocessors for exchanging data with each other, comprising: clock generating means for generating a reference clock; and dividing the reference clock to obtain the plurality of microprocessors. Among them, at least an operation clock serving as an operation reference of the first microprocessor is output, and a variable frequency dividing means having a variable frequency division ratio, and the first microprocessor outputs the operation clock according to the processing state of its own processor. A first division ratio setting signal and a second division ratio setting signal output in association with data exchange between the plurality of microprocessors other than the first microprocessor. A frequency division ratio setting means for selecting one of the two and setting the frequency division ratio of the variable frequency division means according to the frequency division ratio setting signal. In addition, the frequency division ratio setting means sets the frequency division ratio setting signal of the first and second frequency division ratio setting signals, whichever has a higher frequency of the operation clock output from the variable frequency division means. An operating clock generator for a microprocessor, comprising means for selecting and setting a frequency division ratio. 2. The operation clock generator according to claim 1, wherein the second frequency division ratio setting signal is output from a second microprocessor different from the first microprocessor. The detecting means for detecting the data signal sent to the microprocessor of (1) comprises a detection signal output when the data signal is detected, and the division ratio set by the second division ratio setting signal is An operating clock generating device for a microprocessor, wherein the dividing ratio is such that the frequency of the operating clock becomes the highest frequency that can be set. 3. The operation clock generator according to claim 1, wherein the second frequency division ratio setting signal is output from a second microprocessor different from the first microprocessor. An operating clock generator for a microprocessor characterized by the above.