JPH0690609B2 - Display controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image display device, and in particular, a screen of the display device is divided into a plurality of display areas in the horizontal direction, and a plurality of display information is cut out into each display area. The present invention relates to a display control device that associates and generates a display signal.

[Conventional technology]

Using a raster scanning cathode ray tube (hereinafter referred to as CRT) as a display device, the function of displaying information such as sentences (texts), figures, images stored in a memory (for example, refresh memory using dynamic memory) is This is one of the important functions of the image processing apparatus.

Traditional devices such as character terminals mainly displayed simple alphanumeric characters, but recent business personal computers and word processors use interactive processing to display menus or display screens in certain areas on the screen. Advanced features, such as scrolling some, are needed.

Conventionally, in this type of device, information to be displayed on the screen, such as text, graphics, and images, is stored in a refresh memory, and the display control device sequentially reads the display information in synchronization with the scanning timing of the CRT and displays the image. A method of displaying by converting to a signal and supplying to the CRT is adopted.To display the CRT screen such as a menu display by dividing it into multiple display areas, an external circuit or device It was realized by software processing in the central processing unit. However, this increases the number of parts and sacrifices the processing capability of the central processing unit, so that a display control device having this function is desired.

FIG. 6 shows a block diagram of a conventional display system, and display control of a split screen will be described. The apparatus of FIG. 6 controls the operation of the entire system by the central processing unit 41, stores programs and processing data to be executed by the central processing unit 41 in the main memory 42, and uses the keyboard 44 and the keyboard 44 via the peripheral control unit 43. Interface to external storage disk 45, display controller 47
Various display functions are realized by operating the display data of the display memory 48 to display a desired screen on the CRT via. The display control device 47 addresses the display memory 48 in synchronization with the display timing generated inside itself, and converts the read display data into parallel-to-serial conversion by the video signal generation circuit 49 to generate a serial video signal. Supplying to CRT50.
Here, the central processing unit 41, when changing the display on the CRT, gives a command for drawing or editing to the display control unit 47 to rewrite the stored data in the display memory 48 or a command for changing the operation parameter for designating the display operation. give.

When displaying a split screen on a conventional device, the display data is stored in the display memory 48 by the image and the address allocation shown in FIG. 7, and further edited in addition to the CRT screen area shown in FIG. Storage area for screen information is also displayed Memory 48
Is assigned to.

Here, one address of the display memory corresponds to one small section of the display, one display row is formed corresponding to the number k of horizontal display sections of the CRT screen, and k consecutive addresses from the start address SAD of the CRT display. The display data for the first display row was stored in the address of, and the data of the subsequent display rows were stored in units of k addresses from the subsequent address SAD + k.

The display controller 47 sets the specified address of the display memory to the display start address SAD of the CRT screen at the display start timing of the screen such as vertical synchronization, and sequentially updates the specified address of the display memory at the valid display timing to display the display data. Read out. In the example of FIG. 7, the designated address becomes SAD + k at the horizontal retrace line timing after the scanning of the first display row is completed, and in the next horizontal scanning, the display data for one display row is read out using that address as the leftmost display section. ing.

Here, it is necessary to display the operation mode in the upper part of the CRT screen and the input data and the information of the function key in the lower part from the function of the device, but the display information is read from the display memory at the address corresponding to the display position and the CRT is displayed. Since the display signal for the above is generated, the meaning of each information is associated with the display line of the display memory, and the storage address of each information is managed by the program executed by the central processing unit 41.

[Problems to be solved by the invention]

In the above-mentioned split screen display, when a part of a large edit screen is cut out and displayed, a command is given to the data transfer by the program processing of the central processing unit 41 or the display control device 47, and the edit screen area of the display memory 48. The display data was copied to the CRT screen area by designating the address in and the address of the display line in the divided CRT screen. Here, when moving the screen of the CRT such as scrolling, the command for display data transfer is given to the display controller 47 to
The display data of the edit screen portion of the T screen is shifted by one display line, and the display information of the corresponding display line in the edit screen area is copied to the display line vacated by the shift. further,
When changing the display content of the edit screen, such as when a character is inserted in the edit screen, it is necessary to cause the central processing unit 41 to perform a troublesome process such as transferring display data to match the display of the CRT screen. there were.

Further, since the display memory is provided with two storage areas, an edit screen and a CRT screen, a large capacity memory is required, and a display method that does not use an extra memory has been desired. Furthermore, since the screen is moved by data transfer in the display memory 48, it takes time to transfer the data in the memory, and the response time for changing the CRT display is slowed down.

In addition to the above-mentioned method, a method of modifying the access address to the display memory of the display control device 47 according to the division state of the screen by hardware has been proposed. Economical disadvantages such as a register for storing the designated state, a comparator for judging the status of horizontal / vertical scanning, and an arithmetic unit for address modification are required, and the cost of the display controller increases as the number of circuits increases. was there.

It is an object of the present invention to improve the operability and economy of a split screen and improve the display performance, and it is possible to adjust the split screen in real time according to the split status of the screen in real time, with only minimum hardware. It provides a means for generating a display signal to a CRT while changing an address for reading display data.

[Means for Solving the Problems] The present invention has been described above, in which the display control device switches the designated address of the display memory in synchronization with the display timing (in particular, horizontal scanning) in accordance with the division status of the screen. It is recognized that the display data can be read directly from the storage area of the edit screen of the display memory and the display signal to the CRT can be generated. A program counter and a plurality of state registers for storing the state of the execution result of the instruction, and means for selecting one set from the program counter and the state register are provided, and the program counter is synchronized with the horizontal scanning timing generated by the display timing control section. The status register selection was switched, and the selected program counter was used to address and read. According to a program, the position of vertical scanning is counted, the boundary of the horizontal division is determined, and the address information of the display data storage unit corresponding to the screen to be displayed next is set in the display address designation unit.

〔Example〕

FIG. 1 is a block diagram of a display controller according to an embodiment of the present invention. A display system is configured by connecting a display memory 2, a video signal generating circuit 3 and a CRT 4 similar to those in the conventional art to a display control device 1 shown by a dotted line in the figure.

The display control device 1 includes horizontal and vertical display timing control units that generate display timings, a display memory control unit that controls display memory addresses and data, and a display memory that receives commands from the central processing unit of the system. There is a control processor unit that processes the display information of the above and operates the display timing and the control unit of the memory. It should be noted that although there is a portion for transferring commands and data to and from the central processing unit of the system, it is omitted because it is the same as the conventional one.

The control processor unit has two program counters 11 and 12 for specifying the address of the program to be executed, two status registers 13 and 14 for holding the operating state of the program, and temporary storage of processing data and addressing of the memory. General-purpose register 15 used for the operation and arithmetic circuit 16 that performs arithmetic logic operation
An instruction decoder 17 that takes in and decodes an instruction word to be executed to generate a control signal, a program memory 18 that stores a program, a data memory 19 that stores variables such as display control parameters, and program switching. Has a control flag 20 for controlling

In the main program such as command processing from the central processing unit, the control flag 20 is reset, and its output passes through the inverting circuit to the first program counter 11 and the first program counter 11.
Select the status register 13 of the
The instruction word read by addressing the program memory 18 in 11 is sent to the instruction decoder 17 via the internal bus 21,
Based on a control signal generated by the instruction decoder 17, processing data is transferred between the general-purpose register 15 or the data memory 19 and the arithmetic circuit 16 to perform arithmetic / judgment processing. Here, the first status register 13 is selected and stores a status such as a carry generated in the arithmetic circuit 16. As described above, the first program counter 11 and the status register 13 are used for executing the processing based on the command from the central processing unit, that is, the processing for the display data and the processing for the display parameter.

In the display memory control unit, a display address counter 22 that generates a display memory address of information to be displayed, a raster count 23 that counts the number of rasters in the display section, and a signal of the internal circuit are selected and displayed in the display memory 2. There is an interface circuit 24 for transmitting address and data signals. When operating display data in command processing, data on the internal bus 21 is selected as an address and data signal to the display memory 2, and when reading display information to the CRT, display is performed. The address counter 22 and the raster counter 23 are selected and used as output signals.

The display timing control section includes a horizontal timing control circuit including a horizontal counter 26 for counting the number of horizontal dots in the display section and the number of display sections in addition to time parameters such as horizontal synchronization, erasure, effective display, and blanking of the CRT. Like 25
There is a vertical timing control circuit 27 including a vertical counter 28 which indicates vertical time parameters and vertical position of the CRT, and which respectively generate a display partition timing signal, a horizontal timing signal and a vertical timing signal.

Here, the display parameters of the CRT are the same as the conventional ones, and therefore the description thereof will be omitted, and the display memory address control will be described. The display partition signal is a horizontal timing control circuit for each dot time of one display partition of the display memory.
25, the display address counter 22 increments and the video signal generating circuit 3 performs parallel-serial conversion, and the display address is added to the address value of the information to be output next to the CRT 4 each time one display section time elapses. The counter 22 will be updated. The horizontal timing signal is generated by the horizontal timing control circuit 25 every time the horizontal display time of the CRT is over, sets the control flag 20, and causes the flag output to select the second program counter 12 and the status register 14. In the apparatus of the embodiment, the selected second program counter 12 and the status register 14 are used to execute the second program processing for determining the vertical scanning status and setting the display address corresponding to the division of the CRT screen. It is done.

In the following, FIG. 2 shows the display memory contents and the screen image of the CRT in addition to the control variables, and FIG. 3 shows the flowchart of the second program process, and the process of switching the display address of the divided CRT screen in real time will be described. .

As shown in FIG. 2, the apparatus of the embodiment handles four split screens, and the display represented by the vertical start count value and the start addresses DA ₁ to DA _{4 in} which the display information of each split screen is stored. There is control information of positions YP ₁ to YP ₄ , and a flag VBF indicating that the current second program processing is the blanking period of the CRT and a vertical blanking area indicating the time in vertical raster units. Similarly, the size VSB, the effective display area size VSA indicating the time of the effective display area of the CRT, the maximum number of rasters MRC indicating the vertical raster number of one display section or one display row, and the number of display sections of one display row are set. There is a display line address pitch PIT shown and a display screen number SNO that specifies the number of a split screen to be displayed next.
It is stored in the data memory 19 of the apparatus as a variable to be referred to in the program processing. Further, in the processing of the flow shown in FIG. 3, for the hardware of the vertical counter 28, the display address counter 22, and the raster counter 23, a control variable VC indicating the vertical timing, a control variable MAC designating the start address of the display data read, 1 The operation of setting or modifying the control variable RC that indicates the raster position in the display line is performed. Further, in FIG. 3, SNO is a display screen number indicating the screen number of the split screen to be displayed next. The definitions for each of the variables described above are summarized below.

DA1 to 4: Screen start address: Indicates the start address of the display information of split screens 1 to 4.

YP1 to 4: Display position; Display positions based on split screens 1 to 4 vertical raster count value.

VBF: Vertical blank period flag; indicates that the current second program process is the CRT blanking period.

VSB: Vertical blank area size; shows the total number of rasters in the vertical blanking period.

VSA: Effective display area size; Indicates the total number of rasters in the CRT effective display area.

MRC: maximum number of rasters; indicates the number of rasters in one display section in the vertical direction of the display screen.

PIT: Display line address pitch; Indicates the number of display blocks on one display line.

SNO: Display screen number; Indicates the screen number of the split screen to be displayed next.

Further, FIG. 2 also shows the relationship between the display screen and the display memory.

As shown in FIG. 2, in one embodiment of the present invention, control can be performed without associating the display position of the CRT screen with the display data storage area of the display memory, and the display address counter 22 and the raster counter can be used by using the above-mentioned control information. By operating 23, only the display data storage area is accessed and the information to be output to the CRT is read according to the vertical scanning condition.

When the horizontal timing signal is generated from the horizontal timing control signal 25, the control flag 20 is set, the second program counter 12 and the status register 14 are selected, and the processing of the flowchart of FIG. 3 is started. Since the first program counter 11 and the status register 13 are not selected, they hold the execution status value of the main program immediately before the register switching.

In the program started by the horizontal timing signal, first, "1" is added to the vertical counter VC to set the next vertical position (step), and the vertical blanking period flag VBF is determined to determine the vertical scanning state (step). ). When the blanking period flag VBF is set to "1", the CRT scan is in vertical blanking, and when it is reset to "0", it is the effective display area. Performs processing such as address update of display data.

In the blanking period, the vertical counter value VC and the vertical blanking area size VSB are compared to determine whether the period has ended. If they do not match, the blanking period is still in progress, so the second program The process ends (step). If they match, the blanking period flag VBF is reset to “0” and the vertical counter VC is also set to “0” when the blanking period ends and the effective display area is reached.
Clear to (step,). Next, in order to display the first split screen, the display screen number SNO is set to "1" (step), and the display start address DAn of the screen corresponding to the content n of the display screen number SNO, that is, the first The display start address DA1 of the screen is read and stored in the display address counter MAC (step). Then, add "1" to the display screen number SNO so that it becomes the screen number to be displayed next (step), and clear the raster counter RC to "0" to initialize the raster position in one display line. , And terminates the second program processing (step).

As a result, the vertical timing control circuit 25 generates the vertical timing signal, and the generation of the display signal to the CRT is started. Here, the display data is read from the display start address DA1 of the first screen, and in the example of FIG. 2, the display is performed on the CRT in the order of "a", "b", and "c". .

If the vertical blanking period flag VBF is determined to be the valid display period (step), the vertical counter VC and the valid display area size VSA are compared to determine whether the valid display period has ended (step). If they match, the vertical blanking period flag VBF is set to "1" and the vertical counter VC is cleared to "0" at the end of the effective display period and the blanking period, and the second program processing ends. Yes (step,). If they do not match, the display period is still valid, and the display address is updated and the split screen is switched as described below.

Display position Y of the screen specified by the content n of display screen number SNO
By comparing Pn with the vertical counter VC, it is determined whether the next split screen will be displayed (step), and it is detected that the screens are switched by coincidence, and the display address counter MAC of the display address counter MAC is detected as in the case of the first screen. The setting (step) display screen number SNO is updated (step), the raster counter RC is initialized (step), and the second program processing ends. It is detected that the display position YPn and the vertical counter VC do not match within the split screen (step), the raster counter RC and the maximum raster counter MRC are compared to determine the end of one display line (step), and the CRT does not match. It is judged that the display is within one display line, "1" is added to the raster counter RC to make it the next raster of the character line (step), and it is judged that the display of one display line is completed by the match, and the display address counter MAC Is added to the display row address pitch RIT to update to the next display row, and the raster counter RC is initialized to "0" (step,), and the second program processing is ended.

When a series of processing is finished, execute the instruction to return to the previous main routine processing, reset the control flag 20,
Based on the held contents of the first program counter 11 and the status register 14, the interrupted program processing is restarted.

In this way, the judgment is made based on the values of the raster counter 23 and the vertical counter 28 and the control variables, and the display start address of the split screen is set in the display address counter 22 and the display line pitch is calculated, whereby the second In the example of the figure, the display data is read from the first display start address DA1 at the first display position YP1, the display row is updated every predetermined number of horizontal scans, and the display position becomes the position YP2 of the second screen. At the same time, switch to the second display start address DA2, switch to the start address DA3 at the third screen position YP3, and switch to the start address DA4 at the fourth screen position YP4, and display data from the display memory area where the addresses are discontinuous. Can be read.

Therefore, the storage area of the display data can be set in correspondence with the meaning of the display information on the CRT screen, and the display position and the display information can be associated in real time when the display signal is generated. Furthermore, since the display memory 2 can be accessed by skipping addresses that do not need to be output to the CRT, it becomes possible to overlap the storage area of the CRT screen with the storage area of the edit screen.

In the processing shown in FIGS. 2 and 3, the screen boundary is determined based on the display position of the split screen. However, in the apparatus of the embodiment of FIG. 1, how to set and determine the processing variable is determined. By changing the height, it is possible to perform processing based on the height of the split screen. The main points will be described with reference to FIG. 4 and the flow chart of the control variables in the processing.

The program shown in FIG. 5 also handles four split screens in the same manner, and the display position designation YP of the split screen of the embodiment shown in FIG.
Instead of 1 to YP4, control variables for split screen height designation DH1 to DH4 are set, and a control variable for display height counter DHC is added to count the value.

Of the processing by the second program, the processing is the same except for the processing for judging the switching of the divided screens, such as vertical area determination, vertical count, display line determination, raster count, display address update, etc. In the flowchart, the same step numbers as those in FIG. 3 are attached.

In the process shown in FIG. 5, in addition to the operation of setting the display start address DAn of the screen specified by the content n of the display screen number SNO in the display address counter MAC when the vertical blanking is changed to the effective display area, Transfer the screen height DHn to the display height counter DHC (step). The range of the split screen is detected by subtracting "1" from the display height counter DHC and decrementing it, and determining the borrow that occurs as a result (step,). When no borrow occurs, the split screen is detected. The raster counter and the display address are updated within the area, and when a borrow occurs, it is the boundary of the split screen and the screen control information corresponding to the display screen number SNO is set in the display address counter MAC and the display height counter DHC ( Step,).

As a result, a borrow occurs at the number of horizontal scans corresponding to the values set in the display heights DH1 to DH4 of each split screen, and the screens are switched.

Therefore, according to the present invention, even with the same hardware,
By changing the judgment condition of the processing by the second program, various screen division functions can be realized, and it is possible to provide a function which is optimum as a display system and which minimizes the load on the central processing unit.

In terms of hardware, simply providing a second program counter 12, a second status register 14 and a control flag 20,
Since the arithmetic circuit 16 and the data memory 19 of the control processor unit can be shared to perform arithmetic operations and determination, it is not necessary to provide a special circuit such as a comparison circuit or an arithmetic circuit. Here, the processing of the main program is temporarily interrupted for the screen division processing, but the processing time is short due to simple comparison and transfer, and the program can be switched by simply setting / resetting the control flag 20, It is faster than a generally known interrupt that saves and restores the program counter and status register to the stack, and has the least effect on the processing capacity and performance of the main program.

〔The invention's effect〕

As described above, the present invention sets the display data storage area regardless of the display position of the CRT in the control of dividing the CRT screen and reading the display data from the plurality of data storage areas to generate the display signal to the CRT. Can, edit screen and CRT
The display information on the screen can be stored in the same display memory, and the capacity of the display memory can be minimized.

Further, according to the present invention, even when the display on the CRT is moved, it is only necessary to change the control variable of the display start address of the split screen, there is no need to copy the display data in the display memory, and the usability is good. A display system with a fast display response can be configured.

Furthermore, by simply adding hardware that switches the program processing in synchronization with the horizontal scanning timing, complex processing such as judgment and calculation of screen division control can be performed using the hardware of the control processor, By sharing the hardware, it is possible to provide an inexpensive display control device with high flexibility in processing functions.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a display control device according to an embodiment of the present invention, FIGS. 2 and 4 are diagrams showing display memory contents, CRT screen images and control variables, and FIGS. 3 and 5 are screens. FIG. 6 is a flow chart of division processing, FIG. 6 is a configuration diagram of a conventional display system, and FIG. 7 is a diagram showing correspondence between a display memory address and a CRT screen in screen division display of a conventional apparatus. 1,47 …… Display control device, 2,48 …… Display memory, 3,49 ……
Video signal generation circuit, 4,50 ... CRT, 11,12 ... Program counter, 13,14 ... Status register, 15 ... General purpose register, 16 ... Operation circuit, 17 ... Instruction decoder, 18 ... Program Memory, 19 ... Data memory, 20 ... Control flag, 21 ... Internal bus, 22 ... Display address counter, 23
...... Raster counter, 24 ...... Interface circuit, 25 ...
… Horizontal timing control circuit, 26… Horizontal counter, 27…
… Vertical timing control circuit, 28… Vertical counter, 41…
... Central processing unit, 42 ... Main memory, 43 ... Peripheral control unit,
44 …… keyboard, 45 …… disk.

Claims (1)

[Claims] 1. A display data storage unit for storing display information,
A display timing control unit for generating display timing, a display address designating unit for designating an address of the display data storage unit and updating the address in accordance with the display timing, and a control processor for processing the display information,
The display screen is divided horizontally into multiple display areas,
In an image display device that cuts out a plurality of pieces of display information and displays them in association with each display area, a plurality of program counters that specify addresses of instruction words, and a plurality of states that store states of execution results of instructions in the control processor. A register and means for selecting one set from the plurality of program counters and the plurality of status registers are provided, and selection of the program counter and the status register is switched in synchronization with a horizontal scanning timing from the display timing control unit, The program read by addressing with this switched program counter detects the absolute display position or relative display position on the screen to determine the boundary of the horizontal division, and the screen to be displayed next. Address information of the display data storage unit corresponding to the above is set in the display address designation unit. Display control device according to claim.