JPH0690259B2 - Semiconductor integrated logic circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated logic circuit, and more particularly to a logic circuit having a scan path configuration.

[Conventional technology]

Conventionally, this type of scan path configuration includes the configuration shown in FIG. In the figure, flip-flop groups F41 to F43, F44
The switches F41 to SW43 and SW44 to SW46 can switch the shift register configuration, that is, the scan mode and the normal mode. In the scan mode, the input signal is input from the scan-in terminal SIN and output to the scan-out terminal SOT. In the normal mode, the logic circuit A is connected to the data terminal of each flip-flop.
Alternatively, the signal from B is input, and the output of each flip-flop is input to the logic circuit B or C at the next stage. The clock terminal C of each flip-flop is commonly the clock terminal CL
K is connected, and the reset terminal R is commonly reset terminal RST
It is connected to the.

In such a configuration, the clock terminal C and the reset terminal R of each flip-flop circuit are directly output to the external terminals. However, in an actual logic circuit, the clock terminal, the set terminal, and the reset terminal of each flip-flop circuit have other logics. It is often controlled by a circuit. FIG. 5 shows that the clock terminal C of the flip-flop circuits F51 and F52 has another logic circuit NAN.
FIG. 6 shows an example in which the set terminal S of the flip-flop circuits F61 and F62 is controlled by another logic circuit NAND6, which is controlled by D5.

Generally, in the scan path test, if there is a logic circuit that controls the clock terminal or the set / reset terminal of the flip-flop circuit in this way, it is necessary to take measures such as bypassing the logic circuit. become unable.

[Problems to be solved by the invention]

In the conventional method described above, the scan path test method cannot be used when testing the clock circuit of the flip-flop circuit and the logic circuit that controls the set / reset system. It has the drawback that it must be tested by inserting a test pattern from the terminals and measuring the signal at the output terminals.

[Means for solving problems]

An object of the present invention is to provide a semiconductor integrated logic circuit capable of increasing the test efficiency in the scan path test method with a simple configuration.

A semiconductor integrated logic circuit according to the present invention has a logic circuit section and a plurality of flip-flops provided corresponding to a plurality of outputs from the logic circuit section, and a scan path test is performed on the plurality of flip-flops. In a semiconductor integrated logic circuit having a scan path configuration for
Among the plurality of flip-flops, for a flip-flop in which a signal applied to its clock terminal, set terminal or reset terminal is generated from a logic circuit, a corresponding output from the logic circuit section to a data terminal of the flip-flop. Alternatively, a selector circuit is provided, which selects and gives a signal from the logic circuit.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows the basic circuit configuration of the present invention.

In FIG. 1, flip-flop circuits F11 and F12 are flip-flop circuits that can be configured as a scan path by inserting a switch SW11 on the side a. The logic circuit section A1 is a flip-flop circuit during normal operation
A logic circuit connected to the data input D of F11, and the logic circuit section B1 is a logic circuit that cannot be tested by the conventional scan path test.

In such a connection, the switch SW11 is placed on the b side and the switch SW12 is placed on the c side for normal operation. Then, the switch SW11 is placed on the a side to make the flip-flop circuits F11 and F21 into a shift register configuration to perform the scan path operation. By performing the test, the logic circuit unit A1 can be tested. Similarly, when the switch SW11 is on the b side and the switch SW12 is placed on the a side, the logic circuit section B1 can be tested by the scan path operation.

FIG. 2 shows an embodiment of the present invention. In FIG. 2, the logic circuit section A2 is a logic circuit connected to the data input D of the flip-flop circuit E21 during normal operation, and the logic circuit section B2 is a logic circuit connected to the clock c of the flip-flop circuit F21 during normal operation. Circuit. SW21, SW22, and SW23 are switches, and SCLK is a scan clock terminal in the scan path shift register mode. In such a connection, when the clock of the flip-flop circuit F21 is switched by the switch SW22 during the scan path test, the flip-flop circuit F2 is switched at the time of switching.
The switch SW22 must always select the scan clock during the scan path test because an active edge may appear for the clock of 1. In such a case, the logic circuit section B2 cannot be tested.
The output of B2 can be connected to the data of the flip-flop circuit F21 by using the switch SW23.

FIG. 3 shows another embodiment of the present invention.

In FIG. 3, a flip-flop circuit F31 is a circuit in which a −latch is replaced with a flip-flop circuit in order to form a scan path configuration, and a logic circuit portion A3 is a logic circuit connected to a set terminal of a −latch. The circuit section B3 is a logic circuit connected to the reset terminal of the-latch. The OR circuits OR31 and OR32 are logic circuits for preventing the flip-flop circuit F31 from being set or reset by inputting a high level to e and f during the scan path test. The AND circuit AND1 is a logic circuit. Part A
A switch SW31 is a flip-flop circuit, which is a logic circuit for inputting a signal from 3, B3 to the flip-flop F31.
This switch switches F31 between shift register mode and normal mode.

By such a connection, the logic circuit section of the RS latch system, which was previously untestable by the scan path test, can be tested on the logic circuit section of A3 by setting the output of the logic circuit section B3 to a high level. By setting the output of the logic circuit section A3 to a high level, the logic circuit section of B3 can be tested.

It goes without saying that the AND circuit AND1 may be another logic circuit.

〔The invention's effect〕

As described above, according to the present invention, a switching circuit is provided at the data terminal of a flip-flop circuit that can be configured as a scan path, and a plurality of logic circuit units can be switched and connected.
There is an effect that a logic circuit section that cannot be tested by the conventional scan path test can be tested.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a basic circuit configuration of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of another embodiment of the present invention. FIG. 4 is a block diagram of a basic circuit configuration of a conventional scan path, and FIGS. 5 and 6 are block diagrams showing problems in the conventional circuit. F11 to F12, F21, F31, F41 to F46, F51 to F52, F61 to F62 ... Flip-flop circuit, SW11 to SW12, SW21 to SW22, SW31, SW4
1 to SW46 …… Switch, A1, B1, A2, B2, A3, B3, A, B, C …… Logic circuit block, SCLK …… Scan clock terminal, AND1 …… AN
D circuit, OR31 to OR32 ... OR circuit, SIN ... scan-in terminal, SOT ... scan-out terminal, RST ... reset terminal, CLK ... clock terminal, NAND5 to NAND6 ... NAND circuit.

Claims (1)

[Claims] 1. A scan path for a scan path test, comprising a logic circuit section and a plurality of flip-flops provided corresponding to a plurality of outputs from the logic circuit section, respectively. In the semiconductor integrated logic circuit configured as described above, among the plurality of flip-flops, a signal applied to its clock terminal, a set terminal or a reset terminal is generated from the logic circuit with respect to the flip-flop data. A semiconductor integrated circuit comprising a terminal provided with a selector circuit for selectively providing a corresponding output from the logic circuit section or a signal from the logic circuit.