JPH0690174A - Voltage reader - Google Patents

Abstract

PURPOSE:To improve read accuracy only by increasing constitutive bits by counting the output of a comparator and setting the count value of a period counter, which turns an up/down counter to '0', when the outputs are turned to a prescribed number. CONSTITUTION:An analog command voltage 12 is compared with a triangular wave signal 20, which is generated from a triangular wave generating circuit 13, by a comparator 14 and outputted as a PWM signal 21. The signal 21 is inputted to an up/down counter 16, the number of clock pulses 22 generated from a clock oscillation circuit 15 is counted up while the signal 21 is low, and the number is counted down while the signal 21 is high. On the other hand, the signal 21 is inputted to a period counter 17 as well and the counter 17, with the initial set value set by a period setting circuit 18, and outputs a clear signal to the counter 16 at the time of zero count. Thus, the read accuracy is improved only by increasing the constitutive bits, components are reduced, and a voltage can be accurately read at low cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage reading device such as an analog command input type motor drive device.

[0002]

2. Description of the Related Art Conventionally, a voltage reading device for reading a command voltage from a host controller has been used in an analog command input type motor drive device and the like.

A conventional voltage reading device will be described below. FIG. 2 is a block diagram of a motor drive device including a conventional voltage reading device. In FIG. 2, reference numeral 1 denotes an analog command voltage 12 for controlling the rotation speed or rotation torque of the motor by the analog voltage to the motor drive device.
Is output to the upper controller, 2 is the upper controller 1
The command voltage reading device 3 for converting the value of the analog command voltage 12 from the device into a digital binary code is a speed control calculation 3 for controlling the current flowing to the motor 8 based on the information of the command voltage reading device 2 and the speed detector 11 described later. Bowl, 4
Is an output signal of the speed control calculator 3 and is described later in the magnetic pole detector 1.
Multiplier for multiplying magnetic pole position information of 0, 5 is multiplier 4
, A digital / analog converter (hereinafter abbreviated as D / A converter) that replaces the digital output signal of 6 with an analog signal, 6 is a current amplifier for amplifying the output of the D / A converter 5, and 7 is pulse width modulation for the signal of the current amplifier 6. (Hereinafter, abbreviated as PWM) to drive the motor 8 PW
M inverter, 9 is an encoder directly connected to the rotating shaft of the motor 8, 10 is a magnetic pole detector for detecting the magnetic pole position of the motor 8 based on position information from the encoder 9, 11 is rotation of the motor 8 based on speed information from the encoder 9. It is a speed detector that detects a number.

The operation of the motor drive device constructed as above will be described. The analog command voltage 12 of the rotation speed or torque of the motor 8 given from the host controller 1 is input to the command voltage reading device 2 and converted from analog to digital binary code signal 23. Next, this binary code signal 23 is input to the speed control calculator 3. The speed control calculator 3 compares the speed feedback signal from the speed detector 11 with the binary code signal 23 to calculate an optimum gain for the motor 8. The gain determined by the speed control calculator 3 is multiplied by the magnetic pole position information of the motor 8 from the magnetic pole detector 10 by the multiplier 4 and converted into an analog signal by the D / A converter 5. Next, the analog signal is current-controlled by the current amplifier 6, and the PWM inverter 7
Is converted into pulse width modulation by, and the motor 8 is rotated by supplying electric power suitable for the motor 8. The motor 8 is provided with an encoder 9 directly connected to the shaft. The magnetic pole position information is sent to the magnetic pole detector 10, and the speed information is sent to the speed detector 1.
Feedback to 1.

FIG. 3 is a circuit diagram of a voltage reading device using a conventional dedicated IC which constitutes the command voltage reading device 2 shown in FIG. In FIG. 3, 12 is an analog command voltage, 24
Is a reference voltage power supply, 25 is a resistance matrix that divides the output voltage of the reference voltage power supply 24 into a constant voltage width, 26 is a comparator that compares the analog command voltage 12 with the reference voltage divided by the resistance matrix 25, and 27 is An encoder matrix for converting the output of the comparator 26 into a binary code, 19 is an encoder matrix 27
A latch circuit for holding the output of the latch circuit and outputting it to the outside, 23 is a binary code signal output from the latch circuit 19, 28
Is a clock driver for controlling the operation timing of the comparator 26 and the latch circuit 19.

The operation of the voltage reading device configured as described above will be described below. First, the analog command voltage 12 of the motor input by the host controller 1 is compared by the comparator 26 with the reference voltage divided by the resistance matrix 25, and output as a gray code proportional to the analog command voltage 12. The Gray code is then converted by the encoder matrix 27 into a binary code. Next, the read value of the binary code is held by the latch circuit 19 and output to the speed control calculator 3 of FIG.

[0007]

However, in the above-described conventional configuration, when high accuracy is required for reading the analog command voltage 12, it is necessary to increase the number of bits constituting each of the comparator 26, the encoder matrix 27, and the latch circuit 19. However, there is a problem in terms of the number of parts and cost.

[0008]

In order to solve the above problems, the present invention provides a comparator for pulse-width modulating an input voltage, and an UP for counting up or down the clock from a clock oscillation circuit by the output of this comparator. / DOWN counter and UP / DOWN when the output of the comparator is counted and reaches a predetermined number
A cycle counter for setting the counter to 0 and a cycle setting circuit for setting the count number of the cycle counter are provided.

[0009]

The present invention has the above-mentioned configuration and has the UP / DOWN structure.
The reading accuracy can be improved simply by increasing the number of constituent bits of the counter.

[0010]

1 is a circuit diagram of a voltage reading device according to an embodiment of the present invention. In FIG. 1, 13 is a triangular wave generating circuit, 14 is a comparator for performing PWM conversion of the analog command voltage 12, 15 is a clock oscillating circuit that gives a clock pulse 22 to the UP / DOWN counter 16 at the first stage,
17 is PWM converted by the comparator 14
A period counter for counting the pulses of the signal 21, 16 is a PWM signal 2 PWM-converted by the comparator 14.
The UP / DOWN counter that counts up or down the clock pulse 22 by the pulse of 1; 18 is a cycle setting circuit that sets the cycle in the cycle counter 17; 19 is the output signal of the UP / DOWN counter 16; An output latch circuit, 20 is a triangular wave signal output from the triangular wave generation circuit 13, 21 is a PWM signal of the analog command voltage 12 PWM-converted by the comparator 14, 22 is a clock pulse output from the clock oscillation circuit 15, and 23 is It is a binary code signal of the latch circuit 19 and a signal corresponding to the analog command voltage 12.

The operation of the voltage reading device configured as described above will be described below. The analog command voltage 12 for the speed and torque of the motor is compared and calculated by the comparator 14 with the triangular wave signal 20 generated by the triangular wave generating circuit 13 and output as the PWM signal 21. At this time, if the analog command voltage 12 is Vin (V) and the triangular wave signal 2 is
When the amplitude of 0 is Vt (V), it is necessary to keep the relationship of Vt (V)> Vin (V) in order to avoid saturation of the PWM signal 21.

Next, the PWM signal 21 is input to the UP / DOWN counter 16 and the UP / DOWN counter 16 is supplied.
Counts up the number of clock pulses 22 generated by the clock oscillation circuit 15 while the PWM signal 21 is LOW, and conversely, while the PWM signal 21 is HI, the clock pulses 22 generated by the clock oscillation circuit 15 are counted. Count DOWN the number of pulses.

The PWM signal 21 is also input to a period counter 17 which is a DOWM counter in synchronization with the PWM signal 21, and the period counter 17 has an initial set value set by a period setting circuit 18, and UP /
The clear signal is sent to the DOWN counter 16 and the latch circuit 19
The latch signal is output to.

Now, suppose that the set value of the cycle setting circuit 18 is N,
If the frequency of the triangular wave signal 20 is F (Hz) and the conversion speed required to read the analog command voltage 12 is Ct (S), the conversion speed Ct (S) of this circuit is Ct = N.
/ F.

Further, UP / DOW can be obtained by reading once.
When the oscillation frequency of the clock oscillator circuit 15 is φ (Hz) and the count value of the UP / DOWN counter 16 is Cn, the value counted by the N counter 16 is Vint (V) infinitely close to Vt (V). , Cn = Nφ / F, and when Vin (V) = Vt / 2 (V), Cn = 0.
Becomes

Therefore, Vin (V) = Vt / 2 in advance
If the voltage at (V) is set to 0 (V), Vin
(V) can be read from + Vt / 2 (V) to -Vt / 2 (V).

That is, by increasing the set value N of the cycle setting circuit 18, the reading accuracy of the analog command voltage 12 can be improved. Further, the components to be added at that time are only the UP / DOWN counter 16 and the latch circuit 19, which can be connected to each series to increase the number of output bits.

[0018]

As described above, the voltage reading device of the present invention is
A comparator that pulse-width modulates the input voltage, and U that counts up or down the clock from the clock oscillation circuit by the output of this comparator.
By providing a P / DOWN counter, a cycle counter that counts the output of the comparator and sets the UP / DOWN counter to 0 when it reaches a predetermined number, and a cycle setting circuit that sets the count number of the cycle counter , UP / D
Only by increasing the number of constituent bits of the OWN counter, it is possible to increase the reading accuracy, reduce the number of constituent parts, and inexpensively and accurately read the voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a voltage reading device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a motor drive device including a conventional voltage reading device.

FIG. 3 is a circuit diagram of a conventional voltage reading device.

[Explanation of symbols]

 1 Upper controller 2 Command voltage reading device 3 Speed control calculator 4 Multiplier 5 D / A converter 6 Current amplifier 7 PWM inverter 8 Motor 9 Encoder 10 Magnetic pole detector 11 Speed detector 12 Analog command voltage 13 Triangular wave generation circuit 14 Comparator 15 Clock oscillation circuit 16 UP / DOWN counter 17 Cycle counter 18 Cycle setting circuit 19 Latch circuit 20 Triangular wave signal 21 PWM signal 22 Clock pulse 23 Binary code signal 24 Reference voltage power supply 25 Resistor matrix 26 Comparator 27 Encoder matrix 28 Clock driver

Claims (1)

[Claims] 1. A first counting means for counting a clock from the generating means by a modulating means for pulse-width modulating an input voltage, a generating means for generating a predetermined clock, and an output from the modulating means. And counting the output from the modulation means, and when the predetermined number is counted, the first
And a second counting means for setting the value of the counting means of 0 to 0.