JPH0689982A - Nonvolatile memory cell - Google Patents

Abstract

PURPOSE:To have a sufficient write/read speed and stabilize a spontaneous polarization of a ferroelectric substance thin film, and not to cause any cracks by a method wherein a ferroelectric substance thin film is formed on a gate electrode formed in a separation part between a source area and a drain area and a memory electrode is formed on the ferroelectric substance thin film. CONSTITUTION:A source area 3 and a drain area 4 are separated and formed on the surface of a polycrystalline semiconductor layer. Further, a gate insulation film 9 is formed in this separated part and a gate electrode 10 is formed on the gate insulation film 9. A ferroelectric substance thin film 11 constituting a memory part of a nonvolatile memory is formed, and a memory electrode 12 formed on this ferroelectric substance thin film 11 is formed. Thus, an area of the nonvolatile memory cell is enlarged and a spontanenous polarization is stabilized and any cracks are not caused in the vicinity of the interface of the ferroelectric substance thin film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dielectric of a memory section,
The present invention relates to a structure of a non-volatile memory cell using a ferroelectric thin film.

[0002]

2. Description of the Related Art A semiconductor memory is a RAM from a storage state.
(Random Access Memory) and SAM (Sequential Acces
s Memory), and these are in principle RWM (Read Write Memory) and ROM (Rea
d Only memory), which does not require power to maintain stored contents and does not lose stored contents even when the power is turned off. Non-volatile memory, which requires power to maintain stored contents and is stored when the power is turned off. What loses its content is called volatile memory.

Of these, the RWM RAM is generally called "RAM", and the "RAM" is further divided into static RAM (SRAM) and dynamic RAM (DRAM) from the driving means. The SRAM is composed of a flip-flop circuit, and it is difficult to increase the degree of integration due to its complicated structure. On the other hand, since the storage state can be held with a small amount of power, the power consumption is small and the writing / reading operation is performed. Has the characteristic of being fast.

On the other hand, the DRAM is composed of a capacitor which is a storage unit and a transistor which is an active unit for controlling the storage unit, and an update operation called refresh is performed in order to maintain the charge stored in the capacitor. Since it is necessary, it has a drawback of relatively large power consumption, but has a feature that the degree of integration can be increased due to the simple structure of the memory cell, and is widely used as a main storage device of a computer. .

On the other hand, ROM, which is a non-volatile memory that does not require electric power to maintain storage, includes a mask ROM in which information is written at the manufacturing stage and a PROM (Programmable ROM) in which a user can write information later. This P
The ROM is an EPROM (UV-Erasable PR) that is electrically written and erased by irradiating it with ultraviolet rays.
OM) and EEPROM for electrically writing / erasing
(Eletrically-Erasable PROM) is available.

By the way, in recent years, the International Solid State Circuit Conference (ISS)
MOS in DRAM introduced in CC 88)
A RAM using a ferroelectric thin film as a dielectric of a capacitor used in a storage unit in combination with a field effect transistor (MOSFET) is an FRAM (Ferroelectric RAM).
It is called a RAM, it is non-volatile because it does not require power for memory storage, it is suitable for integration due to its simple structure, it can be driven at a low voltage in a wide temperature range, and α-rays are used. It is attracting attention due to its resistance to soft errors.

This FRAM is disclosed in JP-A-2-94571, JP-A-2-94553, and JP-A-2-290.
As disclosed in Japanese Patent Publication No. 079, it is configured by forming a ferroelectric thin film on a source region on a single crystal wafer or on a gate insulating film.

However, since the area of a single crystal silicon wafer is limited, it is necessary to achieve high integration in order to obtain a larger capacity FRAM using a conventional single crystal. For that purpose, High-level fine processing technology such as submicron processing technology is required. Therefore, there is a problem that a large capacity memory cannot be obtained by the conventional FRAM using the single crystal silicon wafer.

Further, when the semiconductor layer and the ferroelectric layer are directly contacted with each other, the polarization charge of the ferroelectric is not completely canceled by the charge on the semiconductor surface, so that the electric field in the direction opposite to the spontaneous polarization is generated by the ferroelectric. Since it occurs in the thin film, the spontaneous polarization may become thermodynamically unstable.

On the other hand, Japanese Patent Laid-Open No. 3-22483 discloses a memory electrode formed on a glass substrate, a ferroelectric thin film formed to cover the memory electrode, and an amorphous semiconductor formed on the ferroelectric thin film. Layer, a contact layer formed separately on the surface of the amorphous semiconductor layer, and a FRAM including a source electrode and a drain electrode formed on each contact layer
Is listed.

Since this FRAM uses a heat-resistant glass insulating substrate which can easily obtain a large area, not a single crystal silicon wafer having a limited size as a substrate, it uses an advanced fine processing technique. Although it is possible to obtain a large-capacity memory without using it, there is a problem in that since the operating semiconductor layer is amorphous, carrier mobility is low and writing / reading operation cannot be speeded up. ing.

To solve this problem, the operating semiconductor layer may be composed of polycrystalline silicon or single crystal silicon. However, when amorphous silicon is heated to polycrystallize or single crystallize it, a layer below it is formed. The ferroelectric thin film may also be heated to change its crystal structure, causing distortion or cracks near the interface between the ferroelectric thin film and / or the semiconductor layer. .

[0013]

SUMMARY OF THE INVENTION The present invention has the above-mentioned problem, namely, it has a high carrier mobility and a fast write / read operation, but cannot obtain a large-capacity memory. Writing / writing due to the problems and low carrier mobility
At the same time, the problem of the FRAM using an amorphous semiconductor that the read operation cannot be speeded up is solved, and the spontaneous polarization becomes unstable thermodynamically due to the lack of charges on the semiconductor surface and the ferroelectricity. An object of the present invention is to obtain an FRAM having a new structure, which solves the problem that a body thin film is heated and is distorted or cracked.

[0014]

In the present application, in order to solve the above-mentioned problems, "a semiconductor layer formed on an insulating substrate, a source region and a drain region formed separately on the surface of the semiconductor layer, a source A source electrode and a drain electrode respectively formed on the region and the drain region, a gate insulating film formed on the surface of a portion of the semiconductor layer separated from the source region and the drain region, and formed on the gate insulating film. A non-volatile memory cell comprising a gate electrode, a ferroelectric thin film formed on the gate electrode, and a memory electrode formed on the ferroelectric thin film.

[0015]

In the present invention having the above structure, the amorphous semiconductor layer formed on the insulating substrate is heated to be polycrystallized or monocrystallized, and then the FET is formed, and the FET is formed on the gate electrode of the FET. A ferroelectric thin film having spontaneous polarization is formed on, and a memory electrode is formed on the ferroelectric thin film. According to this structure, the spontaneous polarization value induced in the ferroelectric substance is changed by the voltage applied to the storage electrode, and the storage electrode operates as the gate electrode to store the data.

Since the memory cell of the present invention can obtain a large-area memory unlike the conventional one using a single crystal silicon wafer, a large-capacity memory can be obtained without using an advanced fine processing technique. While being able to
Since the formed semiconductor layer is not an amorphous semiconductor layer but a polycrystalline semiconductor layer or a single crystal semiconductor layer, a large carrier mobility can be obtained, a sufficient writing / reading speed can be obtained, and a strong writing / reading speed can be obtained. When the dielectric thin film is sandwiched between metal electrodes, the polarization charge of the ferroelectric substance is completely offset by the charge on the metal surface, and the spontaneous polarization is thermodynamically stable, heating the ferroelectric thin film formed during memory manufacturing. Therefore, there is no strain or crack in the vicinity of the interface with the ferroelectric thin film and / or the semiconductor layer.

[0017]

Embodiments of the present invention will be described with reference to the drawings.
FIG. 1A is a schematic diagram showing a configuration of an embodiment in which the first invention of the present application which employs polycrystalline silicon as a semiconductor layer is applied to a 1-transistor + 1-capacitor DRAM type memory cell. This nonvolatile memory cell is formed on a substrate 1 which is an insulating material such as heat resistant glass. This heat-resistant glass insulating substrate has a large area, and a large number of nonvolatile memory cells are formed on it.

A thickness of 0.1 is formed on the heat-resistant glass insulating substrate 1.
.About.0.2 .mu.m of silicon polycrystalline semiconductor layer 2 is formed.
There is. This silicon polycrystalline semiconductor layer 2 is made of silane (SiH
_Four ) Low-pressure chemical vapor deposition using gas as a raw material at a substrate temperature of 550 ° C
Amorphous silicon layer on the substrate by the method (LPCVD)
Then, the formed amorphous silicon layer is subjected to N at 600 ° C. ₂ 
Silicon is grown by solid phase growth in an atmosphere for 24 hours.
The polycrystalline semiconductor layer 2 is formed.

Then, a doping amount of 5 × 10 ¹⁵ / cm ^{2 is} applied to the surface of the formed polycrystalline semiconductor layer by an ion doping method.
Of the source region 3 and the drain region 4 are formed by implanting phosphorus (P) of the above, and contact layers 5 and 6 are formed on the source region 3 and the drain region 4, respectively. A source electrode 7 and a drain electrode 8 made of Al are formed on 5 and 6.
The contact layers 5 and 6 can be omitted.

On the other hand, the portion separated from the source and drain electrodes on the semiconductor layer is sputtered or CVD.
The SiN _x gate insulating film 9 is formed by the method, and the gate electrode 10 made of platinum (Pt) or the like is formed on the gate insulating film 9.

On the gate electrode 10, a ferroelectric thin film 11 made of lead titanate (PbTiO ₃ ) having a film thickness of 0.6 to 0.8 μm, which constitutes a storage portion of a nonvolatile memory, and the ferroelectric thin film 11 are formed. An electrode (memory electrode) 12 made of Al and formed thereon is formed.

By adopting such a structure, it is possible to prevent Pb atoms or O atoms in the ferroelectric thin film, which are harmful to the silicon semiconductor layer, from entering the silicon semiconductor.

The ferroelectric thin film 11 is lead oxide (PbO).
And using titanium oxide (TiO ₂ ) as a raw material, the substrate temperature is 6
It is formed by magnetron sputtering in an Ar / O ₂ atmosphere at 00 ° C. and about 1 Pa, and is prepared so that the formed film composition has a stoichiometric composition ratio.

Since the non-volatile memory cell is formed on the insulating substrate from which a large area can be easily obtained, a large capacity memory can be obtained without using an advanced fine processing technology unlike the conventional one. In addition to being able to obtain high carrier mobility, a sufficient write / read speed can be obtained.

When the ferroelectric substance is sandwiched by the metal electrodes, the polarization charge of the ferroelectric substance is completely canceled by the charge on the metal surface, so that the spontaneous polarization is thermodynamically stable. Further, since the formed ferroelectric thin film is not heated at the time of manufacturing the memory, no strain or crack is generated in the vicinity of the interface between the ferroelectric thin film and / or the semiconductor layer.

FIG. 1B shows an equivalent circuit of the nonvolatile memory cell shown in FIG. This non-volatile memory cell is composed of a field effect transistor (FET) consisting of a source S / gate G and a drain D and a capacitor, like a normal one-transistor + 1-capacitor DRAM type memory cell. Differently, the dielectric of the capacitor is formed by the ferroelectric thin film 11. As a result, a non-volatile memory cell having a storage characteristic utilizing the hysteresis characteristic of the ferroelectric thin film 11 is formed.

The memory cell of the present invention may be formed of a single crystal semiconductor layer instead of polycrystalline silicon as a semiconductor layer. In that case, the single crystal semiconductor layer is formed by heating a polycrystalline semiconductor layer formed over an insulating substrate with a heating means such as an electron beam or a laser beam to recrystallize the polycrystalline semiconductor layer. Note that the structure of the nonvolatile memory of the present invention is not limited to the one in which the semiconductor layer is formed on the insulating substrate, and can be sufficiently applied even when a single crystal silicon wafer is used.

The semiconductor layer has been described on the assumption that it is not an amorphous semiconductor layer having a low carrier mobility. However, in the structure in which the ferroelectric thin film is covered with the semiconductor layer, there is a difference in thermal expansion coefficient between the two when heated. Because of the crack problem,
The configuration of the present invention can also be applied to a nonvolatile memory cell using an amorphous semiconductor.

In the above description, the case where a single memory cell is formed has been described. However, a commonly used memory is not composed of a single memory cell but a plurality of memory cells on a substrate. Are formed. In this normal memory, when the interaction between the electrodes and / or cells becomes a problem, it is necessary to electrically separate the electrodes and / or the cells. In that case, it goes without saying that in order to form such a memory, it is necessary to form an interlayer insulating film and / or a passivation film for electrically separating electrodes and cells from each other.

Further, by forming a CMOS flip-flop using a polycrystalline silicon thin film and using a ferroelectric thin film as the dielectric of the capacitor, the writing / reading time can be improved and the number of rewritings can be improved. It is also possible to improve.

FIG. 2 shows another embodiment of the present invention. The 1-transistor + 1-capacitor DRAM memory cell shown in this embodiment differs from the embodiment in which the source region 3 and the drain region 4 are formed separately on the surface of the semiconductor layer shown in FIG. It is formed over the entire thickness of the semiconductor layer. By adopting such a configuration, the electric field formed between the source region and the drain region becomes a uniform electric field, so that the control by the gate electrode is more effectively performed.

The invention of the present application can be applied not only to the memory cell having the simple shape described in the embodiments but also to a commonly used trench capacitor or stacked capacitor.

[0033]

As is apparent from the above description, since the nonvolatile memory cell of the present invention can easily obtain a large area, it does not require a sophisticated fine processing technique unlike the conventional one. Since a large capacity memory can be obtained and a large carrier mobility can be obtained, a sufficient write / read speed can be obtained.

Further, the presence of the metal electrode stabilizes the spontaneous polarization thermodynamically, and prevents Pb atoms or O atoms which are harmful to the silicon semiconductor layer from entering the silicon semiconductor layer. it can.

Further, since the ferroelectric thin film formed at the time of manufacturing the memory is not heated, no strain or crack is generated near the interface between the ferroelectric thin film and / or the semiconductor layer.

[Brief description of drawings]

FIG. 1 is a circuit diagram of the present invention including one transistor and one capacitor DR.
FIG. 6 is a schematic configuration diagram and an equivalent circuit diagram of an embodiment applied to an AM type memory cell.

FIG. 2 shows the present invention in which 1 transistor and 1 capacitor DR are used.
FIG. 9 is a schematic diagram of the configuration of another embodiment applied to an AM type memory cell.

[Explanation of symbols]

 1 Insulating Substrate 2 Semiconductor Layer 3 Source Region 4 Drain Region 5, 6 Contact Layer 7 Source Electrode 8 Drain Electrode 9 Gate Insulating Layer 10 Gate Electrode 11 Ferroelectric Thin Film 12 Storage Electrode

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] December 1, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H01L 29/784 29/788 29/792 9056-4M H01L 29/78 311 J 371 (72) Inventor Yuji Tatemura 1-13-1 Nihonbashi, Chuo-ku, Tokyo TDC Corporation (72) Inventor Katsuto Nagano 1-13-1 Nihonbashi, Chuo-ku, Tokyo TDC Corporation

Claims (2)

[Claims] 1. A semiconductor layer formed on an insulating substrate, a source region and a drain region formed separately on the surface of the semiconductor layer, and a source electrode and a drain electrode formed on the source region and the drain region, respectively. A gate insulating film formed on a surface of a space between the source region and the drain region on the semiconductor layer, a gate electrode formed on the gate insulating film, formed on the gate electrode A non-volatile memory cell comprising a ferroelectric thin film and a memory electrode formed on the ferroelectric thin film. 2. The non-volatile memory cell according to claim 1, wherein the semiconductor layer is a polycrystalline semiconductor layer formed on an insulating substrate.