JPH0689348A - Single-chip microcomputer - Google Patents

Abstract

PURPOSE:To maintain the secrecy of the data contents of an internal ROM or internal E<2>PROM by preventing an operation mode in program execution from being changed into an internal ROM operation mode. CONSTITUTION:This microcomputer is equipped with at least an address decision circuit 2, an internal ROM 3, a selector 4, a CPU 5, and a latch circuit 6 corresponding to an external memory 7, and the data input from an operation mode specification terminal 51 and the output signal of a latch circuit 6 generated by the reset signal input from a reset terminal 52 are inputted to the address decision circuit 2. Consequently, the logical value at the operation mode specification terminal 41 at the time of reset mode releasing is held and the logical value at the operation mode specification terminal 51 at the time of a change from a reset level to a non-reset level is latched. The output of the latch circuit 6 does not vary. Therefore, the operation mode in program execution is never changed into the internal ROM operation mode at the start of operation in external memory operation moded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single chip microcomputer.

[0002]

2. Description of the Related Art FIG. 6 shows an example of a conventional single-chip microcomputer in which an external memory operation mode can be set via an external terminal. As shown in FIG. 6, the single-chip microcomputer 1 of the conventional example corresponds to the external memory 7 and corresponds to the address determination circuit 2.
And an internal ROM 3, a selector 4, and a CPU 5. Other components such as the internal RAM and the timer circuit are not shown in FIG. 6 because they are not directly related to the present invention. Further, FIG. 7 is a flow chart showing a procedure for reading the contents of the internal memory in this conventional example, and FIG. 8 is a diagram showing an arrangement of an internal ROM read program in the conventional example.

The internal address bus 201 supplies address information to each constituent block of the single-chip microcomputer 1 and also supplies address information to the external memory 7 through the address bus interface terminal. . Address determination circuit 2
Is a circuit for determining whether the input address information is an address indicating the internal ROM 3 or an external memory 7, and this address determination circuit 2
In the case where the level at the operation mode designating terminal 57 is an external memory operation designating level (hereinafter referred to as Ex level), a level signal that operates to select the external memory 7 regardless of the address information. Is output and sent to the selector 4. The selector 4 receives the level signal output from the address determination circuit 2, and outputs the output of the internal ROM 3 and the external memory output input to the selector 4 via the external data bus 203 and the interface terminal. Either one is selected and output to the internal data bus 202. In addition, internal data
The bus 202 supplies processing data to each constituent block of the single-chip microcomputer 1, and
External data bus 203 via interface terminal
It is connected to the.

The CPU 5 executes the processing in response to the input of program data and processing data on the internal data bus 202. In this case, depending on the level at the operation mode designating terminal 57, the operation of the single-chip microcomputer 1 is selected by the output from the internal ROM 3 or the output from the external memory 7. . Also,
From the reset terminal 58, a reset signal for initializing the CPU 5 and other blocks of the constituent blocks of the single-chip microcomputer 1 is input. From the external memory 7, processing data according to the address information supplied to the external memory 7 via the address bus interface terminal in the single-chip microcomputer 1 is output to the external data bus 203. In the external data bus 203, the external memory 7
The processed data output from the device and the data from the data bus interface terminal of the single-chip microcomputer 1 are transmitted.

Next, the operation of reading data stored in the internal ROM 3 in the conventional single-chip microcomputer 1 will be described.

First, as can be seen from the layout diagram of the read program shown in FIG. 8, the addressable area of the single-chip microcomputer 1 is 6 from 0 to FFFFH.
Assuming that the capacity of the internal ROM 3 is 4 Kbytes and 16 Kbytes, the unmapped address of the internal ROM 3 (5000 in FIG. 8) is stored in the external memory 7.
The read program of the internal ROM 3 is stored corresponding to the address starting from the address H). Further, the start address (5000H in FIG. 8) of this read program is set in the reset vector table that sets the program start address after reset.

The program for reading the data of the internal ROM 3 is extremely simple. First, after the level at the operation mode designating terminal 57 is changed to the operation level of the internal ROM 3, a read command for the internal ROM 3 is executed. , The read data is the external data bus 2
It is stored in an external RAM (not shown) via 03 or is read out through a predetermined output port.

Such a read program is stored in the external memory 7, and the reset terminal 5 is set as the Ex level for designating the operation mode designation terminal 57 in the external memory operation mode.
The reset signal for initialization described above is input from 8,
The operation is started. The setting of the Ex level can be realized, for example, by connecting a pull-down resistor to the operation mode designation terminal 57 when the Ex level is the LOW level.

The reading program is started to be executed from the head address of the reading program by setting the reset vector table stored in the external memory 7. Even when the level of the operation mode designation terminal 57 is changed from the Ex level to the operation mode level of the internal ROM 3 (hereinafter referred to as Int level) during execution of the program, the storage address of the program is outside the area of the internal ROM 3. Therefore, in the address determination circuit 2, the data from the external data bus 203, that is, the external memory 7
Since the output for selecting the program data stored in is input to the selector 4, the read program stored in the external memory 7 is continuously executed.

When an instruction to sequentially read the address data stored in the internal ROM 3 is executed during execution of the program, the read address is in the internal ROM area. ROM
A signal for selecting the output of the internal ROM 3 is output to the selector 4, and the data of the internal ROM 3 is transferred to the internal data bus 20.
2 to the external data bus 203. The operation procedure for reading data from the internal ROM 3 is shown in the flowchart of FIG.

That is, the data stored in the internal ROM 3 of the single-chip microcomputer 1 is operated by a third party by operating the level of the operation mode designating terminal 57 by the program stored in the external memory. , And can be easily read.

[0012]

In the conventional single-chip microcomputer described above, the internal level of the single-chip microcomputer is controlled by operating the level of the operation mode designating terminal by the program stored in the external memory. Since the data stored in the ROM can be easily read out, the data can be read out by a third party, and there is a drawback that the confidentiality of the software is lacking.

[0013]

A single-chip microcomputer according to a first aspect of the present invention has an internal ROM, and the internal ROM and a predetermined ROM are selected through a selection operation based on a logical value of a predetermined operation mode designating terminal. In a single-chip microcomputer that operates using either one of external memories connected via an interface terminal as one of data storage means, a logical value at the operation mode designating terminal is latched at the time when the reset state is released. It is configured to include a latch circuit that operates.

The microcomputer of the second invention has an internal ROM and an electrically rewritable memory,
A single chip operating either one of the internal ROM and an external memory connected through a predetermined interface terminal as one of the data storage means through a selection operation by a logical value of a predetermined operation mode designating terminal. In the microcomputer, when the logical value at the time of releasing the reset state at the operation mode designating terminal is the logical value for selecting the data storage means in the external memory, access to the electrically rewritable memory is permitted /
It is configured to include a first flag that is prohibited and a latch circuit that latches the logical value at the operation mode designating terminal at the time when the reset state is released.

The first flag may be composed of an electrically rewritable memory, a mask ROM, or metal wiring of a semiconductor manufacturing process. May be.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, the single-chip microcomputer 1 of the present embodiment corresponds to the external memory 7, an address determination circuit 2, an internal ROM 3, a selector 4, a CPU 5, a latch circuit 6, and It is configured with. It should be noted that the other components including the internal RAM, the timer circuit, and the like are not shown in FIG. 1 because they are not directly related to the present invention. The difference between the present invention and the above-described conventional example is that a latch circuit 6 is newly added to the conventional example, and other components are the same as those in the conventional example, and Since the operation is the same, the description thereof will be omitted.

In the latch circuit 6, in response to the data input from the operation mode designating terminal 51 to the D terminal,
The reset signal input from the reset terminal 52 to the T terminal is used as a trigger input, and the output signal from the Q terminal is input to the address determination circuit 2. The operation of this latch circuit 6 is
Since the level at the operation mode designation terminal 51 is maintained as it is at the time of reset release, the level of the reset signal serving as the trigger input changes from the reset level to the non-reset level at the operation mode designation terminal 51. Latch the level.

With this configuration, the output of the Q terminal of the latch circuit 6 does not change even if the level of the operation mode designating terminal 51 is changed after the reset is released.
Along with this, the operation of the address determination circuit 2 does not change. Therefore, when the operation is started in the external memory operation mode like the read program in the above-mentioned conventional example, the operation mode is set to the internal R during the execution of the program.
Cannot change to OM operation mode, internal ROM3
It becomes impossible to read the data stored in.
As described above, according to the present embodiment, by adding the latch circuit 6, the confidentiality of the data content of the internal ROM 3 can be maintained very easily.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing this embodiment. As shown in FIG. 2, the single-chip microcomputer 1 of this embodiment corresponds to the external memory 7, an address determination circuit 2, an internal ROM 3, selectors 4, 10 and 11, a CPU 5, a latch. Circuit 6
, Output port latches 8 and 9, a memory expansion flag 12, and an AND circuit 13. Also,
FIG. 3 is a diagram showing the arrangement of the internal ROM and the external memory in this embodiment.

This embodiment is a more practical circuit configuration example than the first embodiment described above, but in FIG.
0 and 11 and output ports 8 and 9, and when the external memory 7 is not used, the circuit is configured so that the interface terminal can be used as a port, and the memory expansion flag 12 is set. This is different from the case of the first embodiment in that it is provided with a structure that enables more detailed operation to the outside.

The operation of the address determination circuit 2 and the selectors 4, 10 and 11 depending on the combination of the operation mode designation terminal 53 and the memory expansion flag 12 will be described with reference to FIGS. 2 and 3. In FIG. 3, it is assumed that the address range is mapped to 64 Kbytes of 0 to FFFF and the internal ROM 3 is mapped to 16 Kbytes of 0 to 3FFF as in the conventional example.

After the reset is released, when the level of the operation mode designating terminal 53 is "0" which is the Ex level,
Via the signal input from the address determination circuit 2 to the selector 4, the selector 4 selects and outputs the data from the external data bus 203 regardless of the address information, and outputs the data to the internal data bus 202. To be done.
At that time, the output of the AND circuit 13 also becomes "0", which is the same as the Ex level, regardless of the level of the memory expansion flag 12, and the selectors 10 and 11 correspond to the output "0" of the AND circuit 13. Via the internal address
The bus 201 and the internal data bus 202 are connected to the corresponding interface terminals. Therefore, as shown in FIG. 3, the external memory 7 operates only regardless of the address value.

The level of the operation mode designation terminal 53 is "1".
When the output level of the memory expansion flag 12 is "0", in the selector 4 via the signal output from the address determination circuit 2 to the selector 4, if the address information is 0 to 3FFFH, the internal ROM 3 From the external memory 7 is selected and output if 4000H to FFFFH. In this case, since the output of the AND circuit 13 is "0", which is the same level as the Ex level, the internal address bus 201 and the internal data bus 202 are selected in the selectors 10 and 11, respectively. Therefore, as shown in FIG. 3, according to the address information, the internal ROM 3
And the external memory 7 can be accessed.

Next, the operation mode designation terminal 53 is "1".
Then, when the output level of the memory expansion flag 12 is also "1", if the address information is 0 to 3FFFH in the selector 4 via the signal output from the address determination circuit 2 to the selector 4, The data from the ROM 3 is selected, and if it is 4000H to FFFFH, the data from the external memory 7 is selected. In this case, the output of the AND circuit 13 is "1", which is the same level as the Int level. Selectors 10 and 1
At 1, the output port latches 8 and 9 are selected, respectively. Therefore, as shown in FIG. 3, not the interface signal to the external memory 7, but the data as the output port is output from the interface terminal. Therefore, in this operation mode, the external memory 7
However, the interface terminal can be used as a port output terminal through the operation within the range of the internal ROM 3.

Similar to the description in the first embodiment, the latch circuit 6 maintains the level of the operation mode designating terminal 53 at the time of reset release, so that the operation is started in the external memory operation mode. In this case, access to the internal ROM 3 is impossible, and thus confidentiality of the data in the internal ROM is maintained. On the other hand, when the operation is started in the internal ROM operation mode, it is possible to select whether to use the external memory 7 by rewriting the memory expansion flag 12 with a program. The advantage is that they can be used properly according to the application system.

Next, a third embodiment of the present invention will be described. FIG. 4 is a block diagram showing this embodiment. As shown in FIG. 4, this embodiment is based on the second
2 (see FIG. 2), the E ² PROM operation designation flag 1 defined as an electrically rewritable memory
4 and E ² PROM 15 are added.

The important point of this embodiment is that E ² PRO
The present invention is applied to the single-chip microcomputer 1 equipped with the M15. E ² PRO
M15 can be freely rewritten by software, and even after the power supply is lost
Since the memory contents are not lost, it is used for storing individual data for each application device. For example, storing a password for using the application device. Such individual data for each application device has high confidentiality, and it is necessary to improve confidentiality. The single-chip microcomputer that secures the security of the E ² PROM 15 is the present embodiment.

[0029] Hereinafter, with reference to FIGS. 4 and 5, E ² PROM operation designation flag 14 in the present embodiment, a combination operation by ^operation mode designation terminal 55 and the memory extension flag 12, an address decision circuit 2, a selector The operations of 4, 10, and 11 will be described. In FIG. 5, the address range is 0 to FFFF of 64 Kbytes, the internal ROM 3 is 0 to 3FFF of 16 Kbytes, and E ² PROM.
15 is mapped to 1K bytes of FC00 to FFFF.

The E ² PROM operation designation flag 14 is set to E ²
It is formed of the PROM 15 or mask type ROM, or metal wiring, etc., and is configured so that the stored contents will not be lost even if the power source is lost. Also, E ² PROM
When the data content can be changed by software as in 15, the non-write level (level at the factory shipping stage) is set so that the supply level to the address determination circuit 2 becomes "0" level. To do.

After the reset is released, when the level input from the operation mode designating terminal 55 is the Ex level "0", and the E ² PROM operation designating flag 14 is the "0" level, the addresses 0 to FBFF are stored. The address determination circuit 2 functions so that 63 Kbytes are accessed to the external memory 7 and 1 Kbytes of FCOO to FFFF are accessed to the internal E ² PROM 15. If the level input from the operation mode designating terminal 55 is the Ex level "0" and the E ² PROM operation designating flag 14 is the "1" level, the address determination circuit 2
All 64 Kbytes of addresses 0 to FFFF are designated to access the external memory 7 through the functional operation of. That is, by setting the level in the E ² PROM operation designation flag 14, when the external memory 7 is used, access to the internal E ² PROM 15 is permitted /
It is possible to perform a control action that is prohibited. Moreover, as described above, since the contents of the E ² PROM operation designation flag 14 are not lost even after the power is lost, if the setting level for the E ² PROM operation designation flag 14 is set to “1”. , Can be completely confidential. On the contrary, when it is not necessary to maintain the security of the E ² PROM 15 and the access from the external memory 7 is required, the E ² PROM operation designation flag 1
It can be easily dealt with by changing the level of 4.

The E ² PROM operation designation flag 14 is set to E ²
When the PROM 15 is rewritable by software, the E ² PROM operation designation flag 14 is set by the program stored in the internal ROM 3.
Level is set. However, in the initial state, it is accessible from the external memory 7 as described above. When using a mask ROM or metal wiring, it is necessary to build it at the manufacturing stage,
At the stage of ordering the single-chip microcomputer, it is clear whether or not access from the external memory 7 is necessary, so this designation is possible.

At the time of reset release, when the input level to the operation mode designation terminal 55 is the Int level "1", the E ² PROM operation designation flag 14 is set.
The access to the external memory 7 is changed by the level setting in the memory expansion flag 12 regardless of the designated level of, as in the case of the second embodiment. Further, as in the case of the first embodiment, in the latch circuit 6, the level of the operation mode designating terminal 55 at the time of reset release is maintained as it is,
When the operation is started in the external memory operation mode, the access to the internal ROM 3 becomes impossible, and when the level of the E ² PROM operation designation flag 14 is “1”, the access to the E ² PROM 15 becomes impossible. , The confidentiality of the data stored in the internal ROM 3 and the E ² PROM 15 is maintained. In contrast, if the operation is disclosed in internal ROM operation mode, E ² regardless of the level setting of the PROM operation designation flag 14, it is possible to access to the E ² PROM15, external memory 7 by the memory extension flag 12 Whether or not to use is selected, and there is an advantage that the memory can be used properly according to the application system.

[0034]

As described above, the present invention provides the internal R by providing the latch circuit for latching the level at the operation mode designating terminal at the time of reset release.
This has the effect of maintaining confidentiality regarding the data contents of the OM and the internal E ² PROM.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing an arrangement of an internal ROM and an external memory in the second embodiment.

FIG. 4 is a block diagram showing a third embodiment of the present invention.

FIG. 5 is a diagram showing an arrangement of an internal ROM and an external memory in the third embodiment.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a diagram showing a flowchart of an internal ROM reading procedure of a conventional example.

FIG. 8 is a diagram showing an arrangement of an internal ROM read program in a conventional example.

[Explanation of symbols]

1 Single Chip Microcomputer 2 Address Judgment Circuit 3 Internal ROM 4, 10, 11 Selector 5 CPU 6 Latch Circuit 7 External Memory 8, 9 Output Port Latch 12 Memory Expansion Flag 13 AND Circuit 14 E ² PROM Operation Designation Flag 15 E ² PROM

Claims (5)

[Claims] 1. An internal ROM having an internal ROM, wherein the internal RO is selected through a selection operation according to a logical value of a predetermined operation mode designating terminal.
In a single-chip microcomputer operating either M or an external memory connected through a predetermined interface terminal as one of data storage means, a reset state releases a logical value at the operation mode designation terminal. A single-chip microcomputer including a latch circuit that latches at a specified time. 2. An internal ROM is provided with a memory that is electrically rewritable, and is connected to the internal ROM through a predetermined interface terminal through a selection operation based on a logical value of a predetermined operation mode designating terminal. A single chip that operates either one of the external memories as one of the data storage means.
In the microcomputer, access to the electrically rewritable memory is permitted when the logical value at the time of releasing the reset state at the operation mode designating terminal is the logical value for selecting the external memory for the data storage unit. A single-chip microcomputer, comprising: a first flag for inhibiting; and a latch circuit for latching a logical value at the operation mode designating terminal at a time point when the reset state is released. 3. The first flag comprises an electrically rewritable memory.
The described single-chip microcomputer. 4. The single-chip microcomputer according to claim 2, wherein the first flag comprises a mask ROM. 5. The single-chip microcomputer according to claim 2, wherein the first flag is composed of metal wiring in a semiconductor manufacturing process.