JPH0687553B2 - Digital signal-Quality monitoring method for at least two transmission sections of a transmission section and apparatus for implementing this method - Google Patents

Abstract

A method for monitoring the quality of at least two cascaded transmission sections of a digital transmission link for transmission facilities corresponding to the synchronous digital hierarchy. For accumulating parity errors in successive transmission sections, error signalling bytes, in which parity errors are accumulated, are transmitted as special bytes in the section overhead of synchronous transport modules. A quality criterion for the transmission link monitored is obtained from a sequence of error signalling bytes. The method and the device can be advantageously used in transmission facilities of digital synchronous hierarchy. <IMAGE>

Description

Description: FIELD OF THE INVENTION The present invention relates to a method for quality monitoring of at least two cascade-connected transmission sections for a transmission device corresponding to a synchronous digital hierarchy, said transmission device comprising a synchronous transport. A valid signal is transmitted in the virtual container of the module, and the section overhead of the synchronous transport module has a parity byte and a special byte for special applications, where the valid signal is received at the end of the transmission section respectively. A parity byte is derived, this parity byte is compared with the received parity byte, and an error signal is formed according to a predetermined relationship with the comparison result of this comparison. Section quality monitoring method and this method

Prior Art The above method is based on DE-Z (Western German magazine) / NTZ Vol. 41 (1988)
It is already known from CCITT Recommendations G707-G709 by 10 parts, pages 570-574. In the known method, a byte-structured PCM signal is transmitted with a parity byte. The parity byte is used for determining the bit error rate during transmission. In the usual case, a parity is formed for the bits in a complete frame or a partial frame and this parity is then transmitted in a subsequent frame or partial frame.
The parity byte B1 is checked and monitored by each intermediate regenerator and re-formed. Thereby, the error can be limited to the regenerator section concerned with the error in the transmission section. On the other hand, the parity byte B2 is used for detecting bit errors in the transmission section between the two line ends. The parity byte B3 is provided in the path overhead of each virtual container and therefore cannot be used for quality monitoring of each part of the physical network.

A parity byte is newly formed at the beginning of the regenerator section, respectively, and another parity byte B2 is newly formed at the beginning of the transmission section, so that the regenerator section or the transmission section is individually monitored, whereby , The error in the transmission section can be limited to the reproduction section involved in the error,
Or, the error on the transmission path can be limited to the transmission section in which the error is involved.

Furthermore, DE-Z (West German magazine) telcom report, pages 109-114,
It is known from Spezial, Multiplex-und Leitungseinrichtungen (special multiplex and line devices) to provide a digital transmission system with a device for monitoring during operation. In that case, the intermediary regenerator is a continuous digital sum
tal sum) to monitor the violation of the code rule. Thereby, apart from the burst error, the bit error frequency can be known at the station. The so-called error rate is transmitted in coded form to the position measuring device. Therefore, in the position measuring device, the bit error frequency is detected by each intermediate generator. In this way, the comparison of the bit error frequencies measured at the monitoring terminal makes it possible to know the transmission quality of the individual regenerator areas, which makes it possible to individually monitor the transmission sections.

For quality monitoring, according to CCITT Recommendation G.707… 709 above,
In the Section Overhead SOH, parity bytes B1 and B2 may be used, ie one for each synchronized transport module STM-N.
One parity byte B1 and also one parity byte B in each synchronized transport module STM-1
Two can be used. Parity byte B1 enables monitoring of individual regeneration sections, and parity byte B2 enables monitoring of digital signal line sections. Continuous or penetrating monitoring across multiple digital signal line sections is not done by the two parity bytes mentioned above according to the CCITT recommendation, because the section overhead SOH is between digital signal line sections. This is because compensation of the frequency difference at the time of transition cannot be performed. Therefore, it is not possible to detect a fixed combination of parity bytes in the section overhead to useful information in the virtual container from the input side to the output side of the digital signal line.

OBJECT OF THE INVENTION It is an object or object of the present invention that fixed binding of parity bytes in section overhead to valid information in a virtual container is not possible between the input side and the output side of a transmission section. It is an object of the present invention to provide a method for accumulating errors in successive transmission sections in a transmission apparatus having successive transmission sections. Furthermore, it provides an advantageous device for carrying out such a method.

According to the invention, in a method of the type mentioned at the outset, the problem is solved by the measures specified in the characterizing part of claim 1. In that case, each transmission section of the transmission section may be a line section or a line.

The advantage obtained by the means of the present invention is that the transmission quality of cascaded circuits of a plurality of transmission sections can be detected by means of the accumulation of parity errors of successive transmission sections using means which are not provided per se. It is in.

Advantageous embodiments and devices of the invention are described in the dependent claims.

EXAMPLES Next, the present invention will be described with reference to the illustrated examples.

FIG. 1 shows a device for transmitting a digital valid signal from the line terminal device 1 to the line terminal device 6 via a transmission section d.

In addition to the multiplexers 11, 13, 15 and the demultiplexers 12, 14, 16 the line terminal devices 1-6 additionally have monitoring circuits 21-26 for bit error detection and identification. The relay station 7 has a regenerator 17 and a monitoring circuit 27 for bit error identification. The monitoring circuits 22 to 27 may be connected to the monitoring circuit 21 of the line terminal device 1 via a return (feedback) channel (not shown). The feedback channel is then a component of the operating monitoring device of the transmission device.

The transmission section d consists of digital signal line sections d1 to d3, which will be simply referred to as line sections.
A parity byte is transmitted in addition to the valid signal for monitoring these three consecutive transmission sections. The parity bytes B2 are derived from the valid signal at the beginning of each of the line sections d1 to d3 and inserted into the digital valid signal.

At the end of the line sections d1 to d3, a parity byte is derived from each received valid signal. These parity bytes are compared with the received parity bytes. Therefore, a comparison is made between the received parity byte and the locally formed parity byte. Here, an error message (signal) is formed according to a predetermined relationship with the comparison result according to the dependency given in advance to the comparison result, and the central monitoring circuit is provided via the reverse communication path.
Sent to 21.

Here, the following error signal, that is, the error signal from which the error notification byte is derived from the error signal, and the error notification byte concerned should be distinguished, and are specified in the scope of claims. As described above, the parity byte included in the section overhead and derived from the reception valid signal at the end of the transmission section is generated according to a predetermined relationship between the result of the comparison with the received parity byte. Error signal and an error notification byte specifically derived from the error signal (that is, a new error notification byte is generated when the new error notification byte is generated as defined in claims 3 to 4). When deriving bytes, the number of parity errors resulting from the error signal is added to the number of parity errors reported by the received error notification byte. , Or each time the error notification byte is derived, the locally formed parity error pattern and the received parity error pattern are combined bit by bit through the exclusive OR element. It is to be generated), and it is the relevant error message (signal) that is transmitted to the central monitoring circuit 21 via the reverse (return, return) communication path.

The transmission device belongs to the so-called synchronous digital hierarchy, as is known from CCITT Recommendations G707 to G709. Therefore, the digital transmission section has one synchronous multiplexer 1, 3, 5 at the beginning of the line sections d1 to d3, respectively.
One synchronous digital plexer at each end of ~ d3, 2, 4 and 6
And a synchronous regenerator, for example regenerator 7, in the path of the line.

The bit error identification detection in the regenerator section is carried out by inserting a parity byte B1, which is newly calculated in each regenerator, for example regenerator 7, and inserted in the data stream.

Parity errors that occur in some cases are counted in the monitoring circuits 22 to 26, 27, compared with limit values, and converted into alarm notifications as the case may be.

In the transmission device under consideration, monitoring of individual regenerator sections or line sections takes place in the absence of special measures as explained below, but monitoring over a plurality of line sections cannot take place, There is no method or possibility that can guarantee the frequency difference at the time of transition between line sections, as described below for section overhead SOH.
That is, in a digital signal transmission device using a byte-structured PCM signal of synchronous digital hierarchy (SDH), a frequency difference (differential difference) is generated at the transition transition from one digital signal line section to the next digital signal line section. There is no means for balanced compensation for the difference between frequencies. The frequency difference concerned is rather taken into account in the following way: the pointer in each case indicates (designates) where the first byte of the valid signal comes (is located). Are being considered. In this way, the valid signal in question can be located (positioned). However, section overhead (sectoin overhe
ad) It is not possible to associate (allocate) the parity bytes contained in the SOH with one predetermined valid information over a plurality of digital signal line sections. Therefore, it is not possible to form a fixed combination of the parity bytes in (to) the valid information in the virtual container in the section overhead.

The method described below can be dispensed with without such a combination, the statistical properties of the error over a relatively short period being sufficient for quality monitoring of one transmission section, and the above frequency difference being Based on the recognition that it does not have an adverse effect.

In the method of the first method, at the end of the line section d1, the number of parity errors ZPF (1) for each synchronous transport module STM-1 is calculated from the parity byte B2 and sent to the input side of the line section d2. , There the section overhead SOH of the corresponding standard transport module STM-1 is transmitted. The number of parity errors is calculated at the end of the line section d2 and the sum of the numbers ZPF (1) and ZPF (2) is processed for subsequent transmission.

On the output side of the digital signal line, from the number n of line sections consecutive in each received frame,
Accumulated parity error Is obtained.

The quality of the digital signal line is calculated by using the short-time statistical characteristics over the time series of the accumulated parity error numbers ZPFa (t) of m, that is, Is determined using.

On the basis of the frequency difference between the line sections d1 to d3 (when occurring relatively rarely), during the transition from one line section j to the next line section j + 1, only that location (station ) Accumulated parity errors up to Are lost or transmitted twice.

The standard transport module ST determines the transmission quality of digital signal lines even in the case of prescribed evaluation over a short period.
Since it is based on the statistical properties of M-1 over a relatively large number of frames, even in such a case, the evaluation result is practically unaffected.

For example, it is set when synchronizing digital hierarchy
100 based on the duration of one frame of 125 μsec
If the number of frames is evaluated, a 12.5 msec time interval occurs. The predetermined evaluation period is in particular 10 to 15 msec.

According to the technical idea underlying the second means of the method according to the invention, the parity signal is generated via an all-digital signal line. In that case, two parity errors here that occur on the same parity-track but on different line sections are not identified. On the output side of the line section d1, for each synchronous transport module STM-1, from the parity byte B2 to the parity error-pattern PFM (1)
Is required. Such a parity error pattern is obtained in the following way: the bit clock to be detected for the formal formation of the parity word is first decomposed bit by bit into sub-blocks, followed by each The parity bit is formed for the partial bit block. The parity bits thus determined give rise to a parity word. This method is known under the concept of bit-interleave-parity (BIT).

The parity error pattern PFM (1) is applied to the corresponding synchronous transport module STM- at the input side of the line section d2.
It is inserted in the section overhead of 1 and transmitted. A parity error-pattern PFM (2) is detected at the end of the line section d2 and subsequently combined with the parity error pattern (1) bit by bit via the exclusive OR coupling element to form the parity error pattern (1, 2) is formed.

FIG. 2 shows such a pattern in which the errors which have been identified and detected in the individual tracks are marked with a 1 respectively.

The above combination performs the following:

a) The sum of "1" s in the parity error pattern PFM (1,2) indicates the number of identified parity errors that have occurred up to the output of the line section d2.

b) Two individual parity errors occurring in the same track but in different line sections are treated like double errors, ie they are not affected in the final evaluation result.

Parity error-Pattern PFM (1,2) is line section d3
Is transmitted through. In the line terminal device 6, the parity error-pattern PFM (3) is obtained, and subsequently, it is combined with the parity error pattern (1,2) bit by bit through the exclusive OR coupling element to generate the parity error pattern (1,2). , 3) is formed. Therefore, the digital signal line d
A parity error pattern for the all digital signal line appears on the output side of.

The same holds for the variant of the first method with respect to the influence of the frequency difference between adjacent digital signal line sections.

The block connection diagram of FIG. 3 shows a relay station or an intermediate relay device including a device for adding the number of parity errors.

In the first variant of the method, the accumulation of parity errors is
It is carried out using the device for addition shown in FIG. 3 above. The relay station or the intermediate relay device arrangement shown in FIG. 3 has the bit error number ZPF of the preceding i-th line section in addition to the relay station 2a, 2b in which the relay station is arranged.
It has a device 81 for the calculation of (i), an adder 82 and a device 83. From the relay station 2a, the parity byte received by the relay station 2a is supplied via the connection pipe 81, and the device 81 is supplied with the parity byte calculated from the valid signal via the connection path b1. In the device 81 the bytes are compared with each other. The number of parity errors ZPF (i) of the i-th line section obtained at that time is added by the adder 82 to the number ZPF (1, ... i-1) arriving via the connection path C. That is, it is added to the sum of the bit error numbers from the line section preceding the last line section. The sum thus formed is supplied to the device 83 for insertion into the bit stream emitted by the relay station 2b. In that case, a special (dedicated) byte of the section overhead of the synchronous transport module is used for the transmission of the sum,
The special byte is special (dedicated) according to the CCITT recommendation above.
It's for a purpose.

At the end of the digital signal line, the accumulated parity error at the output of the adder 82 appears and the device 83 is omitted.

In the means of the second method, the accumulation of parity errors is preferably carried out by means of a device such as that of the relay station or intermediate relay device shown in FIG.

The arrangement of relay stations or intermediate relay devices shown in FIG. 4 is, in addition to the interconnected relay stations 2c and 2d, additionally a parity error-pattern forming device 91 and a relay station 2d. A device 92 for the insertion of bit error patterns into the coded bit stream. Here, as explained using FIG. 2, the parity error pattern PFM inserted in the section overhead of the corresponding synchronous transport module STM-1 at the input side of the line section d2.
(1) (corresponding to the first bit pattern) and the parity error pattern PFM (2) (corresponding to the second bit pattern) extracted (detected) at the end of the line section d2,
After taking out the parity error pattern, the parity bit pattern is combined through an exclusive OR coupling element to generate a third bit pattern PFM (3), and the generated third bit pattern has the following meanings as described above. The action (operation process) is achieved.

a) The sum of "1" s in the parity error pattern PFM (1,2) indicates the number of identified parity errors that have occurred up to the output of the line section d2.

b) Two separate parity errors that occur in the same track but in different line sections are treated like double errors, ie they are not affected in the final evaluation result.

Parity error-Pattern PFM (1,2) is line section d3
Is transmitted through. In the line terminal device 6, the parity error-pattern PFM (3) is obtained, and subsequently, it is combined with the parity error pattern (1,2) bit by bit through the exclusive OR coupling element to generate the parity error pattern (1,2). , 3) is formed. Therefore, the digital signal line d
A parity error pattern for the all digital signal line appears on the output side of.

This bit error pattern is generated by using the device 92
It is inserted in the bit stream sent from 2d. On the output side of the digital signal line appears as a cumulative parity error pattern on the output side of the device 91 and the device 92 is omitted.

A particularly simple implementation of the accumulation of the number of bit errors, implemented in the method according to the invention, is possible as follows:
The parity error number PFZa (i) or the parity error pattern (1,2, ... j) is on the same unique connection line as defined in claim 5, that is, the same as the effective signal (digital signal). It is transmitted on the line from the relevant multiplexer of one relay station to the relevant multiplexer of the other relay station.

For the time being, the relay station or / or intermediate relay device (relay other than the end) defined in the claims (intermediate)
link) means the following. That is, the digital relay transmission line is composed of a transmission line and a relay transmission device (a terminal relay device and an intermediate relay device). The terminal relay device is necessary as a transmission line interface, and a transmission unit and a reception unit are installed facing each other for each relay transmission line. Here, the intermediate relay device has a function of identifying and reproducing a received signal distorted on the route, retiming the signal, and then retransmitting the signal.

In FIG. 1, reference numerals 1 and 6 represent line terminal devices corresponding to the above-mentioned terminal repeater, and are represented by 2 in FIG. 1, FIG. 3 and FIG.
Reference numerals 5, 2a, 2b, 2c and 2d represent relay stations corresponding to the above intermediate relay devices.

Advantageous Effects of the Invention According to the present invention, it is possible to detect the transmission quality of the cascade connection circuit of a plurality of transmission sections by accumulating the parity errors of the transmission sections that are successively succeeding by means of means provided for that purpose. The effect is played.

[Brief description of drawings]

Figure 1 shows a PC with two digital signal line sections
FIG. 2 is a conceptual diagram of an M transmission device, FIG. 2 is an explanatory diagram showing how two bit error patterns are combined with a third bit error pattern, and FIG. 3 is a relay station or intermediate relay having a device for adding the number of parity errors. FIG. 4 is a conceptual diagram of a device arrangement structure, and FIG. 4 is a conceptual diagram of an arrangement structure of a relay station or an intermediate relay device having a device for combining bit error patterns. d ... Transmission section, d1 to d3 ... Line section, B1, B2 ... Parity byte, 1,6 ... Line terminal device, 2-5, 2a, 2b; 2c, 2d, 7
... Relay station or intermediate relay device (regenerator)

Claims (6)

[Claims] 1. A method for quality monitoring of at least two transmission sections connected in cascade for a transmission device corresponding to a synchronous digital hierarchy, in which a valid signal is transmitted in a virtual container of a synchronous transport module. , The section overhead of the synchronous transport module has a parity byte and a special purpose byte, where the parity byte is derived from the valid signal respectively received at the end of the transmission section, which parity byte At least one relay station (or intermediate relay device) (2, 3; 4) in a method of comparing with a received parity byte and forming an error signal according to a predetermined relationship with the comparison result of this comparison. , 5; 2a, 2b; 2c, 2d), the error notification byte is derived from the above error signal, It is transmitted as one of the special bytes via the following transmission sections (d2, d3), and
A new error message byte is derived from the error message byte received at the end of at least one subsequent section (d2, d3) and the locally formed error signal, and the new error message byte is deduced by the evaluation of the sequence of error message bytes. A quality monitoring method characterized in that a quality metric is formed for the monitoring transmission section (d). 2. In the evaluation of a series of error reporting bytes described above, even if a change in the evaluation result is caused by the loss of one special byte or the reception of the special byte twice, the degree of change in the evaluation result is within a predetermined limit. 2. The method according to claim 1, wherein said series of error notification bytes are evaluated with a relatively large number of evaluations (times) within a predetermined evaluation period so as to be suppressed. 3. The error signal formed according to a predetermined relationship between a parity byte derived from a valid signal received at the end of the transmission section and a comparison result of the received parity byte. At the time of generation, the number of parity errors is calculated, and at least 1
A new error formed from the error signaling byte and a locally formed error signal received at the end of at least one subsequent transmission section derived from the error signal in question at one intermediate relay device. Method according to claim 1 or 2, wherein the number of parity errors resulting from the error signal is added to the number of parity errors reported by the received error message byte in generating the message byte. 4. A parity error pattern (PFM (2)) is formed for each transport module when forming the error signal, and a locally formed parity error pattern (PFM (2)) is derived each time the error notification byte is derived. Method according to claim 1 or 2, wherein the PFM (2)) and the received parity error pattern (PFM (1)) are combined bit by bit via an exclusive OR element (91). 5. The error reporting byte is sent from the multiplexer of one repeater to the multiplexer of the other (next) repeater.
5. A method according to any one of claims 1 to 4, wherein the method is transmitted on the same line as the valid signal in the opposite direction. 6. A line terminal device (1, 6) comprises a synchronous multiplexer (11) or demultiplexer (16) and a monitoring circuit (2).
1,26) and the intermediate relay device (2,3,4,5; 2a, 2b; 2c, 2d) has a synchronous regenerator and a monitoring circuit (22,23; 24,25) and further relays In at least one of the stations, a device for deriving a comparison signal from the received valid signal, a device for comparing the received parity byte with a locally generated comparison signal, and deriving an error signaling signal. Equipment (81,82,9
1) An apparatus for carrying out the method according to any one of claims 1 to 5, comprising: