JPH0686066A - Picture reader - Google Patents

Abstract

PURPOSE:To make a circuit scale to be remarkably small by using RAM assigned with the address space of CPU as a delay buffer. CONSTITUTION:Reading data from red/blue CCD 1 and 2 is A/D converted in order of blue and red by an A/D converter 8 and latched in the latch circuit 11 of a color separation binarization circuit 9, and blue data is written into delay buffer part of RAM 10 assigned to the address space of CPU. Red data is latched in a latch circuit 12 by a picture element clock shifted by a half cycle. Then, blue data of preceding line is read just before blue data is written into the buffer part to be latched in a latch circuit 13, to form spatial-corrected blue/red data. Blue/red data is stored in the binarization data part of RAM 10 and read by a latch circuit 14 so as to output black/read data by the reading control of the circuit 14. With the constitution of making RAM to be the delay buffer and one for reading binarization color data, the circuit scale is made remarkably small and the device is miniaturized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color image reading device, and more particularly to a color image reading device capable of realizing spatial correction and color separation with a small scale circuit.

[0002]

2. Description of the Related Art First, the principle of color image reading will be described with reference to an example of color recognition (color separation) of two colors, black and red. 4 and 5 are diagrams for explaining the principle of color recognition. The white-colored light emitted from the fluorescent lamp of FIG. 4A is reflected on the screen surface and is condensed on the CCD through the mirror and the lens. The CCD outputs light as the intensity of an electric signal based on the intensity (brightness) of this light. When the color shown in FIG. 4 (b) is written on the screen surface, the CCD output without the filter is as shown in FIG. 4 (c). In FIG. 4 (c), the highest level is the white level, the lowest level is the black level, and an appropriate level between them is the threshold level Th, for example, the threshold Th. The part is recognized as white and the part where the color is written is recognized as black. Here, as shown in FIG. 5A, the sum of the output of the CCD through the red pass filter and the output through the blue pass filter is almost the same as the output without the filter. On the other hand,
Since the value obtained by subtracting the output of the blue pass filter from the output of the red pass filter is as shown in FIG. 5B, red and colors other than red (including black) can be separated by the following algorithm.

When red CCD + blue CCD ≧ Th1,
"White" red CCD + blue CCD <Th1, and red CCD-blue CCD
When> Th2, “red” red CCD + blue CCD <Th1, and red CCD−blue CCD
When ≦ Th2, “black” In addition, red erase copy (copy red as white)
As shown in (c), when the red CCD output is larger than Th3, it may be recognized as "white", and when it is smaller than Th3, it may be recognized as "black".

FIG. 3 shows a conventional color separation / binarization circuit for realizing the color separation / binarization. In FIG. 3, an adder and a subtracter are used for the red and black color separations, and a digital comparator is provided for each of them, and density threshold data is given to each of the comparators. Output a in FIG. 3 is a binarized black signal (color signal other than red including black), output b is a red signal, and output c is a signal in the red erase mode.

When CCDs arranged in three lines are used, a delay buffer such as a shift register is provided in addition to the circuit shown in FIG. 3 to perform space correction in the sub-scanning direction.
After correcting the data on the same line, the processing by the above circuit is performed. This is because if a plurality of CCDs are not on the same line in the sub-scanning direction, the colors belonging to the same line are read at different timings, so it is necessary to delay the color signals read earlier to match the signals read later. Because there is.

[0006]

As described above, the prior art requires an adder, a subtractor, a comparator, etc. for color separation binarization, and a shift register, etc. for spatial correction. However, there is a problem in that the circuit scale becomes large because the delay buffer is required. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art and to provide an image reading apparatus that can realize spatial correction and color separation with a small-scale circuit.

[0007]

Means for writing data for space correction in the sub-scanning direction into a RAM allocated to the address space of the CPU, and the above data for RA.
Means for reading from M, writing means for digitizing CCD output data of a plurality of colors to obtain color separation and binary color data, and means for writing the separated binary color data from the RAM. It was equipped with a reading means.

[0008]

The data for correcting the space in the sub-scanning direction is C
The RAM can be used as a delay buffer because it has means for writing to the RAM assigned to the address space of the PU and means for reading the data from the RAM. Further, since means for writing digitized CCD output data of a plurality of colors to the color separation and binarized color data to the RAM and means for reading the separated binarized color data from the RAM are provided. Color separation and binarization can be handled programmatically.

[0009]

Embodiments of the color image reading apparatus of the present invention will be described in detail below with reference to FIGS. Incidentally, FIG. 1 (a)
1 is a circuit block diagram of a color image reading apparatus embodying the present invention, FIG. 1B is a circuit diagram showing details of the color separation / binarization circuit 9 shown in FIG. 1A, and FIG. 3 is a timing chart related to the color separation / binarization circuit shown in FIG. N-1, N, and N + 1 in FIG. 2 mean three consecutive pixel numbers.

First, the data for spatial correction is CP
RAM allocated to the U address space (hereinafter, simply R
The space correction of the red CCD and the blue CCD will be described as one line from the means for writing the data into the RAM and the means for reading the data from the RAM.

The video data photoelectrically converted by the CCDs 1 and 2 of each color are amplified by the video amplifiers 3 and 4, and are zero-clamped by the clamp circuits 5 and 6, and are blue by the sampling circuit 7 and the A / D converter 8. The data is A / D converted into digital data in the order of red.

The A / D-converted blue CCD data is input to the color separation / binarization circuit 9, where it is latched by a latch 11 in synchronization with a clock (pixel clock) and L1DAT.
A _5-0 is written in the delay buffer section of the RAM 10 at the timing of / BWE. The RAM 10 is assigned to the CPU address space. At this time, as the store address of the delay buffer unit, the one incremented by the pixel clock is used, and data is sequentially written from 0 pixel to n pixels.

Similarly, the A / D-converted red CCD data is latched in the latch 12 by shifting the phase of the pixel clock by a half cycle. Here, immediately before the blue CCD data is written in the delay buffer section, the blue CCD data of the previous line is read as BiD _5-0 and latched in the latch 13 at the timing of / BOE0. OPADR _11-0 is generated from the blue data of the previous line and the red data of the current line.

The OPADR _11-0 is spatially corrected blue data and red data. OPADR _11-0 is stored in another address space of the RAM used as a delay buffer for spatial correction as described above. This stored data is processed according to a program that implements the color separation algorithm, separated into binarized black data, red data, and white data, and stored in another address space of the RAM. Then, as shown in FIGS. 1B and 2, the stored binary data is read as BiD _5-0 to the latch 14 at the timing of / BOE1, and 2 out of 6 bits are generated by the Pixel1 and Pixel0 signals. Bits are selected and output as black data and red data (when both black data and red data are 0, white data is output).

The reading of the delay data from the RAM and the reading of the binarized data are performed in parallel for speeding up as shown in FIG. 3BiDn. That is, as the RAM address BADR _0-12 , the delay data storage address S
TADR _0-11 and binarized data storage address OPADR
_0-11 are output alternately, the delay data is read to the latch 13 at the timing of / BOE0, and the binarized data is read to the latch 14 at the timing of / BOE1. The binarized data is obtained by color-separating the space-corrected data stored in the RAM one or more lines ago and binarizing it. The color image reading device in which a plurality of CCDs are arranged in a plurality of lines has been described above. However, when a one-line color CCD or a CCD arranged in the same line is used, spatial correction is not necessary, so that a delay buffer is also unnecessary. In that case, the latch 11 becomes unnecessary.

[0016]

As is apparent from the above description, according to the present invention, the RAM allocated to the address space of the CPU can be used as the delay buffer, and the color separation and the binarization can be processed by the program. The scale of the circuit is much smaller than before. Therefore, it has a great effect on downsizing and cost reduction of the device.

[Brief description of drawings]

1A and 1B are a block diagram showing an embodiment of the present invention and a circuit diagram showing details of a color separation / binarization circuit of FIG. 1A.

FIG. 2 is a timing chart relating to the color separation / binarization circuit shown in FIG.

FIG. 3 is a block diagram showing a conventional example of a color separation / binarization circuit.

4A, 4B and 4C are diagrams for explaining the principle of color separation.

5A, 5B and 5C are diagrams for explaining the principle of color separation.

[Explanation of symbols]

1 ... Red CCD, 2 ... Blue CCD, 3, 4 ... Video amplifier,
5, 6 ... Clamp circuit, 7 ... Sampling circuit, 8 ... A
/ D converter, 9 ... Color separation / binarization circuit, 10 ... RA
M, 11, 12, 13, 14 ... Latch, 15 ... Selector.

Claims (2)

[Claims] 1. A color image reading apparatus having a plurality of light reading means for reading a color image, wherein a CPU outputs digitized CCD output data of a plurality of colors for obtaining color separation and binarized color data. An image reading apparatus comprising: a unit for writing to a RAM allocated to the address space and a unit for reading the separated binarized color data from the RAM. 2. The image reading apparatus further comprises means for writing data for spatial correction in the sub-scanning direction into a RAM allocated to the address space of the CPU, and means for reading the data from the RAM. The image reading apparatus according to claim 1, wherein: