JPH0685851A - Out of synchronism reduction device between repeaters - Google Patents

Abstract

PURPOSE:To reduce the frequency of occurrence of out of synchronism between a sender side repeater and a receiver side repeater by controlling data quantity stored respectively in an input side buffer and an output side buffer to be constant. CONSTITUTION:A sender side repeater 2 has an input side buffer 22 storing a plain text data and an output side buffer 24 storing ciphered data. The data block read from the buffer 22 is stored in a buffer 24 while being ciphering processing sequentially. The quantity of plain text data and ciphered data stored in the buffers 22, 24 in the transmission initial state is controlled to be a prescribed quantity respectively. Furthermore, a receiver side repeater 3 has an input buffer 32 storing the ciphered data and the output side buffer 34 storing the plain text data and applies decoding processing sequentially to the data block read from the buffer 32 and stores the result to a buffer 34. Idle areas able to store data to the buffers 32, 34 in the reception initial state is controlled respectively to be a prescribed quantity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission side relay device for performing encryption processing for each data block, in which clock systems are different between the transmission side and the reception side in a half-duplex communication system.
The present invention relates to a device for reducing synchronization deviation with a relay device on the receiving side that performs a decoding process for each data block.

[0002]

2. Description of the Related Art FIG. 3 is a conceptual diagram of a synchronization deviation absorbing system disclosed in Japanese Patent Laid-Open No. 61-60036. In the figure, A is a data transmission system, B is a data reception system,
ES is a buffer memory, AD is an address of the buffer memory ES, and DATA is data. Further, DET is a detection circuit that detects that the data transmitted from the data transmission system A is valid data by an interface signal, and RSET receives the output signal of the detection circuit DET, so that the data write address value of the buffer memory ES is changed. The reset circuit resets the read address to "0" or "1F".

The operation of FIG. 3 will be described. First, the detection circuit DE
T is the interface signal (eg CCITT, V2
4 system, 100 series CD signal, etc.) is newly detected, the reset circuit RSET resets the first address value of writing to “00”. In the data transmission system A, the address value of ES is “00”, “01”,
... The data is sequentially written from the one with the smallest address value such as "0n", and when the write address value reaches "1F" (half of the maximum address value of ES), the data receiving system B uses the data in the ES with the clock β. The address value "0"
Reading is sequentially started from 0 "in the direction in which the address value increases. In this way, writing and reading of valid data are always started with an address difference of" 1F "(half of the memory capacity of ES), and therefore, once. Data length to send and buffer memory E
By considering the capacity of S, it is possible to prevent the occurrence of a state in which the effective data is lost or the effective data is waiting to be transmitted.

[0004]

However, in the above-described synchronization deviation absorbing method, it is difficult to predetermine the data length to be sent at one time, such as image data, or data is divided into many times. For security information that is not desirable to send, there is a state of missing valid data or waiting for data to be sent (that is, synchronization loss).
Still occurred.

In a half-duplex communication system composed of a data transmission system, a transmission side relay device, a reception side relay device, and a data reception system, in particular, the transmission side transmits and receives data encrypted in data block units. In a system that decrypts received data on the side, between the data transmission system and the transmission side relay device and between the reception side relay device and the reception system, a state of simply missing valid data or waiting for transmission of valid data occurs. On the other hand, if one bit of the ciphertext is dropped or added between the transmitting-side relay device and the receiving-side relay device while using the basic mode of block cipher, all ciphertexts after that bit are encrypted. There was a problem that the synchronization error was transmitted to the sentence and it became impossible to perform plain culture. In this case, in order to resynchronize, it is necessary to retransmit from the first data according to the encryption communication protocol between the data transmission system and the data reception system, which is a security problem.

As an example of the data encryption method, "Data Encryption Standard" (DES, Data Encryption) promulgated in 1977 by the National Bureau of Standards (NBS) of the US Department of Commerce.
onStandard). The details of this DES algorithm are published in the Federal Information Processing Standard "FIPS 77", and also in Japanese "Modern Cryptography" (3rd
Chapter, The Institute of Electronics, Information and Communication Engineers, September 1986, first edition). In the DES, encryption / decryption is performed in units of 64-bit data blocks. The encryption algorithm is basically transposed and substituting, and 64-bit plaintext (ciphertext) is input, and a 56-bit key is input. It is a block cipher that outputs 64-bit ciphertext (plaintext) based on control. Therefore, if the 64-bit ciphertext is lost by 1 bit to 63 bits or 1 bit is added to 65 bits between the two relay devices on the transmission side and the reception side, the error bits after The synchronization error spreads to all the data blocks, and the ciphertext thereafter cannot be decrypted even if decrypted.

In a system in which data is encrypted and decrypted in units of data blocks between relay devices in this manner, data loss or data transmission waiting due to synchronization deviation between the transmission side relay device and the reception side relay device is called. Although it is necessary to lower the frequency of occurrence of the state from the frequency of occurrence of the same state between the transmission system and the transmission side relay device and between the reception side relay device and the reception system, no measures have been taken. There was a problem that not.

The present invention has been made to solve the above problems, and in a system for performing encryption and decryption in units of data blocks between relay devices, synchronization between a relay device on the transmitting side and a relay device on the receiving side is performed. It is an object of the present invention to provide a synchronization deviation reducing device between relay devices, which can make the deviation occurrence frequency lower than the occurrence frequency of the synchronization deviation between the transmission system and the transmission side relay device and between the reception side relay device and the reception system.

[0009]

In a synchronization deviation reducing device between relay devices according to the invention of claim 1, a clock system is different between a transmitting side and a receiving side, and a transmitting side which performs an encryption process for each data block. In a half-duplex communication system including a relay device and a reception-side relay device that performs a decryption process for each data block, the transmission-side relay device includes an input-side buffer that stores plaintext data and an output that stores encrypted data. Means for sequentially encrypting data blocks read from the input side buffer and storing the data blocks in the output side buffer, and plaintext to be stored in the input side buffer and the output side buffer in the initial transmission state. Means for controlling the quantity of data and encrypted data to a fixed number, respectively, and the receiving-side relay device includes an input-side buffer for storing encrypted data, and An output side buffer for storing culture data, means for sequentially decoding a data block read from the input side buffer and storing it in the output side buffer, and the input side buffer and the output side in an initial reception state And a means for controlling the number of empty spaces in which data can be stored in the buffer to a fixed number.

According to a second aspect of the present invention, there is provided a synchronization deviation reducing device between relay devices, wherein the transmission side relay device according to the first aspect of the invention accumulates in the input side buffer and the output side buffer in a transmission initial state. Set the quantity of plaintext data and encrypted data to 50% and 10% of the buffer capacity, respectively.
The receiving-side relay device controls the number of empty spaces in the input-side buffer and the output-side buffer that can store data to 100% and 50% of the buffer capacity, respectively. It includes means.

[0011]

According to the first aspect of the present invention, the clock system is different between the transmitting side and the receiving side, and the transmitting side relay device for performing the encryption process for each data block and the receiving side for performing the decryption process for each data block. In a half-duplex communication system including a side relay device, the transmission side relay device has an input side buffer for storing plaintext data and an output side buffer for storing encrypted data, and is read from the input side buffer. Data blocks are sequentially encrypted and stored in the output side buffer, and the numbers of plaintext data and encrypted data stored in the input side buffer and the output side buffer in the initial state of transmission are controlled to be constant numbers. The reception-side relay device has an input-side buffer for storing encrypted data and an output-side buffer for storing plaintext data, and sequentially decrypts data blocks read from the input-side buffer to output the data blocks. The number of empty spaces that can be stored in the side buffer and can store data in the input side buffer and the output side buffer in the initial reception state is controlled to be constant numbers.

According to a second aspect of the present invention, the plaintext data and the encrypted data stored in the input side buffer and the output side buffer in the transmission initial state by the transmission side relay device in the invention according to the first aspect are stored. The number of buffers is controlled to 50% and 100% of the buffer capacity, respectively, and the receiving side relay device stores the number of empty spaces in the input side buffer and the output side buffer in the initial state of reception to 100% of the buffer capacity, respectively. % And 50%
To control.

[0013]

1 is a block diagram of a synchronization deviation reducing device between relay devices according to the present invention. In the figure, 1 is a data transmission system, 2 is a transmission side relay device, and an input side interface 21, an input side buffer 22 and a CPU are internally provided.
A (microprocessor) 23, an output buffer 24, and an output interface 25 are included. A receiving-side relay device 3 includes an input-side interface 31, an input-side buffer 32, a CPU 33, an output-side buffer 34, and an output-side interface 35 inside. 4 is a data receiving system. Between the data transmission system 1 and the transmission side relay device 2,
The transmission-side relay device 2 and the reception-side relay device 3, and the reception-side relay device 3 and the data reception system 4 are connected by transmission lines 51, 52, and 53, which are, for example, a public communication network and are connected to each other. A half-duplex communication system that transmits and receives data using different clocks a to f is configured.

Although the transmission side relay device 2 and the reception side relay device 3 in FIG. 1 have the same hardware configuration, the contents of data processing executed by the CPU and the input side and the output side are the same on the transmission side and the reception side. The data quantity control method of the buffer is completely different. That is, the CPU 23 on the transmitting side performs a data encryption process, and the CPU 33 on the receiving side performs a decryption process for returning the ciphertext to a plaintext. A method of controlling the data quantity of the buffer will be described with reference to FIG. Further, the data transmission system 1 of FIG. 1 transmits data at the clock a. The transmission-side relay device 2 inputs / outputs data (that is, writes / reads data) to / from the input-side buffer 22 at clock b.
Data is input to and output from the output buffer 24 at the clock c. The receiving-side relay device 3 inputs / outputs data to / from the input-side buffer 32 at clock d, and inputs / outputs data to / from the output-side buffer 34 at clock e. The data receiving system 4 receives data at the clock f.

FIG. 2 is a diagram for explaining a buffer data quantity control method according to the present invention. 2, 3, 22, 2 in the figure
4, 32 and 34 are the same as in FIG. Further, each of the buffers 22, 24, 32 and 34 is, for example, a FIFO.
(First-in first-out) memory and RAM (random access memory). And buffers 22 and 2
4, 32 and 34 are memories having the same capacity.
Note that the white background portion of each buffer in FIG. 2 indicates an empty area where no data is stored, and the hunting portion indicates an area where data is stored.

The operation of FIG. 1 will be described with reference to FIG. The data transmission system 1 transmits data such as an image to the transmission-side relay device 2 at the clock a via the transmission line 51. In the transmission side relay device 2, the transmission side interface 2
The data received via 1 is sequentially stored in the input side buffer 22 at the clock b. Here, each buffer is the FI
Since it is composed of a digital memory such as FO or RAM,
The data stored in each buffer is digital data that can be directly processed by the CPU.
This digital data is output from 1.

The CPU 23 in the transmission side relay device 2 carries out a data encryption process and a data quantity control process. As an example of data block encryption, it is assumed that DES defined by the US NBS is used. In this DES, a 64-bit data block (plaintext) is made into a 64-bit ciphertext by using 56-bit key data. Therefore CP
U23 is 64 from the data stored in the input side buffer.
The data block for each bit is read, the encryption process is sequentially performed, and the encrypted data obtained as a result is sequentially stored in the output buffer 24. As shown in FIG. 2, the accumulation of data in the input-side buffer 22 and the output-side buffer 24 is performed when the output-side buffer 24 is 100% (full state in which all data is filled) and the input-side buffer 22 is
Until 50% of the capacity of the data is accumulated.

While data is being accumulated in the input side and output side buffers 22 and 24 in the transmitting side relay device 2, the CPU 33 in the receiving side relay device 3 holds dummy data (maintains continuity of data. Therefore, the meaningless data to be added before the valid data) is created and sequentially stored in the output buffer 34. This dummy data is accumulated, and as shown in FIG.
When 0% is accumulated, the CPU 33 transmits the dummy data to the data receiving system 4 via the output side interface 35 and the transmission path 53. After that CPU33
Keeps storing the dummy data in the output buffer 34 so that the data is always stored in 50% of the capacity of the output buffer 34.

The CPU 23 in the transmission-side relay device 2 is shown in FIG.
As shown in, when the output buffer 24 is full,
When the data has been accumulated up to 50% of the capacity of the input side buffer 22, the encryption start character is added to the head, the data is read from the output side buffer 24, passes through the output side interface 25, and is transmitted through the transmission line 52. Via the relay device 3 on the receiving side
Send encrypted data to.

The receiving-side relay device 3 sequentially stores the received data as digital data in the input-side buffer 32 via the input-side interface 31. Since the CPU 33 performs the data decryption process and the data quantity control process, when the encryption start character is detected via the input side buffer 32, the storage of the dummy data in the output side buffer 34 is stopped and the input side buffer 34 is stopped. A data block (ciphertext) of every 32 bits from 64 bits is read, the decryption process is sequentially performed using 56-bit key data, and the plaintext data obtained as a result is stored in the output side buffer 34.

After the dummy data, the plaintext data is transmitted from the output buffer 34, the output interface 35, and the transmission line 53 to the data receiving system 4. Therefore, the data is not interrupted between the dummy data and the valid data, and the continuity of the data is maintained.

Here, if the speeds of the clocks a, b, c, d, e and f from the data transmission system 1 to the data reception system 4 are all the same, there will be no problem because synchronization deviation does not occur. The buffer margin that can absorb the synchronization deviation when the clock speeds are not equal will be described below. (1) When the clock a of the data transmission system 1 is faster than the clock b of the transmission side relay device 2, the data is sequentially input to the input side interface 21 in the transmission side relay device 2 at the clock a, so that the input side The buffer 22 is in a state equivalent to writing data at clock a and reading data at clock b. However, in this case, in the initial state, the input-side buffer 22 in the transmission-side relay device 2 has a vacancy of 50% of its capacity, so that the synchronization deviation can be absorbed until this vacancy becomes full. After that, data loss occurs, but since it is before the data encryption processing here, the error due to this data loss does not spread to others.

(2) When the clock c of the transmission-side relay device 2 is slower than the clock d of the reception-side relay device 3, data is taken into the input-side interface 31 in the reception-side relay device 3 at the clock d. For the output side buffer 24 in the transmission side relay device 2, data is written at the clock c and the data is read at the clock d. However, in this case, in the initial state, the output side buffer 24 and the input side buffer 22 in the transmission side relay device 2 are
Since 3/4 of the total capacity (currently the two buffers 24 and 22 have the same capacity) is stored, the synchronization shift can be absorbed until the stored data becomes empty.

After this, if no measures are taken, the synchronization error will spread to all the ciphertexts thereafter. Therefore, in the present invention, before the occurrence of this condition, the C
The PU 23 encrypts the dummy data and outputs it to the output buffer 2
It is stored in 4. As a result, the data stored in the output side buffer 24 is not emptied, so that the synchronization error can be prevented from spreading to other data.

(3) When the clock c of the transmission-side relay device 2 is faster than the clock d of the reception-side relay device 3, data is input to the input-side interface 31 in the reception-side relay device 3 at the clock c. For the input side buffer 32, data is written at clock c and data is read at clock d. However, in this case, in the initial state, the total capacity of the input side buffer 32 and the output side buffer 34 (currently 2
Since the three buffers 32 and 34 have the same capacity (3/4), the synchronization deviation can be absorbed until the two buffers become full with data.

After that, if no measures are taken, the synchronization error will spread to all the ciphertexts thereafter. Therefore, in the present invention, before the occurrence of this state, the C on the receiving side is affected.
The PU 33 reads the block data from the input side buffer 32 and discards the decrypted plaintext data (does not store it in the output side buffer 34) so that only one block data is lost, and the synchronization error is converted to other data. I try to prevent it from spreading.

(4) Clock f of the data receiving system 4
Is faster than the clock e of the reception side relay device 3, the data is sequentially taken in by the data reception system 4 at the clock f, and therefore the output side buffer 34 in the reception side relay device 3 receives the data at the clock e. The state is equivalent to writing and reading data at clock f. However, in this case, in the initial state, since the output side buffer 34 in the receiving side relay device 3 has 50% of the capacity of the data, the synchronization deviation can be absorbed until the output side buffer 34 becomes empty. After that, a state of waiting for the transmission of data from the reception-side relay device 3 occurs, but since the data has already been flattened here, the synchronization deviation error does not spread to all subsequent data.

(5) When the clock a of the data transmission system 1 is slower than the clock b of the transmission side relay device 2, the clock c of the transmission side relay device 2 of (2) is the clock of the reception side relay device 3. The result is the same as when d is later than d.
Further, when the clock f of the data receiving system 4 is slower than the clock e of the receiving side relay device 3, as a result, the clock c of the transmitting side relay device 2 in (3) is faster than the clock d of the receiving side relay device 3. It becomes the same state as.

In the above embodiment, the buffers 22, 24, 32 and 34 in the relay device have the same capacity, and the data quantity accumulated in the buffers 22 and 24 in the initial state of transmission is 50% of the buffer capacity. 100%,
In the initial state of reception, the empty quantity that can store data in the buffers 32 and 34 is 100% of the buffer capacity and 50
However, the present invention is not limited to this and may be controlled to other quantities. In addition, when the system is actually operated, the amount of data stored and the number of available data in the initial state may be variably controlled according to the frequency of occurrence of a state in which valid data is lost or a valid data transmission waiting state occurs.

[0030]

As described above, according to the present invention, the clock system is different between the transmission side and the reception side, and the transmission side relay device for performing the encryption process for each data block and the decryption process for each data block are provided. In a half-duplex communication system including a receiving-side relay device for performing, the transmitting-side relay device has an input-side buffer for storing plaintext data and an output-side buffer for storing encrypted data, The number of plaintext data and encrypted data stored in the input side buffer and the output side buffer is controlled to a fixed number respectively,
Further, the receiving-side relay device has an input-side buffer for storing encrypted data and an output-side buffer for storing plaintext data, and can store data in the input-side buffer and the output-side buffer in the initial reception state. The number of empty spaces is controlled to a fixed number, respectively, and a certain number of data stored in both buffers in the sending side relay device and a certain number of empty numbers prepared in both buffers in the receiving side relay device. Since the synchronization deviation within the range can be absorbed, the occurrence frequency of the synchronization deviation between the transmission side relay apparatus and the reception side relay apparatus, which has a very large influence, can be calculated between the transmission system and the transmission side relay apparatus and between the reception side relay apparatuses. This is effective in reducing the frequency of occurrence of synchronization deviation between the receiving system and the receiving system. Further, even when the synchronization deviation exceeds the range in which the synchronization deviation can be absorbed, it becomes possible to prevent the synchronization deviation error from spreading to other data.

Further, according to the present invention, the quantities of plaintext data and encrypted data accumulated in the input side buffer and the output side buffer in the initial state of transmission of the transmitting side relay device are respectively 50% and 100% of the buffer capacity. In the initial state of reception of the receiving side relay device, the number of empty spaces that can store data in the input side buffer and the output side buffer is 100% and 5% of the buffer capacity, respectively.
By controlling to 0% and making the capacities of both buffers equal, it is possible to absorb the synchronization deviation within the range of 150% of the single buffer capacity.
Compared with the case of 0%, the synchronization deviation absorption capacity is 3
Can be doubled.

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronization deviation reducing device between relay devices according to the present invention.

FIG. 2 is a diagram illustrating a data quantity control method of a buffer according to the present invention.

FIG. 3 is a conceptual diagram of a conventional synchronization deviation absorbing method.

[Explanation of symbols]

 1 data transmission system 2 transmission side relay device 3 reception side relay device 4 data reception system 21, 31 input side interface 22, 32 input side buffer 23, 33 CPU 24, 34 output side buffer 25, 35 output side interface 51-53 transmission Road

Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display area H04L 9/14

Claims (2)

[Claims] 1. A half system including a transmitting-side relay device that performs an encryption process for each data block and a receiving-side relay device that performs a decryption process for each data block. In a multiple communication system, the transmission-side relay device includes an input-side buffer that stores plaintext data and an output-side buffer that stores encrypted data, and sequentially encrypts data blocks read from the input-side buffer. And storing it in the output side buffer, and means for controlling the quantity of plaintext data and encrypted data stored in the input side buffer and the output side buffer in a transmission initial state to a fixed number respectively, and the receiving side The relay device has an input-side buffer that stores encrypted data and an output-side buffer that stores plaintext data. A means for sequentially decoding the output data block and storing it in the output side buffer; and means for controlling the number of empty spaces capable of storing data in the input side buffer and the output side buffer in a reception initial state to a fixed number respectively. A synchronization deviation reducing device between relay devices, comprising: 2. The means for controlling the transmission side relay device to control the quantity of plaintext data and encrypted data stored in the input side buffer and the output side buffer in the initial state of transmission to 50% and 100% of the buffer capacity, respectively. The receiving-side relay device sets the number of free spaces in the input-side buffer and the output-side buffer in the initial reception state to 100% and 50% of the buffer capacity, respectively.
The synchronization deviation reducing device between the relay devices according to claim 1, further comprising: