JPH0685761A - Digital signal transmitter - Google Patents

Abstract

PURPOSE:To send digital data at a high bit rate such as data with a high sam pling frequency or data with lots of quantization bit numbers through a transmis sion circuit. CONSTITUTION:The transmitter is provided with a data division circuit 4 dividing data at a high bit into plural samples, plural transmission circuits 1, 11 modulating data at a low bit rate divided by the data division circuit 4 and sending the modulated data, reception circuits 2, 12 receiving plural signals at a low bit rate and demodulating the signals, and a data coupling circuit 5 coupling the plural data at a low bit demodulated by the reception circuits 2, 12. Thus, the data at a high bit rate such as data with a high sampling frequency or data with lots of number of bits are sent through the transmission circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmission device used for transmitting digital data such as a digital audio signal.

[0002]

2. Description of the Related Art In recent years, so-called digital audio technology for converting an analog signal such as a music signal into a digital signal and recording / reproducing it has been remarkably developed. For example, there are a PCM processor using a VTR mechanism and a tape, a compact disc, a DAT and the like. The DAT is described in detail as a DAT cassette in the Japan Electronic Machinery Manufacturers Association Standard CP-2305. The DAT, which is a conventional digital signal transmission device, will be described below.
The DAT has a digital audio interface of AES / EBU format and can transmit audio data. FIG. 4 is a block diagram of DAT. 4a is a digital audio output terminal, 4b is a digital audio input terminal, 41 is a transmission circuit, 51 is a driver circuit, 52 is a preamble addition circuit, 53 is a biphase mark modulation circuit, 54 is a parity addition circuit, and 55 is a data register circuit. Is. 42 is a receiver circuit, 71 is a receiver circuit, 72 is a PLL circuit, 73 is a synchronization extraction circuit, 74 is a biphase mark demodulation circuit, 7
5 is a parity check circuit, and 76 is a data register circuit. Reference numeral 43 is a recording / reproducing circuit. 41 transmitter circuits,
The receiving circuit 42 is a digital audio interface of AES / EBU format. The above two D
Dubbing is performed by connecting an AT with an AES / EBU format digital audio interface cable, setting one in a reproduction mode to transmit audio data, and the other in a recording mode to receive audio data.

In the DAT on the transmitting side, the reproduced audio data having the quantization bit number of 16 bits and the sampling frequency of 48 kHz obtained from the recording / reproducing circuit 43 is supplied with sub data such as sampling frequency and emphasis information in the data register circuit 55 of the transmitting circuit 41. Then, the parity is added by the parity adding circuit 54. After that, biphase mark modulation circuit 53 performs biphase mark modulation, and preamble addition circuit 52 adds a preamble and sends it to driver circuit 51. Driver circuit 51
Then, level conversion, impedance conversion, etc. are carried out and output to the digital audio output terminal 4a. The output of 4a is a digital interface cable and D on the receiving side.
It is input to the digital audio input terminal 4b of the AT.

On the receiving side, the received signal is amplified and shaped by the receiver circuit 71. The PLL circuit 72 reproduces a clock from the amplified and shaped reception signal, and the synchronization detection circuit 73 detects synchronization based on this clock. Further, the received signal is biphase-mark demodulated by the regenerated clock in the bi-phase mark demodulation circuit 74, and after checking the parity in the parity check circuit 75, it is temporarily stored in the data register circuit 76, and the audio data and the sub-data are recorded. And is sent to the recording / reproducing circuit 43.

The recording / reproducing digital data of DAT has a sampling frequency of 48 kHz, 44.1 kHz or 32 kHz.
It has three modes of Hz, and the number of quantization bits is 16 bits. With the AES / EBU format digital audio interface, the sampling frequency of the audio data that can be transmitted is 48 kHz, 44.1 kHz.
Alternatively, at 32 kHz, the maximum number of bits per sample is 24 bits.

FIG. 5 is a format diagram of a digital interface signal of AES / EBU format. One sample of audio data is sent in a subframe which is the minimum unit of transmission. A subframe consists of 32 time slots. The digital audio data is stored in the audio sample words 93 of time slots 8 to 27. Time slots 0 to 3
The preamble 91 is a sync signal for frame synchronization. The AUX 92 of the time slots 4 to 7 is a spare slot of the audio original or audio sample word which is the sub information. The validity flag (V) 94 of the time slot 28 is a flag indicating the reliability of the audio sample word. Time slot 29
The user frequency (U) 95 and the channel status (C) 96 of the time slot 30 store the sampling frequency and emphasis information as sub data.
The parity bit (P) 97 of the time slot 31 stores the even parity of the time slots 4 to 31. A sub-frame for the left channel and a sub-frame for the right channel make up a frame.

[0007]

In the digital signal recording / reproducing apparatus, there is an increasing demand for a further increase in the number of quantization bits of the digital signal and the sampling frequency. However, in the configuration of the above-described conventional digital signal transmission device, when recording / reproducing data having a sampling frequency of, for example, 96 kHz by the recording / reproducing circuit and transmitting this by the digital signal transmitting device, the permissible bit rate of the transmitting circuit or the receiving circuit is exceeded. Therefore, there was a problem that it could not be transmitted.

The present invention solves the above-mentioned problems of the prior art. A high bit rate in which the number of quantization bits and the sampling frequency are increased by using a conventional low bit rate transmission circuit and a plurality of low bit rate reception circuits is provided. An object of the present invention is to provide a digital signal transmission device capable of transmitting rate data.

[0009]

In order to achieve this object, a synchronization device of the present invention comprises a data dividing circuit for dividing high bit rate data into a plurality of samples, a plurality of low bit rate transmitting circuits, and a plurality of low bit rate transmitting circuits. A low bit rate receiver circuit,
It has a configuration of a data combining circuit for combining a plurality of low bit rate data.

[0010]

According to the present invention, with the above-described structure, high-bit-rate digital data such as data having a high sampling frequency or data having a large number of quantization bits can be matched with the sampling frequency or the quantization bits of the conventional interface format. The sample is divided, and the divided digital data is transmitted at a low bit rate by a plurality of conventional transmission circuits. The receiving side demodulates a plurality of received signals and combines the original data from the demodulated samples.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a digital signal transmission apparatus according to a first embodiment of the present invention. In FIG. 1, a1 and a2 are digital audio output terminals, and b1 and b2 are digital audio input terminals. 1, 11 are transmitting circuits, 51, 61 are driver circuits, 52, 62 are preamble adding circuits, 53, 63
Is a bi-phase mark modulation circuit, 54 and 64 are parity adding circuits, and 55 and 65 are data register circuits.
2, 12 are receiver circuits, 71 and 81 are receiver circuits, 7
2, 82 are PLL circuits, 73, 83 are synchronization extraction circuits, 7
4, 84 are biphase mark demodulation circuits, 75, 85 are parity check circuits, and 76, 86 are data register circuits. 3 is a signal processing circuit, 4 is a data dividing circuit, 5
Is a data coupling circuit. The operation of the digital signal transmission apparatus of this embodiment constructed as above will be described below.

The above two digital signal transmission devices are AE
Connect with a digital audio interface cable of S / EBU format. The signal processing circuit 3 handles digital data having a sampling frequency of 96 kHz and a quantization bit number of 16 bits on both the transmitting side and the receiving side. The transmission circuits 1 and 11 and the reception circuits 2 and 12 are the same as the blocks used in the conventional digital signal transmission device DAT.

The digital signal transmission device on the transmission side sends the reproduction data of 16 bits and 96 kHz obtained from the signal processing circuit 3 to the data division circuit 4. In the data division circuit 4,
As shown in FIG. 2, the 96 kHz sampling audio data 101 of the right channel (Rch) and the left channel (Lch) are converted into two audio data sequences of even number and odd number of 48 kHz, and the even number data 102 is transmitted by the transmission circuit 1.
To send the odd column data 103 to the transmission circuit 11.

In the transmission circuit 1 and the transmission circuit 11, the data register circuits 55 and 65 convert the audio data into audio data,
Add sub data. Here, in addition to the conventional sub-data such as the validity flag, channel status, and user bit, sub-data indicating whether the audio data is even-numbered column data or odd-numbered column data is added as channel status. Further, the parity adding circuits 54 and 64 generate and add parity. After that, biphase mark modulation circuits 53 and 63 perform biphase mark modulation, preamble addition circuits 52 and 62 add preambles, and the preambles are sent to driver circuits 51 and 61. Level conversion and impedance conversion are performed in the driver circuits 51 and 61, and output to the digital audio output terminals a1 and a2. The output of a1 and a2 is 2
It is input to the digital audio input terminals b1 and b2 of the digital signal transmission device on the receiving side with this digital interface cable.

On the receiving side, the receiving circuit 2 and the receiving circuit 12
Amplified and shaped by the receiver circuits 71, 81 of the PLL
The circuits 72 and 82 reproduce the clock, and the synchronization detection circuits 73 and 83 detect the synchronization based on the clock. Further, it is demodulated by the clock reproduced by the bi-phase mark demodulation circuits 74 and 84, and the parity check circuits 75 and 8
After checking the parity at 5, the data is temporarily stored in the data register circuits 76 and 86 and divided into audio data and sub data. The 48 kHz audio data reproduced by the respective receiving circuits 2 and 12 and sub data indicating whether the data is the even column data or the odd column data reproduced from the channel status are sent to the data combining circuit 5. In the data combination circuit 5, as shown in FIG.
Even column data 202 and odd column data 2 based on sub data
The audio data 201 of 03 to 96 kHz is combined. The combined audio data 201 is sent to the signal processing circuit 3 where it is recorded or converted.

As described above, according to this embodiment, a data dividing circuit for dividing high bit rate data into a plurality of samples, a plurality of low bit rate transmitting circuits, a plurality of low bit rate receiving circuits, and a plurality of low bit rate receiving circuits. By providing a data combining circuit for combining low bit rate data, it is possible to transmit high sampling frequency data and high bit rate digital data such as data having a large number of bits in a conventional transmission circuit and reception circuit. .

In the present embodiment, the data is divided into even-numbered columns and odd-numbered columns, but the division method may be other than this, for example, if the transmission data is stereo data, it is divided into the right channel and the left channel. May be.

Further, in this embodiment, the sub data indicating whether it is an even column or an odd column is transmitted by using the channel status. However, even if it is not the channel status, for example, a user's bit may be used or an audio ogi. You can also use a shari.

Further, even if the method of inserting information of even columns and odd columns into sub data is not used, the digital audio input / output terminals for even and odd columns are uniquely determined and fixed in the data division / coupling circuit accordingly. You may perform the process of division and connection.

Further, instead of increasing the sampling frequency, data division and combination may be performed in response to an increase in the number of quantization bits, and the data may be transmitted by a plurality of circuits.

[0021]

As described above, according to the present invention, a data dividing circuit for dividing high bit rate data into a plurality of samples, a plurality of low bit rate transmitting circuits, a plurality of low bit rate receiving circuits, and a plurality of low bit rates. By providing a data combining circuit for combining rate data, it is possible to transmit high sampling frequency data and high bit rate digital data such as data having a large number of bits by a conventional transmission circuit or reception circuit. That is, conventional interface cables and interface circuits can be used as they are,
Since the transmission bit rate per line does not change, the increase of unwanted radiation can be reduced, and efficient and economical transmission can be achieved, which is very effective.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital signal transmission device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a method of dividing audio data in a data division circuit of a digital signal transmission device according to an embodiment of the present invention.

FIG. 3 is a diagram showing a method of combining audio data in a data combining circuit of a digital signal transmission device according to an embodiment of the present invention.

FIG. 4 is a block diagram of a conventional digital signal transmission device, DAT.

FIG. 5 is a diagram showing a format of a digital interface signal of AES / EBU format.

[Explanation of symbols]

4a, a1, a2 Digital audio output terminal 4b, b1, b2 Digital audio input terminal 1, 11, 41 Transmission circuit 51, 61 Driver circuit 52, 62 Preamble addition circuit 53, 63 Bi-phase mark modulation circuit 54, 64 Parity addition circuit 55,65 Data register circuit 2,21,42 Receiver circuit 71,81 Receiver circuit 72,82 PLL circuit 73,83 Sync extraction circuit 74,84 Bi-phase mark demodulation circuit 75,85 Parity check circuit 76,86 Data register circuit 3 Signal processing circuit 43 Recording / reproducing circuit 4 Data dividing circuit 5 Data combining circuit 93 Audio sample word 91 Preamble 92 Audio original (AUX) 94 Validity flag (V) 95 User bit (U) 96 Channel status (C) 97 Parity bit (P) 101,102 96kHz sampling audio data 102,202 Even column data 103,203 Odd column data

Claims (2)

[Claims] 1. A data division circuit for dividing high bit rate data into a plurality of samples, a plurality of transmission circuits for modulating and transmitting the low bit rate data divided by the data division circuit, and a plurality of low bit rates. A digital signal transmission device comprising a receiving circuit for receiving and demodulating the signal of 1. and a data combining circuit for combining a plurality of low bit rate data demodulated by the receiving circuit. 2. The digital signal transmitting apparatus according to claim 1, wherein the low bit rate transmitting circuit and the receiving circuit are AES / EBU format digital audio interfaces.