JPH0685657A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To decrease the breakdown strength of a bipolar transistor when aging is performed and to improve a cutoff frequency. CONSTITUTION:The potential of the source 3 of the NMOS 500 for base discharge of a pull-up bipolar transistor 100 and the potential of the source 4 of the PMOS 401 for pull-down are used separately in an ordinary operation and the aging, respectively. When the ordinary operation is performed, a voltage higher than GND2 is supplied to the source 3, and a voltage lower than a positive power source VCC to the source 4. When aging, the GND potential and the VCC are supplied to the source 3 and source 4 respectively. At this time, the voltage between the gate and source applied to the MOSs 400, 401, 500, and 501 and the voltage between the drain and source are set equal to the power source VCC in the aging. Thereby, it is possible to set a source voltage in the aging at the one required for the aging of the MOS and to set required breakdown strength (BVCEO) equal to the aging voltage of the MOS. Therefore, fT can be improved by suppressing BVCEO at a low level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to aging of BiCMOS circuits.

[0002]

2. Description of the Related Art Conventionally, a circuit disclosed in Japanese Patent Application Laid-Open No. 2-260713 has been proposed as a basic gate circuit of a BiCMOS LSI. The inverter circuit 605 in FIG. 1 shows a circuit that is substantially similar to the conventional circuit disclosed in this publication. In the figure
400 and 401 are P-channel MOS (hereinafter referred to as PMOS) transistors, 500 and 501 are N-channel MOS (hereinafter referred to as NMO)
The transistor 100 is a bipolar transistor. In the inverter circuit 605 of FIG. 1, the output 2
Bipolar transistor 1 charging a load connected to 0
The source of the PMOS 401, which supplies a high level potential (hereinafter, H level) of the output 20 by supplying the source electrode 3 of the NMOS transistor 500 for discharging the base charge of 00 with a voltage higher than the GND potential 2 by 0.5 to 0.9 V. By supplying the electrode 4 with a voltage 0.5 to 0.9 V lower than the power supply voltage V _CC of the positive power supply 1,
The voltage V _DS applied between the source and drain of the PMOS 400, 401, NMOS 500, 501 is 0.5 from the power supply voltage V _CC.
It becomes smaller by ~ 0.9V. This makes it possible to apply a power supply voltage that is 0.5 to 0.9 V higher than that of the CMOS circuit of the same processing technology, and realize a higher speed operation than the CMOS circuit even if the processing technology is downsized to 0.2 μm. it can.

[0003]

In the circuit 605 of FIG. 1, the
From the potential of GND2 to the source 3 of the NMOS 500 for discharging the base charge of the load charging bipolar transistor 100 from 0.5 to 0.
A PMOS4 that supplies a high voltage of 9V and provides an output H level
By supplying the source 4 of 01 with a voltage 0.5 to 0.9 V lower than V _CC,
Although a high-speed operation was realized by applying a 0.9 V higher power supply voltage, the operation during an aging test, in which a stress voltage higher than a normal voltage is applied to a semiconductor integrated circuit to evaluate reliability, is not mentioned. . In this way, the source 3 of the base charge discharging NMOS 500 is 0.5 to 0.5
PM that supplies 0.9V higher voltage and gives output H level
When a voltage lower than V _CC by 0.5 to 0.9 V is supplied to the source 4 of the OS 401, the source-drain voltage V _{DS of} the MOS becomes 0.5 to 0.9 V lower than the power supply voltage V _CC . Power supply voltage or bipolar transistor
The voltage applied between the collector and the emitter of 100 must be 0.5 to 0.9 V higher than the voltage required for aging the MOS. Therefore, the required collector-emitter breakdown voltage BV _CEO is 0.5 than the voltage required for MOS aging.
Increases by ~ 0.9V. However, the cutoff frequency f _T and BV _CEO of the bipolar transistor is an important factor for determining the performance of the BiCMOS circuit Torre - located on offs relationship, f _T decreases by increasing the BV _CEO, Bi
This leads to deterioration of the performance of the CMOS circuit.

Therefore, it is an object of the present invention to provide a BiCMOS circuit which makes it possible to use a high f _T bipolar transistor by setting the BV _CEO required for aging to about the voltage required for MOS aging. .

[0005]

In order to achieve the above object, in order to make the voltage applied to the bipolar transistor (100) at the time of aging the voltage required for aging of the MOS, it is necessary to perform the operation at the time of normal operation and at the time of aging. NMO for base charge discharge of load charging bipolar transistor (100)
The potential of the source (3) of S (500) and the potential of the source (4) of the PMOS (401) which gives the H level of the output (20) are separated. During normal operation, the source (3) of the base charge discharge NMOS transistor (500) is supplied with a voltage higher than GND (2) by 0.5 to 0.9 V, and the source (4) of the PMOS (401) is supplied with a positive power source V. Supply a voltage 0.5 to 0.9V lower than _CC (1). During aging, the GND potential is supplied to the source (3) of the NMOS transistor (500) and V _CC is supplied to the source (4) of the PMOS (401).
(Figs. 1 and 2).

[0006]

[Function] When aging, the source (3) of the NMOS (500)
Supply the GND potential and supply the power source V to the source (4) of PMOS (401)
By supplying _CC (FIGS. 1 and 2), the signal amplitude of the output (20) becomes equal to the power supply voltage V _CC . Since the output signal (20) is the input signal of other circuits, each MO will be
The gate-source voltage V _GS , the drain-source voltage V _DS, and the power supply voltage V _CC applied to the S transistors (400, 401, 500, 501) become equal. As a result, the power supply voltage during aging can be made a voltage required for aging of the MOS, and the collector-emitter breakdown voltage BV _CEO required for the bipolar transistor also becomes equal to the aging voltage of the MOS. Therefore, BV _CEO can be kept low to improve the cutoff frequency f _T of the bipolar transistor.
Higher speed of the iCMOS circuit can be achieved.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows Bi which enables aging according to the present invention.
It is a circuit diagram showing an embodiment of a CMOS basic gate circuit,
FIG. 2 shows the relationship between the potentials of the voltages 3 and 4 of the circuit of FIG. 1 and the power supply voltage. The BiCMOS circuit 605 (400, 401, 50 of FIG.
0, 501, 100) is an inverter circuit that outputs a signal having a phase opposite to the signal of the input 10 to the output 20 in response to the input signal 10, and the circuit 600 is another circuit in the chip having the same configuration as the 605. BiC
It is a MOS circuit. Especially when aging, BiCM
V _GS added to the MOS 400, 401, 500, 501 of the OS circuit,
In order to equalize V _DS and V _CC and equalize the required BV _CEO and MOS aging voltage, the potential 3 of the source of the NMOS 500 and the potential 4 of the source of the PMOS 401 are devised as follows. That is, during normal operation, a voltage higher than GND by 0.5 to 0.9 V is supplied to the source 3 of the NMOS 500, and P
A voltage of 0.5 to 0.9 V lower than V _CC is supplied to the source 4 of the MOS 401. As a result, CMOS of the same processing technology
It is possible to apply a power supply voltage higher than the circuit by 0.5 to 0.9 V. The source potential of NMOS 500 is GND
It is 0.5 to 0.9 V higher than this, and the low level potential of the gate potential (hereinafter referred to as L level) is the GND potential, so it is desirable that the NMOS 500 has a low V _TH . At the time of aging to apply a voltage higher than that in normal operation, the source 3 of the NMOS 500
By supplying approximately GND potential to (Fig. 2), MOS 400, 500
V _DS and V _CC of can be made equal. Further, by supplying the power source V _CC to the source 4 of the PMOS 401 (FIG. 2), the MOS 40
The drain-source voltages V _DS and V _{CC of 1} and 501 can be made equal, and the signal amplitude of the output 20 and the power supply voltage V _CC can be made equal. Since the output signal 20 is an input signal of another internal circuit, V _GS applied to the MOSs 400, 401, 500 and 501 during aging can be equal to the power supply voltage V _CC . By implementing this control in the circuits 601 and 602, the power supply voltage during aging can be set to the voltage required for MOS aging, and BV
_CEO also becomes equal to the aging voltage of MOS. Therefore B
V _CEO can be kept low to improve f _T.
Higher speed of the CMOS circuit can be achieved. Reference voltage circuit 60
The 1 and 602 may be externally controlled to generate the voltage during normal operation or aging, but if the power supply voltage is detected and the 601 and 602 are controlled by that signal, the number of chip signal terminals can be increased. You don't have to.

FIG. 3 shows a voltage generator circuit 601 of the present invention shown in FIG.
Is an example. During normal operation, the PMOS 402 is non-conducting. The potential of 4 becomes a value lower than V _CC by the value obtained by dividing the base-emitter voltage V _BE of the bipolar 101 by the resistors 200 and 201. The bipolar 102 is an element provided to clamp the potential of 4 to the voltage of V _CC -V _BE when the potential of 4 is lowered, and the capacitor 300 is an element provided to reduce potential fluctuation of 4. . By conducting the PMOS 402 during aging, the potential of 4 is set to approximately V _CC .

FIG. 4 shows an example of the voltage generating circuit 602 of the present invention. During normal operation, the NMOS 502 is turned off. The potential of 3 becomes higher than the GND potential by the value obtained by dividing V _BE of the bipolar 103 by the resistors 204 and 205. Bipolar 104
Is an element provided to clamp the potential of 3 to the potential of + V _{BE when} the potential of 3 rises, and the capacitor 301 is an element provided to reduce the potential fluctuation of 3. By conducting the NMOS 502 during aging, the potential of 3 is approximately GND.
The potential.

FIG. 5 shows the power supply voltage of the present invention, which is 40 in FIG.
2 is an example of a circuit for controlling conduction / non-conduction of 502 in FIG. In the circuit of FIG. 5, the potential V _CC −3V _{BE of} 40 and the potential 2 of 41 are used.
V _BE is compared and the result is output to the gate 30 of the PMOS 402 of FIG. 3 and the gate 31 of the NMOS 502 of FIG.
Incidentally, the PMOS 403, 404, 405, 406 and the NMOS 50 of FIG.
Reference numerals 3, 504 and 505 form a differential amplifier, and terminal 5 indicates a bias terminal for supplying a current to 403 and 404. Power supply voltage V _CC
If it is less than 5V _BE , the potential of 40 is less than 41 and the potential is NM.
The gate potential of OS 505 becomes L level. This gives 31
Indicates L level, 30 indicates H level, 402 in FIG. 3, 502 in FIG.
Becomes non-conductive. When the power supply voltage V _CC is higher than 5V _BE , the potential of 40 becomes higher than that of 41 and NMOS
The gate potential of 505 becomes H level. As a result, 31 becomes H level, 30 becomes L level, and 402 in FIG. 3 and 502 in FIG. 4 become conductive.

FIG. 6 shows another example of the aging method of the BiCMOS basic gate circuit of the present invention. In FIG. 2, the potential 4 of the source of the PMOS 401 is approximately V _CC during aging.
However, the potential of 4 may be higher than V _CC as shown in FIG. In the method of FIG. 6, there is a possibility that a sufficient acceleration voltage cannot be applied to the gate of PMOS 400.
Since a sufficient voltage can be applied between the gate and source of the MOS and between the drain and the source of the MOS, it is effective for aging of an LSI in which most of the chip is an NMOS such as a memory of a high resistance load type memory cell. The potential of 4 may be applied from the outside, but it goes without saying that it can be generated inside the chip.

FIG. 7 shows another example of the aging method of the BiCMOS basic gate circuit of the present invention. FIG. 8 shows the relationship between the potential of each part of the circuit of FIG. 7 and the power supply voltage.
In FIG. 6, since only the source potential 4 of the PMOS 401 is set to a potential higher than V _CC during aging, it is possible that a sufficient acceleration voltage cannot be applied to the gate of the PMOS 400. In the circuit of FIG. 7, the potential 6 of the source of the PMOS 400 is set to a potential higher than V _CC during aging, so that the PMO
It is devised so that a sufficient voltage is applied to S 400 as well. In the circuit of FIG. 7, the collector and the base of the bipolar 100 are forward-biased, but if the forward-bias is about 0.5 V, the forward current that flows is small and the degree of saturation is small, so there is no problem of aging. 6 of the hour
The potential of is higher than V _CC by about 0.5V. It goes without saying that the potential of 6 may be applied from the outside or generated internally.

[0013]

As described above, according to the present invention, the CM of the same processing technique is used during the normal operation of the conventional BiCMOS circuit.
BV required for aging without impairing the characteristic that a power supply voltage higher than that of the OS circuit by 0.5 to 0.9 V can be applied
By lowering the _CEO and improving f _T , BiCM
The speedup of the OS circuit can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram of a BiCMOS circuit and a power supply circuit showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of generated voltage-power supply voltage characteristics of a power supply circuit used in the present invention.

FIG. 3 is a diagram showing an example of a power supply circuit of the present invention.

FIG. 4 is a diagram showing an example of a power supply circuit of the present invention.

FIG. 5 is a diagram showing an example of a control signal generation circuit of the power supply circuit of the present invention.

FIG. 6 is a diagram showing another example of the voltage-power supply voltage characteristic of each part of the circuit of FIG. 1 of the present invention.

FIG. 7 is an example of a BiCMOS circuit showing an embodiment of the present invention.

8 is a diagram showing an example of voltage-power supply voltage characteristics of each part of the circuit of FIG. 7 of the present invention.

[Explanation of symbols]

1. ． ． Positive power supply terminal, 2. ． ． GND terminals 3, 4,
6. ． ． Voltage terminal, 5. ． ． Bias voltage terminal, 1
0. ． ． Signal input terminal, 20. ． ． Signal output terminal, 4
0, 41. ． ． Internal terminals, 30, 31. ． ． Power supply circuit control signal terminal, 100 series. ． ． Bipolar transistor, 200 series. ． ． Resistance, 300s. ． ． capacity,
400 series. ． ． PMOS transistor, 500 series. ． ． NMOS transistor, 700 series. ． ． Current source, 600. ． ． BiCMOS circuit, 601, 60
2. ． ． Voltage generating circuits 603, 604, 605. ． ．
Inverter circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masataka Minami Minamitaka Minami 4026 Kujicho, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Inc. Central Research Center

Claims (4)

[Claims] 1. A gate circuit comprising a bipolar transistor and a CMOS circuit, wherein the output of the CMOS circuit is connected to the base of the bipolar transistor, wherein the source potential of the NMOS transistor of the CMOS circuit is set during normal operation and during an acceleration test. A semiconductor integrated circuit having different values, wherein the source potential of the NMOS transistor during the acceleration test is lower than that during the normal operation. 2. A bipolar transistor and a CMOS circuit, wherein the output of the CMOS circuit is connected to the base of the bipolar transistor, the emitter of the bipolar transistor is connected to the drain of the first PMOS transistor, and the first PMOS is connected. In the gate circuit in which the gate electrode of the transistor is connected to the input terminal of the CMOS circuit, the source potential of the first PMOS transistor is set to different values during normal operation and during the acceleration test, and the first PMOS during the acceleration test is performed. A semiconductor integrated circuit, wherein the source potential of the transistor is set higher than that in the normal operation. 3. A bipolar transistor and a CMOS circuit, wherein the output of the CMOS circuit is connected to the base of the bipolar transistor, the emitter of the bipolar transistor is connected to the drain of the first PMOS transistor, and the first PMOS is connected. In a gate circuit in which a gate electrode of a transistor is connected to an input terminal of a CMOS circuit, the source potential of the first PMOS transistor is set to different values during normal operation and during an acceleration test, and the first PMOS transistor during the acceleration test is performed. Source potential of CM above
A semiconductor integrated circuit having a voltage higher than a power supply voltage of an OS circuit. 4. A gate circuit comprising a bipolar transistor and a CMOS circuit, wherein the output of the CMOS circuit is connected to the base of the bipolar transistor, wherein the source potential of the PMOS transistor of the CMOS circuit during the acceleration test is the collector potential of the bipolar transistor. A semiconductor integrated circuit characterized by being made higher.