JPH0685062A - Design of cell base layout - Google Patents

Abstract

PURPOSE:To enable higher integration of a semiconductor integrated circuit by improving usage efficiency of the first wiring layer. CONSTITUTION:Rectangular areas 17P and 17N which traverse in parallel with a pair of power source wirings 13P and 13N, with no inter-cell wiring between them in the same wiring layer in the standard cell, are allowed to extend/ contact in the direction orthogonal to the power source wirings 13P and 13N within a specified range, and the rectangular-area of the wiring layer is set as the inter-cell wiring channels 17P and 17N, and further, wiring tracks T1P, T2P, T1N and T2N are run in the direction parallel with the power source wirings 13P and 13N, and in addition, the number of wiring tracks is set variable within the range specified by the extension/contraction. On the inter-cell wiring channels 17P and 17N, inter-cell rough routing is made so as to decide the number of wiring tracks in the inter-cell wiring channel, and then based upon the decided number of wiring tracks, the rectangle area of the standard cell is extended/contracted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell-based layout design method.

[0002]

2. Description of the Related Art In cell-based design, patterns of basic gates and logic circuits that are frequently used are registered in advance as standard cells, and layout design is performed by arranging standard cells and wiring between cells.

FIG. 9 shows an example of a conventional standard cell. This standard cell is a CMOS inverter, and a pair of P-type diffusion region 11P and N-type diffusion region 11 are provided in the cell frame 10.
N, a gate 12 made of polysilicon or the like extending on the P-type diffusion region 11P and the N-type diffusion region 11N, and a pair of high-potential-side power supply wirings 13 extending on the gate 12 in a direction perpendicular to 12
P and the low potential side power supply wiring 13N and the power supply wirings 13P and P
The contact 14P for connecting the source of the type diffusion region 11P, the power supply wiring 13N, and the N type diffusion region 11N.
A contact 14N for connecting to the source of
To connect the in-cell wiring 15 of the first wiring layer (first metal wiring layer from the semiconductor substrate) extending in parallel with the gate 12 to one end of the in-cell wiring 15 and the drain of the P-type diffusion region 11P Contact 16P and a contact 16N for connecting the other end of the in-cell wiring 15 and the drain of the N-type diffusion region 11N.

The power supply wirings 13P and 13N are wirings of the first wiring layer (first layer wirings), and the longitudinal direction thereof is parallel to the cell row, and when this direction is taken as the X direction, it is the second from the semiconductor substrate side. The longitudinal direction of the power supply wiring of the second wiring layer which is the metal wiring layer is the Y direction perpendicular to the X direction, and the power supply wiring of the third wiring layer which is the third metal wiring layer from the semiconductor substrate side is The longitudinal direction is the X direction. Therefore, only the second wiring layer can be used for wiring between different cell columns.
If the number of wiring tracks in the second wiring layer is insufficient, it is necessary to secure a new wiring area between cells and perform wiring, so that the degree of circuit integration is reduced.

In the recent cell-based design, in order to improve the degree of integration, not only the in-cell wiring but also the inter-cell wiring is performed using the first wiring layer on the cell. For this on-cell wiring, the wiring tracks T1P, T2P,
TN1 and TN2 are set, and wiring between cells is performed by laying wiring on this track.

[0006]

However, in the prior art, since the track of the on-cell wiring was fixed, the wiring track was unused and wasted, or conversely, the wiring tracks were insufficient and the second wiring layer and Since it has been necessary to use the contact for interlayer connection, it has been a cause of lowering the degree of integration.

Further, at present, generally, a semi-custom LS is used.
I is a cell-based design for grid layout, and full-custom LSI is a manual design for gridless layout. However, if the microfabrication technology further advances and tens of millions of transistors can be integrated on one chip, the proportion of cell-based designs in full-custom LSIs will increase. Therefore, there is a strong demand for a method of performing wiring so that the degree of integration becomes higher when the gridless layout is performed by the compaction after the grid layout is performed.

In view of the above problems and circumstances, it is an object of the present invention to provide a cell-based layout designing method which improves the use efficiency of the first wiring layer and enables high integration of a semiconductor integrated circuit. is there.

[0009]

A cell-based layout designing method according to the present invention will be described with reference to the drawings according to the embodiments.

In the present invention, for example, as shown in FIGS.
(70) A pair of pre-registered parallel power supply wirings 13
After arranging standard cells including P and 13N and roughly wiring between the standard cells, (74) a layout design of the semiconductor integrated circuit is performed by making the rough wiring detailed wiring.

Regarding the standard cell, the power source wirings 13P and 1P are provided between the pair of power source wirings 13P and 13N of the standard cell.
The rectangular areas 17P and 17N that intersect in parallel with the power supply wirings 13P and 13N, in which the inter-element wiring in the standard cell does not exist in the same wiring layer (first wiring layer) as 3N, are connected to the power supply wirings 13P and 1P.
3N is made expandable / contractible within a predetermined range in a predetermined range, the rectangular region of the wiring layer is used as an inter-cell wiring channel, and wiring tracks T1P to Through T3P and T1N to T3N, the number of the wiring tracks is made variable within a predetermined range determined by the expansion / contraction range.

(70-73) The inter-cell wiring channel is roughly wired to determine the number of wiring tracks in the inter-cell wiring channel, and the number of wiring tracks in the standard cell is determined based on the determined number of wiring tracks. Stretch a rectangular area.

This expansion / contraction range is limited due to the characteristics of the transistor. When the rectangular regions 17P and 17N are shortened by this method, the useless first-layer wiring region becomes narrower and the first
The use efficiency of the wiring layer can be improved, and the degree of integration of the circuit can be improved. With this method, rectangular areas 17P and 17N
Is extended, for example, in FIG. 4 (A) and FIG. 5 (A)
As is clear from comparison between FIG. 4B and FIG. 5B, the use efficiency of the first wiring layer is increased, which contributes to the improvement of the integration degree of the semiconductor integrated circuit.

In the first aspect of the present invention, for example, FIG.
One pair of power supply wirings 13P, 13N as shown in
Side inter-cell wiring channel 17P and a pair of power supply wirings 13
Inter-cell wiring channel 17N on the other 13N side of P and 13N
And 1 are defined as independent inter-cell wiring channels, and inter-cell rough wiring is performed to perform inter-cell wiring channel 1
Determine the number of wiring tracks in 7P and 17N.

In the second aspect of the present invention, for example, FIG.
One pair of power supply wirings 13P, 13N as shown in
Side inter-cell wiring channel 17P (FIG. 1 (A)) and inter-cell wiring channel 17N (FIG. 1 (A)) on the other side 13N of the pair of power supply wirings 13P and 13N are combined into one combined inter-cell wiring channel. 17, the rough wiring between cells is performed to determine the number of wiring tracks in the wiring channel 17 between combined cells.

Such a structure can be adopted depending on the wiring requirements of the block. In this case, the schematic wiring is shown in FIG.
It is easier than the case (A).

In the third aspect of the present invention, for example, FIG.
One pair of power supply wirings 13P, 13N as shown in
Power supply wirings 13P and 13N on the side opposite to the first inter-cell wiring channel 17P with the one power supply wiring 13P sandwiched therebetween.
The second inter-cell wiring channel in the rectangular area of the same wiring layer is secured, and the first inter-cell wiring channel 17P and the second inter-cell wiring channel are combined to form one inter-synthetic cell wiring channel 27P. The number of wiring tracks in the wiring channel 27P is made constant, the inter-cell rough wiring is divided into a first stage and a second stage, and in the first stage, it is determined which inter-cell wiring is to be passed through the inter-synthesis cell wiring channel 27P. In the second stage, the first inter-cell wiring channel 17P and the second inter-cell wiring channel are set as independent inter-cell wiring channels, and the inter-cell rough wiring is performed to make Determine the number of wiring tracks.

For inter-cell wiring within a relatively large block, inter-cell wiring channels 17P, 1P are provided as shown in FIG.
When 7N is taken, the general wiring becomes complicated. However, according to the third mode, the general wiring can be prevented from becoming complicated.

In the fourth aspect of the present invention, for example, FIG.
As shown in, in the detailed wiring, the coordinates in the direction parallel to the power supply wiring 13P connect the two points XA1 and XA2 to each other.
If the inter-cell wiring 50 and the second inter-cell wiring 51 connecting the two points of the coordinates XB1 and XB2 are in the inter-cell wiring channel and XA1> XB1 and XA2 <XB2, the first cell The inter-wiring 50 and the second inter-cell wiring 51 are wired so as not to intersect with each other.

In this structure, the number of second-layer wirings can be reduced as much as possible to improve the use efficiency of the first wiring layer.

In the fifth aspect of the present invention, as shown in FIG. 8, for example, after the detailed wiring, the power supply wirings 13N1 and 13N are formed.
Power supply wiring 1 in which two power supply wirings 13N1 and 13N2 of two standard cells adjacent to each other in the direction perpendicular to 2 have the same potential and are adjacent to each other
When there is no wiring in the same wiring layer as the power supply wirings 13N1 and 13N2 between the 3N1 and 13N2, the two standard power supply wirings 13N1 and 13N that are adjacent to each other by bringing adjacent standard cells close to each other.
N2 is unified and the width of the unified power supply wiring 13N is made smaller than the sum of the widths of the two power supply wirings 13N1 and 13N2 before integration.

In the case of this configuration, two power supply wirings 13N
1 and 13N2 are eliminated, and the width of the integrated power supply wiring 13N is two before the integration of the two power supply wirings 13N1 and 13N1.
Since it can be made smaller than the sum of the widths of N2, the degree of integration of the semiconductor integrated circuit can be improved.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

In FIGS. 1 and 3, the same components as those in FIG. 9 are designated by the same reference numerals.

In this embodiment, in FIG. 1, the high-potential-side power supply wiring 13P and the low-potential-side power supply wiring 13N can be moved in the cell column unit in the direction perpendicular to the longitudinal direction, that is, on the cell for inter-cell connection. The width of the inter-cell wiring channel through which the first layer wiring is passed is made variable, and this width is determined according to the result of the rough wiring. FIG. 1 shows three ways of forming the inter-cell wiring channel. Each inter-cell wiring channel is one wiring channel common to the cell column, and is roughly wired regardless of the wiring track.

In FIG. 1A, a variable width inter-cell wiring channel 1 is formed in the first layer wiring unused area on the P type diffusion area 11P.
7P, and a variable-width inter-cell wiring channel 17N is provided in the first layer wiring unused area on the N-type diffusion area 11N. In the inter-cell wiring channel 17P, wiring tracks T1P and T2P parallel to the longitudinal direction of the power supply wiring 13P are initially set. Similarly, in the inter-cell wiring channel 17N, a wiring track T parallel to the longitudinal direction of the power supply wiring 13N is provided.
1N and T2N are initialized.

In the general wiring, for each wiring channel, N first cell wirings for inter-cell connection in the range of N0-ΔN1≤N≤N0 + ΔN2 are passed irrespective of the wiring track. Here, N0 is in the inter-cell wiring channel 17P and 17 of the standard cell of the initial size before moving the power supply wiring.
The number of each wiring track in N, and in FIG.
0 = 2. ΔN1 and ΔN2 are values within the allowable range due to the characteristics of the MOS transistor, and for example, ΔN1
= 2 and ΔN2 = 1.

Depending on the wiring requirements in the block, FIG.
As in (B), one variable width inter-cell wiring channel 17 can be provided between the power supply wiring 13P and the power supply wiring 13N. The inter-cell wiring channel 17 is shown in FIG.
Similarly to the first layer wiring unused area, the wiring track T1P,
T2P, T1N and T2N are initialized.

In the rough wiring, N first layer wirings for inter-cell connection in the range of 2N0-2ΔN1 ≦ N ≦ 2N0 + 2ΔN2 are passed through the inter-cell wiring channel 17 independently of the wiring track, and the rough wiring is shown in FIG. It is easier than the case (A).

In the inter-cell wiring in a relatively large block, if the inter-cell wiring channels 17P and 17N are taken as shown in FIG. 1A, the general wiring becomes complicated. In such a case, as shown in FIG. 1C, an inter-cell wiring channel 27P having a fixed width extending over both sides of the power supply wiring 13P and an inter-cell wiring channel 27N having a fixed width extending over both sides of the power supply wiring 13N. And take.

The inter-cell wiring channel 27P is shown in FIG.
Of the variable-width inter-cell wiring channel 17P, which is the same as the inter-cell wiring channel 17P on the side opposite to the inter-cell wiring channel 17P with the power supply wiring 13P interposed therebetween. It includes an unused area of the first layer wiring. A wiring track T1P and a wiring track T2P are initialized in the former area, and a wiring track T4P and a wiring track T5P are initialized in the latter area.
Similarly, the inter-cell wiring channel 27N includes the same first-layer wiring unused area as the variable-width inter-cell wiring channel 17N of FIG. 1A, and the inter-cell wiring channel 17N sandwiches the power supply wiring 13N. Inter-cell wiring channel 17 on the other side
The first layer wiring unused area having the same width as N is included. In the former area, the wiring track T1N and the wiring track T2N are provided.
And are initialized, and the wiring track T4N is set in the latter area.
And the wiring track T5N are initialized.

In the first stage of the rough wiring, a fixed number C is set for each of the inter-cell wiring channels 27P and 27N, and in the case of FIG. 1C, four inter-cell connecting first layer wirings are unrelated to the wiring tracks. To determine which wiring is to be routed. In the second stage of the rough wiring, the inter-cell wiring channel 27P is divided into the inter-cell wiring channel 17P having a variable width shown in FIG. 1A and the inter-cell wiring channel in the remaining area, and using an appropriate evaluation function, N in the range of N0−ΔN1 ≦ N ≦ N0 + ΔN2 in the inter-cell wiring channel 17N
Through the first inter-cell connection first layer wiring, and C-N inter-cell connection first layer wiring through the other inter-cell wiring channel. The same applies to the inter-cell wiring channel 27N.

Next, the layout / wiring design procedure of the standard cell in which the inter-cell wiring channel as described above is set will be described with reference to FIG. This design is done by CAD in either manual or automatic mode. Note that which inter-cell wiring channel in FIGS. 1A to 1C is to be used is determined in advance for all cell columns or for each cell column based on experience, for example. Hereinafter, the numerical value in the parenthesis represents the step identification number in the figure.

(70) Based on the netlist, standard cells are arranged and rough wiring is performed. For example, in the case of using the standard cell of FIG. 1A, it is assumed that 0 to 3 wirings can be passed through the inter-cell wiring channels 17P and 17N, respectively, and the rough wiring is not specifically determined. I do.
At this time, optimization is performed by using an appropriate evaluation function. As a result, the number N of wirings that pass through the inter-cell wiring channels 17P, 17N or 17 is determined.

(71) Compare N0 with N after rough wiring. If N> N0, proceed to step 72, where N <
If N0, the process proceeds to step 73, and if N = N0, the process proceeds to step 74.

(72) For example, when the standard cell shown in FIG. 1C is used and N0 = 2 and N = 3, FIG.
, The power supply wiring 13P is moved to the outside of the cell in the direction perpendicular to the longitudinal direction thereof along with the contact 14P by the pitch p of the wiring track T3P, and the P-type diffusion region 11P is moved in this direction by the moving distance of the power supply wiring 13P. Extend by p and then extend the end of gate 12 by this distance p. Also in the inter-cell wiring channel 17N, if N = 3, the same processing as in the inter-cell wiring channel 17P is performed. In this way, the size of the standard cell is increased.
This size change is performed for each cell column and each inter-cell wiring channel. This size change generally corresponds to the first inter-cell wiring channels 17P and 17N as shown in FIG.
The unused area of the layer wiring may be extended in a direction perpendicular to the power wiring. Then, it proceeds to step 74.

(73) For example, when the standard cell shown in FIG. 1C is used and N0 = 2 and N = 1, the power supply wiring 1
3P is moved in the direction perpendicular to the longitudinal direction and inside the cell by the pitch p of the wiring track T3P together with the contact 14P, and the P-type diffusion region 11P is shortened in this direction by the moving distance p of the power supply wiring 13P. Then, the end of the gate 12 is shortened by this distance p. Inter-cell wiring channel 17
Even in N, if N = 1, the same processing as in the inter-cell wiring channel 17P is performed. In this way, the size of the standard cell is reduced and the useless first layer wiring region is narrowed, so that the degree of integration of the circuit can be improved. This size change is performed for each cell column and each inter-cell wiring channel. This size change is generally performed by shortening the unused area of the first layer wiring corresponding to the inter-cell wiring channels 17P and 17N as shown in FIG. 1A in the direction perpendicular to the power supply wiring.

(74) Detailed wiring is performed to determine which wiring is to be arranged on which wiring track. Since the range of N is limited as described above, the second layer wiring may be necessary even if the wiring method of this embodiment is used. Since the specific wiring route is not taken into consideration in the rough wiring, the number of the second layer wirings differs depending on the detailed wiring method. Therefore, the second
In order to reduce the number of layer wirings, processing shown in FIG. 7 described later is performed.

(75) Next, compaction is performed to compress the redundant portion of the pattern to improve the degree of integration.

In the compaction, the grid layout is converted into the gridless layout, and the spacing between the wirings of the same wiring layer having no contact in the periphery is made narrower than the pitch of the grid, which is close to the manual design, as will be concretely shown below. You can get the layout. Further, for example, as shown in FIG. 8A, when there is no wiring between the low potential side power supply wiring 13N1 and the low potential side power supply wiring 13N2 of two standard cells which are adjacent to each other in the direction perpendicular to the power supply wiring, The power supply wirings 13N1 and 13N2 are one power supply wiring 13N as shown in FIG. 8B. Since the width of the power supply wiring 13N can be made smaller than the sum of the width of the power supply wiring 13N1 and the width of the power supply wiring 13N2, the degree of integration can be increased. Even if the first-layer signal lines are partially present between the power supply wirings, this unification can be performed in a portion where the first-layer signal lines are not provided between the power supply wirings. In the figure, 13P1 and 13P2 are high potential side power supply wirings.

FIGS. 4 and 5 show the effects of the present embodiment wired as described above in comparison with the conventional example. In the drawing, the wiring with hatching is the second layer wiring, and the wiring without hatching is the first layer wiring.

FIG. 4B shows the on-cell wiring before the position of the power supply wiring 13P is changed, that is, the conventional on-cell wiring.
Shows the on-cell wiring after the processing of step 72 is performed to change the position of the power supply wiring 13P.

In FIG. 4B, inter-cell wiring 40 and 41.
Is laid in the first wiring layer because it is arranged inside the cell with respect to the power supply wiring 13P, but the connection between the inter-cell wiring 42L and the inter-cell wiring 42R cannot be performed inside the cell. It is arranged in a wiring layer and crosses over the power supply wiring 13P, one end of the inter-cell wiring 42L and one end of the inter-cell wiring 42U are connected by a contact 42A, and one end of the inter-cell wiring 42R and the other end of the inter-cell wiring 42U are connected. It is connected by the contact 42B.

On the other hand, in FIG. 4A, the power supply wiring 1
Since 3P is moved to the outside of the cell, the inter-cell wiring 42 can be arranged in the first wiring layer in place of the second layer wiring in FIG. 4B, whereby the use efficiency of the first wiring layer is improved. Contributes to the improvement of circuit integration.

While FIG. 4 shows one in-cell wiring, FIG. 5 shows wiring near two cells adjacent to each other in the direction perpendicular to the power supply wiring. FIG. 5B shows the power supply wiring 13P.
Before the position change, that is, the on-cell wiring of the conventional example is shown. In FIG.
The on-cell wiring after changing the position of P is shown.

The high potential side power supply wiring 23P is the power supply wiring 13
It is in a standard cell adjacent to the standard cell containing P. In FIG. 5B, the inter-cell wiring 40L and the inter-cell wiring 40R cross the power supply wiring 13P and are connected by the inter-cell wiring 40U and the contacts 40A and 40B, and the inter-cell wiring 41L and the inter-cell wiring 41R connect the power supply wiring 13P. The inter-cell wiring 41U and the contacts 41A and 41B are connected to each other, and the inter-cell wiring 42L and the inter-cell wiring 42R cross the power supply wiring 13P and the inter-cell wiring 42U and the contacts 42A and 42B.
Connected by. In addition, the inter-cell wiring 43L and the inter-cell wiring 43R cross the power supply wiring 23P and the inter-cell wiring 43L.
D, the contacts 43A and 43B, and the inter-cell wiring 44L and the inter-cell wiring 44R cross the power supply wiring 23P and are connected by the inter-cell wiring 44D and the contacts 44A and 44B.

On the other hand, in FIG. 5A, the inter-cell wirings 40, 41 and 42 can be arranged in the first wiring layer by moving the power supply wiring 13P. Inter-cell wiring 44L and 44R
Is in the second wiring layer, the use efficiency of the first wiring layer is not deteriorated even when the power wirings 23P and 13P are crossed.

The wiring within the width HB from the power supply wiring 13P to the power supply wiring 23P in FIG. 5B corresponds to the wiring within the width HA in FIG. 5A and HA <HB. This increases the use efficiency of the first wiring layer and contributes to the improvement of the degree of integration.

FIGS. 4 and 5 show an example in which the use efficiency of the first wiring layer is improved by changing the position of the power supply wiring, but even if the position of the power supply wiring is the same, it depends on the wiring method. In some cases, the use efficiency of the first wiring layer can be improved. FIG. 6 shows such a case. Although the number of second layer wirings is two in FIG. 6A for performing the same wiring, the number of second layer wirings is three in FIG. 6B. It is a book. Inter-cell wiring 5 without hatching in the figure
0, 50L, 51, 51U and 52U are first layer wirings, and hatched inter-cell wirings 50R, 51L, 5
1R, 52L and 52R are second layer wirings.

Generally, when the X-coordinate is connected between the two points XA1 and XA2, the two points XB1 and XB2 are connected, and the two points XC1 and XC2 are connected, the number of second layer wirings is as large as possible. A method of reducing the use efficiency of the first wiring layer is shown in FIG. This method is used in step 74 above.

(80) (XA1-XB1) (XA2-X
The value of B2) is set to JAB, and (XB1-XC1) (XB2
The value of -XC2) is JBCB, and (XC1-XA1)
The value of (XC2-XA2) is JCA.

(81) Depending on the negative numbers 3 to 0 of JAB, JBC, and JCA, one of the following steps 82 to 85 is performed to reduce the number of wiring crossings as much as possible.

(82) When the negative number is 3, the mutual intersection of the three wirings is set to 0 as shown in the figure.

(83) When the negative number is 2, for example, JA
When B and JCA are negative and JBC is positive, the wiring between XA1 and XA2 and the wiring between XB1 and XB2 are laid without crossing each other as shown in the figure, and the wiring between XC1 and XC2 is XB1 and XB2. Intersect only the wiring between them once. In this case, since the wiring from XC2 becomes the second layer wiring, even if this wiring crosses the power supply wiring 13P as shown in FIG. 6A, the use efficiency of the first wiring layer does not decrease.

(84) When the negative number is 1, for example, JA
When B is negative and JBC and JCA are positive, the wiring between XA1 and XA2 and the wiring between XB1 and XB2 are laid without crossing each other as shown in the drawing, and the wiring between XC1 and XC2 is XB1 and XB2. Intersect only the wiring between them once. In this case, since the wiring from XC1 becomes the second layer wiring, the use efficiency of the first wiring layer does not decrease even if this wiring crosses the power supply wiring 13P of FIG. 6 (A).

(85) When the negative number is 0, for example, as shown in the figure, the wiring between XB1 and XB2 and XA1 and XA2
The wiring between them is laid by crossing each other once, and XB1, XB
The wiring between B2 and the wiring between XC1 and XC2 are laid so as to intersect each other once. In this case, since the wiring from XA2 and XC1 is the second layer wiring, this wiring is shown in FIG.
Even if the power wiring 13P is crossed, the use efficiency of the first wiring layer does not decrease.

[0057]

As described above, according to the cell-based layout design method of the present invention, the use efficiency of the first wiring layer, which is the same wiring layer as the power supply wiring of the standard cell, is improved,
It has an excellent effect that the semiconductor integrated circuit can be highly integrated.

The configuration of the second aspect of the present invention can be adopted depending on the wiring requirement of the block, and in this case, there is an effect that the schematic wiring becomes simple.

In the inter-cell wiring in a relatively large block, if the inter-cell wiring channel is taken as in the first mode, the general wiring becomes complicated. However, according to the third mode of the present invention, This has the effect of avoiding complication.

According to the fourth aspect of the present invention, in the detailed wiring, the number of second layer wirings can be reduced as much as possible, and the use efficiency of the first wiring layer can be improved.

According to the fifth aspect of the present invention, after the detailed wiring, there is no space between two adjacent power supply wirings, and
Since the width of the integrated power supply wiring is smaller than the sum of the widths of the two power supply wirings before being integrated, there is an effect that the degree of integration of the semiconductor integrated circuit can be increased.

[Brief description of drawings]

FIG. 1 is a standard cell pattern diagram showing how to take an inter-cell wiring channel through which a first layer wiring on a cell is passed.

FIG. 2 is a flowchart showing a standard cell layout / wiring design procedure.

FIG. 3 is a pattern diagram before and after changing a standard cell size.

FIG. 4 is a wiring pattern diagram showing on-cell wiring before and after changing the power supply wiring position.

FIG. 5 is a wiring pattern diagram showing on-cell wiring before and after changing the power supply wiring position.

FIG. 6 is a wiring pattern diagram showing an example in which the number of second layer wirings differs depending on the method of wiring on the cell.

FIG. 7 is a flowchart showing a method for reducing the number of second layer wirings.

FIG. 8 is a pattern diagram showing a single power supply wiring by compaction.

FIG. 9 is a conventional standard cell pattern diagram.

[Explanation of symbols]

10, 20 Cell frame 11P P-type diffusion region 11N N-type diffusion region 12 Gate 13P, 13P1, 13P2 High-potential-side power supply wiring 13N, 13N1, 13N2 Low-potential-side power supply wiring 14P, 14N, 16P, 16N, 40A, 40B, 4
1A, 41B, 42A, 42B, 43A, 43B, 44
A, 44B, 51A, 51B, 50B, 52A, 52B
Contact 15 Intra-cell wiring 17P, 17N, 17, 27P, 27N Inter-cell wiring channel T1P to T5P, T1N to T5N Wiring track 40 to 42, 50 to 52, 40L, 41L, 42L, 4L
3L, 44L, 40R, 41R, 42R, 43R, 44
R, 40U, 41U, 42U, 43D, 44D, 50
L, 50R, 51R, 51L, 51U, 52R, 52
L, 52U inter-cell wiring

Claims (6)

[Claims] 1. A semiconductor integrated circuit in which standard cells including a pair of parallel power supply wirings (13P, 13N), which are registered in advance, are arranged, and between the standard cells are roughly wired, and then the rough wiring is made into a detailed wiring. In a cell-based layout design method for designing a circuit layout, there is no inter-element wiring in the standard cell in the same wiring layer as the power wiring between the pair of power wirings of the standard cell. A rectangular area that traverses in parallel is made flexible in a direction perpendicular to the power supply wiring within a predetermined range, and the rectangular area of the wiring layer is defined as an inter-cell wiring channel (17P, 17N), and in the inter-cell wiring channel, The wiring tracks (T1P, T2P, T1N, T2N) in the direction parallel to the power supply wiring are passed, and the number of the wiring tracks is made variable within a predetermined range determined by the expansion / contraction range. A cell is characterized in that rough wiring between cells is performed on a channel to determine the number of wiring tracks in the inter-cell wiring channel, and the rectangular area of the standard cell is expanded or contracted based on the determined number of wiring tracks. Base layout design method. 2. A pair of the power supply wirings (13P, 13N)
The inter-cell wiring channel (17P) on one side and the inter-cell wiring channel (17 on the other side of the pair of power supply wirings
2. The cell-based layout according to claim 1, wherein N) and N) are defined as independent inter-cell wiring channels, and the inter-cell rough wiring is performed to determine the number of wiring tracks in the inter-cell wiring channel. Design method. 3. A pair of the power supply wirings (13P, 13N)
The inter-cell wiring channel (17P) on one side and the inter-cell wiring channel (17 on the other side of the pair of power supply wirings
N) and one synthetic inter-cell wiring channel (1
7. The cell-based layout design method according to claim 1, wherein, as 7), the rough wiring between cells is performed to determine the number of wiring tracks in the combined inter-cell wiring channel. 4. A pair of the power supply wirings (13P, 13N)
The first inter-cell wiring channel (17P) on one side is further sandwiched by the one power supply wiring (13P).
On the side opposite to the inter-cell wiring channel, a second inter-cell wiring channel in a rectangular area in the same wiring layer as the power supply wiring is secured, and the first inter-cell wiring channel and the second inter-cell wiring channel are combined to form 1 As one combined inter-cell wiring channel (27), the number of wiring tracks in the combined inter-cell wiring channel is made constant, and the inter-cell general wiring is divided into a first stage and a second stage. It is determined whether a wiring is to be passed through the composite inter-cell wiring channel, and in the second stage, the first inter-cell wiring channel and the second inter-cell wiring channel are set as independent inter-cell wiring channels. 2. The cell-based layout design method according to claim 1, wherein the number of wiring tracks in the first inter-cell wiring channel is determined by performing general wiring between the cells. 5. In the detailed wiring, a first inter-cell wiring connecting two points having coordinates XA1 and XA2 in a direction parallel to the power supply wiring (13P) and the coordinates XB1 and XB.
The second inter-cell wiring that connects the two points of 2 exists in the inter-cell wiring channel (17P), and XA1> XB1 and X
When A2 <XB2, the first inter-cell wiring and the second inter-cell wiring
5. The cell-based layout design method according to claim 1, wherein wiring is performed so that inter-cell wiring does not intersect with each other. 6. After the detailed wiring, the adjacent power supply wires of two standard cells adjacent in the direction perpendicular to the power supply wire (13P) have the same potential and the power supply wire is between the adjacent power supply wires. When there is no wiring in the same wiring layer, the standard cells adjacent to each other are brought close to each other to integrate two adjacent power supply wires, and the width of the integrated power supply wire is
6. The cell-based layout designing method according to claim 1, wherein the width is smaller than the sum of the widths of the two power supply wirings before being integrated.