JPH0685049A - Manufacture of semiconductor device including groove-filling-process - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing semiconductors with shorter manufacturing time, higher productivity and higher reliability, while the portion to be removed is evenly removed, relating to the manufacture of semiconductor devices which includes the process for filling the groove in a base body through depositing means that performs etching and depositing at the same time. CONSTITUTION:Relating to the semiconductor device manufacturing method that includes the process of filling grooves 21-23 formed in a base body, by a depositing means in which etching and depositing are made at the same time, after the grooves 21-23 are filled, the depositing means is performed under the condition that etching horizontally progresses as required, and then a film 4 whose side wall is etched faster than others is formed, in an intention that filling materials 34-36 formed on the position other than portions to be filled are removed. And then, with the film used as a mask 4', filling materials 34'-36' to be removed are partially removed, and the remains are removed by grinding. All these processes are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a step of filling a groove. INDUSTRIAL APPLICABILITY The present invention can be used as a method for manufacturing various semiconductor devices that require a step of filling a trench to form a trench isolation, a trench capacitor, a buried plug (buried contact) of a groove, and other structures.

[0002]

2. Description of the Related Art With the miniaturization and high integration of semiconductor devices such as semiconductor integrated circuits, the element-to-element isolation method has replaced the conventional LOCOS method, which has a large dimensional conversion difference. For example, the shallow trench method is about to be used, and its practical application is an important issue.

In order to form such groove-type element isolation with good performance, a technique capable of satisfactorily filling grooves of various shapes is required. To this end, a deposition technique (bias ECR-CVD) in which etching and deposition are performed simultaneously is performed.
Method is typical) can be preferably used. Bias E
The CR-CVD method can form high-density plasma at low pressure, can achieve high-speed growth at low temperature, and by applying an RF bias to a substrate such as a semiconductor wafer, not only deposition but also simultaneous etching can be performed. Therefore, it is possible to satisfactorily embed a miniaturized trench (groove),
It can be said that this technology is indispensable for embedding fine grooves.

However, this technique has the following problems. That is, when the grooves 2a to 2c are filled by making use of the above-mentioned advantages, as shown in FIG. 2, the deposited shape to be formed is dependent on the underlying pattern. As shown in FIG. 2, on the large area A of the substrate 1 such as the Si substrate, the extra burying material 31 (SiO ₂ or the like) to be removed except the burying portion remains thick. This is because this method generally uses sputter etching of Ar ions for flattening, and the sputter etching has an angle dependence of the etching rate. Therefore, at the horizontal portion, the deposition rate> the etching rate. This is because

Therefore, it is necessary to remove the extra embedding material 31 formed outside the embedding portion. At least, to some extent, a margin for mask alignment is provided around the groove 2a, and therefore some removal is indispensable. In response to this request, the present inventor has invented a method of securing a margin for resist alignment by using so-called horizontal return etching, and then etching and removing an extra filling material (SiO ₂ etc.) to be removed. The horizontal return means that the deposition is performed under the condition that etching progresses in the horizontal direction (horizontal direction in the figure) and neither etching nor deposition progresses in the vertical direction (vertical direction in the figure).
1 is a technique for partially removing 1 (see Japanese Patent Application No. 1-277929 by the present applicant).

However, this horizontal return method requires a certain amount of time because of mask alignment for removing the extra filling material 31 over a wide area, and thus has a problem of poor production efficiency.

[0007] Therefore, the present applicant solves the above-mentioned problems and, even if an excessive burying material to be removed remains on a large area, provides a technique for removing the burying material promptly. As a manufacturing method capable of shortening the manufacturing time and obtaining a semiconductor device with high productivity when manufacturing a semiconductor device including a step of filling a groove on a substrate with a deposition means that is performed simultaneously, a bias ECR-
After filling the groove by using the CVD technique, a technique of removing an excessive filling material to be removed by polishing has been proposed (Japanese Patent Application No. 3-89573). However, the technique of simply removing an excessive portion by polishing has a problem in that polishing is pattern-dependent and uniform polishing cannot be removed. That is, as shown in FIG. 4, the stopper layer 43 for polishing is used.
When the narrow substrate convex region B having a and 43b (the material 35 'to be removed is above this) and the large embedded region C are adjacent to each other, the polishing rate of the stopper layer 43b of the narrow substrate convex region B is The polishing rate is higher than the polishing rate of the stopper layer 43a in the wide substrate convex portion area A (the material 36 'to be removed is present thereon). Therefore, a difference appears in the polishing rate between the adjacent embedded regions C and D, and as a result, for example, as shown by E in the figure, the embedded region C is polished more, resulting in a difference in flatness and surface flatness. There was a problem that was uneven.

[0008]

It is an object of the present invention to solve the above problems and to reduce the manufacturing time when manufacturing a semiconductor device including a step of filling a groove on a substrate with a deposition means for simultaneously performing etching and deposition. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can be shortened to obtain a semiconductor device with high productivity and which can uniformly remove an extra filling material to be removed.

[0009]

The invention according to claim 1 of the present application provides a method of manufacturing a semiconductor device, which comprises a step of filling a groove formed on a substrate by a deposition means for simultaneously performing etching and deposition. After filling the groove,
A step of forming a film having a high etching rate on the side wall and using this film as a mask to partially remove the filling material to be removed formed in the portion other than the filling portion, and the remaining portion of the filling material to be removed A method of manufacturing a semiconductor device having a step of filling a groove, the method including a step of removing by polishing, which achieves the above object.

According to the invention of claim 2 of the present application, the depositing means is carried out under the condition that the etching progresses in the horizontal direction to partially remove the filling material formed in the portion other than the filling portion, and thereafter. A method of manufacturing a semiconductor device having a step of burying a groove according to claim 1, wherein the step of removing the remaining portion of the burying material to be removed is carried out by polishing, and the above object is achieved thereby.

The structure of the present invention will be briefly described below with reference to the example of FIG. 1 showing an embodiment which will be described later in detail. As illustrated in FIG. 1B, the grooves 21 to 23 formed on the substrate 1 such as a semiconductor substrate are embedded by a deposition unit that simultaneously performs etching and deposition as illustrated in FIG. After burying the grooves 21 to 23, the depositing means is performed under the condition that the etching proceeds in the horizontal direction to partially remove the burying materials 34 to 36 formed in the portions other than the burying portion. With the structure illustrated in FIG. 1C (the portions exposed by the removal at this time are shown by reference numerals 10a to 10e. This step may be omitted), the film 4 having a high etching rate on the sidewall is formed thereafter. 1 (d), the filling material 34 'to be removed is formed by using the film 4 as a mask (see FIG. 1).
1 (d)) to obtain the structure illustrated in FIG. 1E, and the remaining portion to be removed is removed by polishing.
(G) is provided with the step of forming the structure.

The film 4 having a high etching rate on the side wall means
A side wall, for example, a portion 41 indicated by a broken line shown in FIG. 1D is easily etched away, and is, for example, a P-SiN (plasma silicon nitride) film, a P-SiN film.
A SiO film, a P-SiON film, and a P-PSG film are preferable,
Moreover, P-BPSG and P-BSG can also be used. Since these have a rough film quality, for example, in the case of wet etching, only the side wall portion to which the etching liquid is attached is easily removed by etching.

[0013]

According to the present invention, the horizontal return as shown in FIG. 1 (c) is performed for a very short time, or even if this step is omitted, the side wall shown in FIG. 1 (d) (e) is removed. Of the extra filling material other than the filling portions 31 to 33, for example, the filling material 35 on a narrow region (35 ′ in FIG. 1 (c) and thereafter) by the etching using the film 4 having a high etching rate as a mask.
Are easily removed (see FIGS. 1 (d) and (e)), and are then removed by polishing, which is a portion to be removed, for example, on a large area corresponding to reference numerals 34 and 36 in FIG. 1 (b). Embedded material is removed. As a result, the embedding material on the narrow area is pre-removed and the removal by polishing is only for the remaining embedding material on the large area,
The pattern dependence of polishing is eliminated. Therefore, the time-consuming horizontal return can be made small or can be omitted, so that the process time can be shortened, the manufacturing time can be shortened, and the highly efficient and highly productive semiconductor device can be manufactured without pattern dependence and reliability. It can be realized with a high method.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. However, as a matter of course, the present invention is not limited to the examples described below.

Example 1 This example is for manufacturing a miniaturized and integrated semiconductor device such as a VLSI device, in which trenches having active regions with different widths are buried and planarized by using a bias ECR-CVD method. The present invention is applied to the case where the method includes the step of performing the above to form the trench isolation.

In this embodiment, the substrate 1 which is a silicon substrate
(Etching stopper layer 41 such as polysilicon film,
And a SiO ₂ film which will serve as an etching stopper layer 42 when the polysilicon film is removed. The stopper layer 41 serves as an etching stopper layer when removing the embedded material portion to be removed, and also serves as a stopper layer when removing by polishing.) A trench pattern is formed on the stopper layer 41 to form the grooves 21 to 23. Having FIG. 1
The structure of (a) is obtained. For patterning, a photolithography technique using a normal resist process and a silicon etching technique can be used. At this time, a wide area A and a narrow area B are formed in the active area.

Next, using bias ECR-CVD,
The grooves 21 to 23 are embedded and flattened. For example, deposition is performed under the following conditions and SiO ₂ is embedded. Gas system used: SiH ₄ / N ₂ O = 20/35 SCCM Pressure: 7 × 10 ⁻⁴ Torr RF bias: 500 W Microwave: 800 W As a result, the structure of FIG. 1B is obtained. The filling material (SiO _{2 in} this example) embedded in the grooves 21 to 23 is indicated by reference numerals 31 to 33, and the extra filling material deposited on the portion other than the embedded portion is indicated by reference numerals 34 to 36.

Next, if necessary, horizontal return is performed. As a result, the structure shown in FIG. As shown in the figure, an extra filling material (here, SiO ₂ ) 34 to be removed is used.
36 is partially removed. The exposed part is denoted by 10a to 10
Although indicated by e, this may be a very small portion, and may be a small amount that is not necessary as much as a mask alignment margin (in the figure, it is exaggerated for clarity). The conditions for horizontal return at this time can be set as follows, for example. Used gas system: SiH ₄ / N ₂ O = 7.5 / 35SCC
M Pressure: 7 × 10 ⁻⁴ Torr Microwave: 800W RF bias: 500W

Next, the film 4 having a high etching rate on the side wall is formed.
To form. Here, SiO ₂ which is a filling material and P-SiN which is a material having an etching rate ratio can be used for CVD.
Then, this film 4 was obtained. The formation of P-SiN by CVD may be performed under normal conditions, for example, the following conditions can be adopted. Gas system used: SiH ₄ / NH ₃ / N ₂ = 180/50
0/720 SCCM Pressure: 0.3 Torr Temperature: 250 ° C. RF application: 900 W (380 KH _Z ) Electrode gap: 5 cm At this time, the quality of P-SiN attached to the SiO ₂ side wall, which is the extra filling material 34 ′, becomes rough. There is. Although the mechanism by which the film quality of the portion becomes rough is not always clear, as shown in FIG.
The portion corresponding to the side wall of No. 4 is not irradiated with the ions I, so that the film is not densified, whereas the other regions are irradiated with ions accelerated by the energy of the sheath or the plasma potential and the film is densified. It is presumed that this is due to In addition, as a technique utilizing such a property that the etching rate of the step portion is higher than that of other portions, “Nikkei Electronics”, Nikkei McGraw-Hill 1982 Mar.
There is one described on pages 93 to 94 of the 29th issue of the month, 10
The original document is cited on page 0. Therefore, by utilizing this property, the side wall portion indicated by reference numeral 41 in FIG. 1D is removed by diluted HF or the like.

Next, the film 4 (P-
Using the SiN film) as a mask 4 ', excess filling material is partially removed. That is, here, SiO ₂ typified by a portion indicated by reference numeral 35 ′ formed on the narrow region is removed. For example, when etching with dilute HF, SiN
Since the selection ratio of SiO ₂ and SiO ₂ is about 10, the structure shown in FIG. 1E is obtained by this etching. In the figure, reference numeral 10 indicates a removed portion. In this way, all the surplus SiO ₂ on the narrow region can be removed, so that the problem of pattern dependence due to the existence of the wide region and the narrow region is eliminated in the next polishing process.

Next, P-S which forms the film 4 is made of phosphoric acid or the like.
iN is removed to obtain the structure shown in FIG.

Next, the remaining SiO ₂ corresponding to the reference numerals 34 and 36 in FIG. 1B is removed by polishing. The polishing conditions at this time were: pressure 7 psi, carrier rotation speed 3
The rotation speed was 5 rpm and the platen rotation speed was 17 rpm. The polishing liquid (slurry) used during polishing is trade name SC-1
(Manufactured by CABOT COORATION) was used. Its solid component is silica (30% of total weight) (pH: 10.5-10.7, silica particle size: 25-35).
nm, pH adjuster: KOH). This SC-1 was diluted 15-20 times with deionized water and diluted with diluted hydrochloric acid or KOH, Na.
The pH was controlled using an OH solution before use. By this polishing, the structure shown in FIG. 1D was obtained.

Further, the stopper layers 41 and 42 are made of Si.
The O ₂ / poly Si structures 41, 42 are removed. As a result, as shown in FIG. 1H, the embedded portions 3 of the grooves 21, 22 are
A structure in which 1 and 32 are slightly projected from the substrate 1 and have good pressure resistance as element isolation can be obtained.

According to this embodiment, after the trenches 21 to 23 are filled, the film 4 is formed on the trenches 21 to 23, and only the portion of the film 4 attached to the side wall of SiO ₂ which is the extra filling material 34 ′ to 36 ′ is attached. Is selectively removed, and excess SiO _{2 is used} as a mask.
Since all or part of the
By the VD method, a mask for removing an extra burying material portion (SiO ₂ ) can be formed, so that it is possible to eliminate (or shorten) the horizontal return, and the subsequent polishing also has a problem of pattern dependence. Therefore, uniform polishing removal can be realized.

Second Embodiment This embodiment is a modification of the first embodiment. Until the structure of FIG. 1C is obtained, the same process as in Example 1 is performed. However, in FIG.
Continue horizontal return to obtain the structure of (c), and
The extra embedding material indicated by 35 'in (c) is also removed by this horizontal return. That is, the extra filling material 35 on the narrow region in FIG. 1B is removed by horizontal return. The operating conditions were the same as those shown in Example 1.

After that, a P-SiN film is formed as the film 4 having a high etching rate on the side wall similarly to the first embodiment, and an excessive filling material, that is, the reference numeral of FIG. The sidewalls of the portions corresponding to the material portions indicated by 34 and 36 were removed by etching, and the remaining portions were removed by polishing. The specific method was the same as in Example 1. Also in this embodiment, the process time can be shortened, and the excess filling material on the narrow region is removed by horizontal return in advance before the polishing process, so that polishing can be performed without pattern dependence in the polishing process. Becomes

[0027]

According to the present invention, when a semiconductor device is manufactured with a step of filling a groove on a substrate with a deposition means for simultaneously performing etching and deposition, the manufacturing time is shortened and the productivity is improved. It is possible to uniformly remove the expensive and extra portions, and thus the semiconductor device can be obtained by a highly reliable process.

[Brief description of drawings]

1A to 1C are sectional views showing steps of Example 1 in order.

FIG. 2 is a diagram showing a problem.

FIG. 3 is an operation explanatory view.

FIG. 4 is a diagram showing pattern dependence of polishing.

[Explanation of symbols]

1 Substrate 21-23 Groove 34-36, 34'-36 ', 34 "Filling Material to be Removed 4 Film with High Sidewall Etching Rate 4'Mask

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[Procedure amendment]

[Submission date] August 26, 1993

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device, comprising a step of filling a groove formed on a substrate by a deposition means that simultaneously performs etching and deposition, wherein a sidewall has a high etching rate after the groove is filled. Forming a film, and using this film as a mask, a step of partially removing the embedding material to be removed formed in a portion other than the embedding portion and a step of removing the remaining portion of the embedding material to be removed by polishing A method for manufacturing a semiconductor device, comprising a step of filling a groove, which comprises: 2. After burying the groove, the depositing means is performed under the condition that the etching proceeds in the horizontal direction to partially remove the burying material to be removed formed in a portion other than the burying portion. 2. The method for manufacturing a semiconductor device having a groove filling step according to claim 1, wherein the step of removing the remaining portion of the filling material to be removed is performed by polishing.