JPH0683697A - Information processor - Google Patents

Abstract

PURPOSE:To unnecessitate jumper setting at the time of expanding memory capacity by detecting the memory capacity of a memory block by a program, writing to a latch circuit by a central processing circuit corresponding to a detected result and appropriately setting latch signals to a memory decoder. CONSTITUTION:A latch 104 latches optional data by writing to a specific address from the central processing circuit 101 and supplies the latches A112 and B113 to the memory decoder 102. In this case, the latch 104 is constituted so that the latches A112 and B113 are both '1' when a power is supplied. Also, the prescribed data are written in the address, the contents are read and compared with the written data and when they are coincident, the address is mounted with a memory. That is, the memory module of 16 megabytes is mounted to the memory block B106. Further, the other addresses are checked and when they are OK, the memory module of 16 megabytes is also mounted in the memory block A105.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device whose memory capacity can be changed.

[0002]

2. Description of the Related Art In recent years, the performance of an information processing apparatus for processing various data has been remarkably improved, which is due to the improvement of the performance of a central processing unit and the storage capacity of a semiconductor memory. In particular, the storage capacity of semiconductor memories has been remarkably improved in recent years. For this reason, in information processing apparatuses such as workstations, in many cases, means for expanding the memory is adopted in order to extend the product life. Specifically, each of the memory blocks can be replaced as an independent memory module. The memory module here is one in which only one block of semiconductor memory is mounted on a printed wiring board, and is connected to an information processing device without a memory through a connector. This is because when a semiconductor memory having an increased memory capacity is supplied to the market in the future, the module can be replaced for the purpose of expanding the memory.

A conventional information processing apparatus will be described below. FIG. 4 is a block diagram of a conventional information processing device, and the memory module is a dynamic RAM (hereinafter referred to as DRAM).
It is assumed to be composed of.

In FIG. 4, 101 is a central processing circuit, 1
Reference numeral 03 is a timing for outputting the RAS timing signal 116 and the CAS timing signal 117 necessary for DRAM access from the address confirmation signal 110 output from the central processing circuit 101 indicating that the upper address signal 109 and the address signal 107 are confirmed. It is a generator. Reference numerals 301 and 302 denote jumpers A and B, which are set according to the capacities of the memory modules mounted in the respective memory blocks, and output the latches A112 and B113, respectively. Also, 10
Reference numeral 2 indicates 114R in synchronization with the RAS timing signal 116 from the upper address signal 109 output from the central processing circuit 101 and the states of the latch A 112 and the latch B 113.
ASA or 115RASB is further synchronized with CAS timing signal 117 to 114CASA or 115C
It is a memory decoder that selectively outputs ASB. 10
Reference numerals 5 and 106 denote a memory block A and a memory block B, each of which is composed of a memory module. 1
Reference numeral 08 is a data signal for exchanging data between the central processing circuit 101 and the memory block, and 111 is a WRITE signal indicating whether the operation state of the central processing circuit 101 is writing or reading.

Here, in this conventional example, four 4-megabit DRAMs, which are most supplied to the market, are mounted on the four chips.
It is possible to mount a megabyte DRAM module in each of the memory blocks, and to mount eight 16-megabit DRAMs that will be supplied to the market in the future.
It is assumed that the megabyte DRAM module has an accessible circuit configuration, and for simplification, only the case where a memory module exists in both two memory blocks will be considered.

[0006] In the information processing apparatus having the above components, the mutual relationship and operation of the components will be described with reference to the operation timing chart shown in FIG.

First, when reading from a memory block, the central processing circuit 101 outputs an address to be read as an address signal 107 and an upper address signal 109, and further an address decision signal 110 indicating that these addresses are decided. Is output. Next, the timing generator 103 which has received the address confirmation signal 110 generates the RAS timing signal 116 and the CAS timing signal 117 necessary for accessing the DRAM forming the memory block and supplies them to the memory decoder 102. The memory decoder 120 uses the upper address signal 109
Further, according to the input states of the latch A110 and the latch B113, the RAS timing signal 116 outputs the RSAA114 or RASB115, and the CAS timing signal 117 outputs the CASA114 or CASB115. The operation of the memory decoder 102 is shown in (Table 1).

[0008]

[Table 1]

A22, A23, A24 in (Table 1)
Represents the high-order address signal 109. In the first row of (Table 1), when both the latch A 112 and the latch B 113 are 0 and the high-order address signal 109 is all 0, RASA and CASA 114 are activated. (Active)
RASB, CASB 115 obtains an inactive (non-active) output. That is, the memory block A105 is accessed. Here, the central processing circuit 10
WRIT to indicate that the operation of 1 is a read
Since the E signal 111 remains inactive, the data signal 108 is output from the memory block A 105, and the central processing circuit 101 can input data. Here, the address input to the memory block is time-divided into a row address and a column address in the case of DRAM, but it is not included in FIG. 4 of the conventional example because it is not an issue of the present invention.

There are two types of memory modules installed in each memory block, 4 megabytes and 16 megabytes. To facilitate memory management in software, the memory block A105 and the memory block B106 are consecutive addresses. If so, there are four patterns as shown in FIG. Here, the lower address side is the memory block A105. Jumper A301 and jumper B3 to realize four memory configurations
It is necessary to input 02 to the memory decoder 102 via the latch A 112 and the latch B 113 by short-circuiting or non-shorting. For example, pattern 1 in FIG.
Requires the jumper A301 and the jumper B302 to be short-circuited to set both the latch A112 and the latch B113 to 0, and the pattern 2 short-circuits the jumper A301,
Set jumper B302 to non-short circuit and latch A112 to 0,
It is necessary to set the latch B113 to 1.

[0011]

However, in the above-mentioned conventional information processing apparatus, when the user who is using the pattern 1 in FIG. 6 mounts the memory module of 16 megabytes in order to expand the memory capacity, the jumper A301 is used. Unless the setting of the jumper B302 is changed, the purpose of memory expansion cannot be achieved. The same applies when the setting is incorrect.

An object of the present invention is to solve the above problems and an object thereof is to provide an information processing apparatus which does not require a jumper setting when expanding the memory capacity.

[0013]

In order to achieve the above object, the present invention shows a maximum memory configuration in an initial state, a latch circuit in which writing from a central processing circuit is possible, and an output is supplied to a memory decoder. And a program for detecting the memory capacity.

[0014]

The present invention has the above-mentioned structure,
When the power is turned on, the memory capacity of each memory block is detected by the program, and the central processing circuit writes the data in the latch circuit according to the detection result to appropriately set the latch signal supplied to the memory decoder.

[0015]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention.

In FIG. 1, reference numeral 104 denotes a latch, which latches arbitrary data by writing to a specific address from the central processing circuit 101 and supplies a latch A 112 and a latch B 113 to the memory decoder 102. Other configurations are the same as those in FIG. Here, memory block A
The memory block 105 and the memory block B106 are each configured as a module via a connector.

In this embodiment as well as the above-mentioned conventional example, it is possible to mount a 4-megabyte DRAM module having eight 4-megabit DRAMs, which are most supplied to the market, in each memory block and to supply it to the future market. It will also be possible to access a 16-megabyte DRAM module equipped with eight 16-megabit DRAMs that will be implemented. That is, the above two types of DRAM modules are used at the same timing, and the signals on the connector are made compatible. Here, the 16 megabyte DRAM module has one more address signal than the 4 megabyte DRAM module, but it goes without saying that the 16 megabyte DRAM module is matched with the 16 megabyte DRAM module on the connector. RASA, CASA11 for selecting a memory block
The input logic for outputting 4, RASB and CASB115 will be described later.

The operation timing of the information processing apparatus configured as described above is the same as that of FIG. 5 described in the conventional example.

Here, there are two types of memory modules installed in each memory block, 4 megabytes or 16 megabytes. To facilitate memory management in software, the memory block A105 and the memory block B106 are set as continuous addresses. If so, there are four combinations as shown in FIG. Here, it is assumed that the lower address side is the memory block A105 and the upper address side is the memory block B106. First, the central processing circuit 101
Determines one of the four patterns in FIG. 3 by a program, writes appropriate data in the latch 104, and sets the latch A112 and the latch B113 according to (Table 1). Here, the flow of the program will be described with reference to FIG. The latch 104 is configured so that both the latch A 112 and the latch B 113 are 1 when the information processing apparatus according to the present invention is powered on. That is, the memory decoder 10
2 decodes pattern 4 in FIG.
Here, the predetermined data is written in the address A of FIG. 3, the content of the address A is further read, and compared with the written data, and if the data is the same (OK), the address A has a memory, that is, the memory block B106. Is 16
This means that a megabyte memory module is installed. Further, the address B is checked by the comparison, and if OK, it means that the memory block A105 is also equipped with a 16-megabyte memory module.
That is, it can be seen that the memory configuration is pattern 4. Similarly, according to the flowchart of FIG. 2, pattern 1, pattern 2,
The memory configuration of pattern 3 can also be determined. Note that the abnormality referred to in FIG. 2 is a prohibited pattern, so it is necessary to give a warning to the user.

The memory configuration recognized by the program is latched by the latch A11 via the latch 104 in accordance with Table 1.
2, the latch B113 is supplied to the memory decoder 102.

As described above, according to this embodiment, it is not necessary to set jumpers or the like even when the memory configuration is changed.

[0022]

As is apparent from the above embodiments, according to the present invention, when the memory configuration is changed for the purpose of expanding the memory capacity or the like, it is possible to operate normally just by replacing the memory module. It is possible to provide an information processing device that eliminates labor and erroneous operation associated therewith.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a flow chart of a program in the device.

FIG. 3 is a memory configuration diagram of the device.

FIG. 4 is a block diagram showing a configuration of a conventional information processing device.

FIG. 5 is an operation timing chart of the information processing apparatus according to the present invention and the conventional example.

FIG. 6 is a memory configuration diagram in a conventional example.

[Explanation of symbols]

 101 central processing circuit 102 memory decoder 104 latch 105 memory block A 106 memory block B

Claims (1)

[Claims] 1. An information processing apparatus comprising a central processing circuit and a plurality of memory blocks, each of said memory blocks being capable of mounting a memory of a plurality of sizes, wherein writing from said central processing circuit is possible, and An information processing apparatus comprising: a latch circuit set at maximum configuration when power is turned on; and a memory decoder for determining an output according to an address signal of the latch circuit and the central processing circuit, and a program means for detecting a memory capacity.