JPH0683476A - Information processor - Google Patents

Abstract

PURPOSE:To easily vary the clock of the information processor by a program in an external storage device by writing the clock frequency of a CPU which is supplied from the external storage device in the storage means of the information processor and generating a clock corresponding to data in this storage means. CONSTITUTION:A CPU of 16MHz in maximum clock frequency is taken out of a CPU socket and replaced with a CPU of 20MHz in maximum clock frequency. The floppy disk attached to the purchased CPU of 20MHz in frequency is loaded in an FDD 309. The software which executes instructions for writing values corresponding to a 20MHz clock frequency in a CLK control part 303 is stored on the floppy disk. When a user turns ON the power source of the information process for booting through the FDD, the instructions for writing the values corresponding to the clock frequency in the CLK control part 303 are automatically executed to vary the clock frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device capable of changing a CPU clock frequency.

[0002]

2. Description of the Related Art Conventionally, as a method of changing a clock frequency (hereinafter referred to as CLK frequency) of a CPU in an information processing apparatus having a CPU, there is a method of setting a switch of the information processing apparatus or changing the CLK frequency by keyboard input. Was known. This is to maintain compatibility of software, and the other is to provide a mode for reducing the power consumption of the entire information processing apparatus.

Normally, the CLK frequency of the CPU can be set to a predetermined value of a few settings such as low speed, medium speed, high speed, etc., and the BIOS can know the setting. However, the application software stored in the external storage device cannot accurately recognize what the CLK frequency is. This is because the CPU mounted in the information processing device functions up as the device progresses, and since the CLK frequency of the future CPU is unknown, the C
This is because the function of notifying the CLK frequency of PU cannot be provided in the information processing device.

As a conventional example, the CL of the CPU 111 is shown in FIG.
An example of changing the K frequency has been shown. In this example, the CPU 11
The output of the oscillator that generates the CLK 102 corresponding to the maximum CLK frequency of 1 and the CLK 103 having a frequency lower than the maximum CLK frequency are switched.

In the example of FIG. 22, the maximum CLK frequency is 40.
FIG. 3 is a circuit block diagram for switching the CLK 110 of the CPU 111, which is 0 MHz, and shows the oscillation frequency 1 of the oscillator 101.
02 and the oscillating frequency 103 obtained by dividing the oscillating frequency 102 by 1/2 are selected by a CLK frequency switching signal 104 generated by the user operating a CLK changeover switch or the like and supplied as the CLK 110 of the CPU 111.

In addition to the example using the oscillator shown in FIG. 22, a PLL (phase-locked) for generating a fixed frequency by externally applying a signal to FIG.
CPU using a loop-type frequency synthesizer
An example of the CLK supply circuit is shown. Frequency synthesizer is IC
Since it is relatively easy to implement, ICs and the like that generate some arbitrarily set frequencies are commercially available. In this example, the frequency synthesizer IC 105 has a serial
The frequency of the CLK10 to be output is changed according to an arbitrary set value 107 which has an interface 106 and is given from the system. In the conventional example, an arbitrary set value given from the system is fixed as the system, and the signal 107 is generally generated only by the circuit. Therefore, as a result, the frequency of CLK10 is also fixed in the system.

Further, conventionally, as a means for upgrading the CPU of the information processing apparatus, it has been general to replace the entire CPU board on which a memory, a control IC and the like are mounted in addition to the CPU. Also, as a method of upgrading by replacing only the CPU, a method of changing the CLK frequency supplied from the outside to a predetermined frequency with a dip switch or the like, and an internal CLK
There has been known a method of exchanging the CPU with the frequency doubled to several times.

An example of changing the CLK frequency supplied from the outside to a predetermined frequency is shown in FIG. In this example, after the CPU 111 is replaced, a circuit example in which the CLK frequency corresponding to the CPU 111 is selected by the jumper 21 is shown. (Examples of 16 MHz, 25 MHz, and 33 MHz are shown.) Further, as another conventional example of CLK switching, a CPU
Japanese Patent Publication No. 12842/1992 discloses that the total power consumption of a microcomputer system is minimized by specifying the required clock pulse frequency. The invention disclosed in Japanese Examined Patent Publication No. 4-12842 is an invention focusing on that a frequency synthesizer generates a high-frequency CLK from a low-frequency CLK, and provides a CLK frequency necessary for executing a programmable task. When the task processing is completed, it is operated at a frequency lower than the maximum frequency to reduce power consumption.

However, since the invention disclosed in Japanese Patent Publication No. 4-12842 aims at constructing a system capable of operating with minimum power consumption, the CLK frequency of the CPU is changed based on the information from the external storage device. Features are not taken into account (because there is no reason to take them into account).
The invention disclosed in Japanese Examined Patent Publication No. 12842/1992 is effective for a limited system in which the CLK frequency can be finely controlled for each programmable task, but it is general-purpose as shown in the embodiments of the present invention. In an information processing device such as a personal computer, which is effective, it cannot be controlled finely by a program, and thus is not an effective means.
The biggest difference in the configuration between the invention disclosed in Japanese Patent Publication No. 4-12842 and the present invention is that the invention disclosed in Japanese Patent Publication No. 12842 is limited to a frequency synthesizer. Is that it can be realized without using a frequency synthesizer.

[0010]

The first problem is C
A case of upgrading the PU will be described. As described in the section of the related art, in the past, it was common to replace the entire CPU board. However, such a method has a problem that the CPU board needs to be redesigned and that the CPU board has to be made into a block so that the CPU board can be exchanged in advance so that it can be exchanged with a connector or the like. It was

In order to solve this problem, as described in the section of the prior art, a method of upgrading by replacing only the CPU has become common. As a method of exchanging only the CPU, a method of changing the CLK frequency supplied from the outside to a predetermined frequency with a dip switch or the like, and a method of exchanging the internal CLK frequency with a CPU whose frequency is doubled to several times are known. Was there.

First of all, there is a method of increasing the internal CLK frequency. However, since only the CPU corresponding to the frequency of the external CLK is targeted as the CPU to be upgraded, C
There is a problem that it cannot support CPUs with different LK frequencies and limits the upgrade range. Also, CPU
In the method of internally increasing the CLK frequency by 2 times, 3 times, etc., the CLK frequency cannot be changed from the outside in real time because the PLL method or the like is used as the technology.
Therefore, a large amount of current consumption is always wasted even if the CPU does little processing. CL when the CPU is not processing like a notebook computer
In the case of an information processing device having a function of extending the battery life by stopping or delaying K and upgrading the CPU, a device that does not have a function of switching the CLK frequency from the outside in real time is excluded. There are many problems in the method of increasing the CLK frequency inside the CPU from the viewpoint of power consumption.

Next, in the method of changing the frequency to a predetermined frequency with a dip switch or the like, it is necessary to mount a plurality of CLK oscillators or the like on the substrate in advance, and needless to know the corresponding frequency value in advance. was there. Therefore, in the traditional design, the user
When an information processing device having U is purchased, even if the CPU technology advances and a high-performance CPU that operates at a high frequency is created, if the operating frequency cannot be predicted in advance, there is no means to increase the frequency and the CPU is replaced. There was a problem that it was not possible to measure the function improvement. High-speed C that could not be developed when the user purchased the information processing device
It has become important from the viewpoint of effective use of resources that the user can upgrade his / her system by replacing the CPU when a PU (of course, the frequency when the user purchases it is unknown) is developed. A conventional system cannot have the above environment.

As a second problem, a problem seen from the application software side will be described. As described in the section of the related art, in the information processing device having the conventional CPU, the application software stored in the external storage device cannot control the CLK frequency of the CPU in the information processing device.

As the present day, the processing capability of the CPU is improved,
If the user interface of the corresponding application can sufficiently cope with the operation speed of the user, the higher the processing capacity of the CPU is, the better the application may not be. For example, an application corresponding to a notebook computer may want to give priority to the battery life over the information processing capability. Conventionally, the selection method is provided in the information processing device for each predetermined frequency, and the user operates the means.

In addition, in order to match the operation speed of the user in an application such as a game, the optimum CPU CLK frequency for each information processing device is described in the application software manual, etc.
I was changing the K frequency. However, with this, the CLK frequency must be manipulated for each application, which is bothersome and difficult. Especially MS-Windows
When a plurality of application programs such as s (registered trademark) and OS / 2 (registered trademark) can be operated at the same time, the user is forced to change CLK for each window or each program.

As described above, conventionally, there is a problem that it is difficult for the application side to provide an optimum user interface corresponding to each information processing device (corresponding to the CLK frequency of each CPU).

An object of the present invention is to solve the above problems, and when a user purchases an information processing device having a CPU, the processing power is higher than that of the CPU installed in the purchased information processing device. When upgrading to a CPU that operates with a high-frequency CLK, it is possible to provide a system capable of improving the function of the information processing device by simply replacing the CPU without purchasing the entire information processing device. It is an object. Another object is to provide a system in which application software stored in an external storage device can build an optimum user interface corresponding to each information processing device.

[0019]

An information processing apparatus of the present invention is an information processing apparatus capable of changing a CPU clock frequency, wherein data relating to the CPU clock frequency provided by an external storage device is stored in the information processing apparatus. It is characterized in that writing is performed in a specific storage means, a corresponding clock is generated based on the data in the storage means, and the conventional clock is replaced.

An operating system for managing a plurality of tasks executed on the information processing apparatus, a plurality of storage means for setting data on a clock frequency corresponding to at least the plurality of tasks, and an instruction of the operating system. And a clock generation circuit for generating a clock based on the data of the storage means selected by the selector.

The first CPU and the first CPU
Means for adding a second CPU operating at a different CLK frequency to the first CPU or having a means for exchanging the first CPU, and outputting a CLK corresponding to the CLK frequency of the second CPU And a means for generating a READY signal corresponding to the second CPU.

Further, the means for outputting the CLK corresponding to the CLK frequency of the second CPU is controlled by a reset signal or a signal generated by turning on / off the power supply.

Further, the means for outputting CLK corresponding to the CLK frequency of the second CPU has a frequency synthesizer for generating the first CLK given to the CPU based on the information from the external storage device, and The frequency synthesizer further includes CLK generating means for generating a second CLK different from the frequency synthesizer, and the first C is used when the CLK of the CPU is switched.
It has a means for switching between LK and the second CLK.

Further, the second CPU is connected to the first CP.
It is characterized by further comprising means for initializing a clock frequency to a detection signal indicating addition to U or replacement with the first CPU and an arbitrary frequency predetermined by the detection signal.

Further, the operating system of the information processing apparatus has means for selecting the clock frequency of the entire operating system in preference to the clock frequency of the task currently being executed.

[0026]

According to the configuration of the present invention, when the CPU originally mounted in the information processing apparatus is replaced with a high-performance CPU,
C that supports a high-performance CPU based on information in an external storage device
It is possible to generate LK and READY signals and switch CLK while preventing runaway of the device. Further, even if the CPU is not replaced, the CLK of the CPU can be changed by the application program of the external storage device, and it is possible to provide the operating environment suitable for the ability of the user.

[0027]

EXAMPLES The present invention will be described in detail below based on examples.

FIG. 1 is a block diagram of an information processing apparatus of the present invention. The information processing device includes a CPU unit 301, a memory,
CPU control unit 302, CLK control unit 303, L
A VIDEO circuit unit 304 for controlling the CD 305 and the CRT 306, a keyboard control unit 308 for controlling the keyboard 307, an FDD 309 and an IC card 310,
It has an I / O control circuit unit 311 for controlling an external storage device such as the HDD 313, and an expansion bus unit 312 for connecting another device or the like outside the information processing device.
First, the entire function of the present invention will be briefly described, and then detailed description will be given for each functional block.

In FIG. 2, the user selects C in the information processing device.
7 shows a flowchart from replacing the PU (here, the CLK frequency is 16 MHz) with a functionally upgraded CPU (here, the CLK frequency is 20 MHz) to setting the CLK frequency according to the CLK frequency of the CPU. Also, to the left of the flow chart, see how CLK frequency changes with each step.
The frequency change table is shown.

First, the user opens the back cover of the information processing device having a structure in which the CPU can be replaced,
A CPU with a maximum CLK frequency of 16 MHz is taken out from the CPU SOCKET 501 as shown in FIG. 4B and replaced with a CPU with a maximum CLK frequency of 20 MHz.

At this time, the frequency of CLK10 output from the CLK control unit 303 of FIG. 1 is the same as that of the CPU unit 301 of FIG.
In addition, it is necessary for the user to have a function to be initially set to the maximum CLK frequency of the built-in CPU when the user purchases the information processing apparatus (for example, 16 MHz->
16M to upgrade from 20MHz to> 25MHz
Initialize to Hz). This is, for example, CLK1 in FIG.
This is because if the frequency of 0 is set to 20 MHz and the CPU of 16 MHz is set in the information processing device, a runaway occurs from the beginning. (Step 401) Next, the floppy disk attached to the purchased 20 MHz CPU is loaded into the FDD (30 in FIG. 1) of the information processing apparatus.
(Corresponding to 9). This floppy disk stores software for executing an instruction to write a value corresponding to the CLK frequency (20 MHz in this case) to the CLK control unit 303 in FIG. CPU CLK in Figure 1
A detailed example of the control unit is shown in FIG. (Step 40
2) The user turns on the information processing apparatus and boots from the FDD. (Step 403) An instruction for writing a value corresponding to the CLK frequency of 20 MHz of the CPU in the information processing apparatus stored in the attached floppy disk to the CLK control unit 303 of FIG. 1 is automatically executed.

FIG. 3 shows a simple flowchart of a program for changing the CLK frequency.

First, to know the current CLK frequency,
0C, which is a register that stores the value of the CLK frequency
READ 12 (H). (Program step 41
0) Next, the current CLK frequency (16 MHz in this example) and the changed CLK frequency (25 MHz in this example) are displayed on the screen, and a message is output to the user as to whether or not to change the CLK. (Program Step 411) If NO, a message not to change will be displayed on the screen (Program Step 412), and if YES,
Write the value of the CLK frequency to be changed into 0C12 (H). (Program step 413) Next, a message that the CLK frequency has been changed is displayed on the screen, and a message instructing to tap the keyboard to reboot is output. (Program step 414) RESET P for reboot upon receiving keyboard input
Rebooting is performed by accessing 0F0 (H) which is the ORT, and the CLK frequency is changed to 25 MHz according to the value written in the program step 413.
(Program Step 415) As described above, the reason why the instruction shown in the program step 413 is to reboot without immediately changing the CLK frequency is
This is because when the CLK frequency is set by the PLL frequency synthesizer circuit as shown in FIGS. 23 and 10, if the CLK is switched immediately, the waveform may fluctuate and the CPU may run away. As a matter of course, the memory / CPU control unit 302 in FIG. 1 needs to have a function so as not to malfunction even if the CLK frequency changes. This can be realized by a ready signal control or the like described later.

(Steps 404 and 405) After restarting, the attached floppy disk for setting the CLK frequency is removed and the normal application disk is inserted to execute the application. If you want to boot from the hard disk, just remove the attached floppy disk. (Steps 406 and 407) In addition to the above steps, step 405 of FIG. 2 is omitted by the circuit configuration example shown in FIG.
It is also possible to move from step 4 to step 406. The circuit function shown in FIG. 15 will be described later. (Step 407) As described above, when the user purchases an information processing apparatus having a CPU, a high-frequency CLK having a higher processing capacity than the CPU mounted on the purchased information processing apparatus.
In the case of upgrading to a CPU that operates on the CPU, the information processing apparatus as shown in the block diagram of FIG. 1 can be upgraded by replacing the CPU according to the flowchart shown in FIG. 2 without purchasing the entire information processing apparatus. It becomes possible to plan. Further, each function described in the above example, that is, information stored in a floppy disk, an IC card, a hard disk, or a C
Function to change LK frequency, function to switch CLK frequency by RESET signal, READY
A function to operate the information processing device normally even if the CLK frequency fluctuates due to signal control or the like, and a CPU that was initially built in when the user purchased the information processing device by a signal indicating that the CPU was replaced. It can be seen that the function initially set to the maximum CLK frequency is necessary to upgrade the function without purchasing the entire information processing apparatus.

Next, detailed description will be given for each functional block.

First, the CPU section 301 in FIG. 1 is normally mounted on a substrate in a form as shown in FIGS. 4a and 4b.
In the configuration of FIG. 4a, the CPU 502 is directly mounted on the substrate without a socket. UPGRADE for later mounting the CPU 504 with improved functions
SOCKET 503 is also implemented at the same time. In the information processing apparatus of the present invention, the UPGRADE SOCKET 503 can be easily attached to the CP by opening the lid in advance so that the user who purchases the information processing apparatus can perform the function UP of the information processing apparatus by replacing the CPU.
It has a structure that allows U to be inserted.

FIG. 5 shows a circuit corresponding to FIG. 4a. Figure 5
CPU502 signal and UPGRADE SOCKE
The signals of T503 are mutually connected except for some signals. CPU504 is UPGRADE SOCKET5
When installed in the CPU 03, the CPU
Since the CHG signal 601 which is a signal connected to the GND terminal of 04 is connected to GND, the pull-up resistor 60
By 6, the signal which was "H" becomes "L". (The waveform is shown in FIG. 6 601).
Puts the output signal (702 in FIG. 6) in a high impedance state. By the above operation, the CPU bus signal 604 is
The output signal from the CPU 504 becomes valid instead of the signal from the CPU 502.

A signal CLR70 for initializing the frequency of CLK10 generated in response to the change of the CHG signal.
1, the CLK control unit 303 of FIG. 1 is initialized to an arbitrary predetermined frequency among the CLK frequencies corresponding to the information processing device. (The frequency to be initialized is usually determined so as not to affect the performance of the restart operation.) By the way, in order to reduce power consumption, the CHG signal 60 of FIG.
Although the method of putting the CPU 502 in the standby mode by 1 is generally used, CLK is supplied only to the CPU 504, and the CP
It is also possible to take a circuit configuration such as cutting the CLK signal of U502 or fixing it to the L level. A circuit example is shown in FIG. CHG signal 601 causes oscillators 1000, 10
By selecting the power supply of 01, the power consumption can be reduced to one CPU even if there are two CPUs.
Further, even if the oscillator 1000 that generates the CLK signal 1003 to be supplied to the CPU 502 when the CPU 504 is mounted is not turned off, the internal circuit of the CPU 504 does not operate even if the CLK signal 1003 is fixed to the L level, so that the current consumption is reduced. Can be lowered.

Next, the configuration of FIG. 4b is also a commonly used configuration. In this case as well, assuming that the CPU 502 of FIG. 5 does not exist, it is the same as that of FIG.
It can be known by the HG signal 601.

As a method of knowing the replacement of the CPU, it can be known by taking the configuration of FIG. 7 and the circuit system shown in FIG. As shown in FIG. 7, a photodiode 81 that produces an electromotive force by receiving light is mounted in the CPU socket. In FIG. 8, a photodiode 81 receives light and generates an electromotive force when the CPU is replaced. As a result, the transistor 91 is turned on, and the signal CHGCPU92 indicating that the CPU has been replaced changes from "H" to "L". The CHG CPU signal 92 is the CHG signal 60.
1 and the CLR 701 generated by this signal causes the CLK control unit 303 in FIG. 1 to be initially set to a predetermined arbitrary frequency among the CLK frequencies to be supported by the information processing apparatus.

As a second detailed description, the CLK control unit 303 in FIG. 1 will be described. 10 and 15 are shown as typical examples in which the user purchases the information processing apparatus, replaces the internal CPU, and changes the CLK thereof.

Similar to FIG. 23, FIG. 10 shows a method of changing the output frequency of the frequency synthesizer by giving external data to the frequency synthesizer. As a method of giving data from the outside, there are a method of using an external storage device such as a floppy disk, an IC card, a hard disk, and a method of allowing the user to change the CLK frequency by a setup menu in advance. Here, if it is possible to set 1 to 150 MHz or the like in a menu or the like so that the user can change it, it is easy to set carelessly and the CPU may run away and the information stored in the floppy disk etc. may be destroyed. is there.

Therefore, for safety, it is preferable to supply the setup program through an external storage device so that it is not easily set in the setup menu or the like. The program includes a BIOS RO in a flash ROM.
CP if you have a program to rewrite M (BIOSROM314, etc. in Figure 1) according to CLK frequency
A flexible environment by U exchange can be provided at the same time.

Hereinafter, description will be made with reference to FIGS. 10 to 14. Data for the CLK frequency of the corresponding CPU (fine setting data composed of several registers) is I
I / O WR of O instruction 0C00 (H) to 0C08 (H)
It is latched by the data latch circuit 1101 as the LAT signal 1100 which is the ITE command and output as data 1102 to the code generation circuit 1103. Code generation circuit 11
03 (generates a code corresponding to the corresponding CLK frequency from fine setting data) is a PW as shown in FIG.
It is latched by the LOAD signal 1104 which changes when the SW is turned on / off, and is output to the code conversion circuit 1106 as the corresponding code 1105. It should be noted here that the power supply of the data latch circuit 1101 is always backed up by a battery or the like. (The backup power supply is VBK1
It turns off the setting corresponding to the CLK frequency given by the LAT signal 1101).
This is to retain the data even at times and to initialize the data when the CPU is replaced. When the CPU is replaced, the CHG signal 601 shown in FIG. 5 is received by the transistor 1120 shown in FIG.
HGB1121 is output. As shown in FIG. 13, in response to the change of the signal CHGB1121, the CLR 701 which is an "L" pulse is input to the data latch circuit 1101 and reset to the initial data such that the CPU does not run away.

Corresponding code 1105 is counter data 110 corresponding to CLK in code conversion circuit section 1106.
Converted to 9 PROGRAMMABLE DIVIDE
It is input to the R unit 1110. As a result, the frequency of CLK10 is changed.

In the above example, after the user changes the CLK frequency according to the information stored in the floppy disk or the like, the CLK frequency must be changed by temporarily turning on / off the PWSW as shown in FIG.
(In order to generate the LOAD signal 1104) Then, as another example, by pressing the reset button, the LOAD signal 11
FIG. 14 shows an example in which 04 is generated and the CLK frequency is changed. Signal 1123 generated by RESET button
Causes the RESET signal 1122 to be generated. Further, a LOAD signal 1104 is also generated by the signal 1123 and data corresponding to the new CLK frequency is given to the code generation circuit 1103 in FIG. 10 to change the frequency of CLK10.

A period 11 sufficient for the frequency synthesizer circuit 1108 to lock the body RESET signal 1122.
By setting it to 24, the user can replace the CPU and change the CLK frequency without turning off the power again after changing the CLK frequency.
It becomes possible to reset to a new frequency by pressing the T button.

FIG. 15 shows an application example of the CLK frequency generation circuit by the frequency synthesizer 1108 shown in FIG. According to the configuration of this circuit example, after the user changes the CLK frequency according to the information stored in the floppy disk or the like, without performing the initialization processing of the information processing apparatus such as power on / off and RESET signal, Two
The process can proceed as in step 407 of the above.
Therefore, FIG. 16 showing the circuit of FIG. 15 and each signal waveform thereof
The function of changing CLK10 from 25 MHz to 50 MHz after CPU replacement will be described using. Figure 16 CLK1
0 is CL of 25MHz before switching CLK frequency
K is output. By the operation corresponding to step 404 in FIG. 2, the control circuit 1402 in FIG.
At timing 07, the frequency selection signal 1403 is set to "L".
To "H". CLK10 by signal 1503
Is switched by the selector 1406 in FIG. 15 from the frequency synthesizer circuit output 1404 to the oscillator output 16 MHz 1405.

Thereafter, the frequency synthesizer is set to 50 MHz.
1501 corresponding to the data is the data latch signal 1407
Latched by, the frequency synthesizer is 25MHz
To 50 MHz. Frequency selection signal 1
A period 1502 in which 403 is "H" corresponds to a period until the PLL circuit in the frequency synthesizer circuit locks to a new set frequency. At the timing 1508 when the frequency synthesizer becomes stable, the frequency selection signal 140
CLK10 is switched from the oscillator output 1405 to the frequency synthesizer circuit output 1404 by 3 and 50M
It becomes Hz.

CLK10 of FIG. 15 corresponds to the signal 14 of FIG.
Although it fluctuates like 04, if this is input to the CPU as it is, there is a possibility that the timing will not match at the time of memory access and a malfunction will occur. Therefore, by passing through the CLK switching circuit 1409 of FIG. 15, the bus hold signal 141 indicating the time of periodical memory refresh or the like.
0 switches the CLK1401 at a timing that does not affect the system operation and sets the CPU1 as the CLK10.
Supply to 1.

As a third detailed description, the memory / CP shown in FIG.
The U control unit 302 will be described. Even if the CPU is replaced, the entire system must functionally operate normally. A typical waveform of the memory / CPU control unit 302 is shown in FIG. C as the CPU frequency increases
The pulse width 1700 of LK becomes shorter.

As a result, the RAS pulse width of DRAM is 1
703, CAS pulse width 1702, etc., will not meet the DRAM standards. Therefore, according to the present invention, the memory / CPU control unit is provided with a circuit for receiving the counter data 1109 of FIG. 10 and the frequency selection signal (data) such as 1403 of FIG. Is characterized by.

IO for memory compatibility and compatibility with standard limits
By finely controlling the cycle time adjustment for each CLK frequency, it is possible to guarantee the normal operation when the CPU of the information processing device is replaced. Although it is well known that READY is controlled and weighted, the information processing apparatus of the present invention is novel in that the READY generating circuit is switched in accordance with the CLK frequency of the upgraded CPU. At first glance, it seems that the performance of this circuit does not change because the operating frequency of the peripheral circuits does not change even if the CLK frequency rises. However, this can be solved by incorporating CACHE in the CPU to improve the performance of the CPU itself without depending on the peripheral circuits. This circuit is also necessary when a CLK synchronous DRAM is used. It is always REA during random access and IO cycle
This is because it is necessary to control DY.

A circuit block diagram is shown in FIG. 18 as an embodiment. FIG. 18a shows a conventional circuit example, and FIG. 18b shows a circuit example of the present application. The corresponding waveform is shown in FIG.

Conventionally, the READY generation circuit was created by counting CLK. In FIG. 19, the CPU
When ADS1704 is output from the
In this example, the control unit 302 determines that it is an IOR instruction and outputs an IOR pulse 1800 after a constant command delay 1806. Upon receiving the IOR pulse, READY 1701 is output after a constant delay 1802 through a circuit 1805 composed of a counter and a shift register. Along with that, the command 1800 also starts up.

When the frequency of the CPU is flexibly changed, it is not possible to take a circuit configuration which is synchronized with CLK in advance. Therefore, the command delay 1806 and the delay 1802 are set to the ADS / status signal 1 from the CPU.
From 704, a reference CLK 1807 (reference CLK that does not change even when the CPU frequency is changed) is used and generated through a composite circuit 1808 including a counter shift register. In fact, one consisting of several signals
A command signal 1800 and a READY signal 1701 are output by synchronizing 809 with CLK10. Each delay may be created by a delay line or the like instead of the reference clock. Although the circuit configuration is more complicated than that of the conventional circuit configuration of FIG. 18a, a function for exchanging the CPU is added to the circuit configuration, and it can be said that this circuit configuration is more flexible than the conventional circuit configuration.

Although the above description has been focused on only changing the CLK frequency when the CPU is replaced, a wider range of CPUs can be supported by simultaneously changing the CLK frequency and replacing the signal lines and changing the voltage. I can do things. First, regarding the replacement of the signal lines, it is assumed that, for example, the signal lines of the CPU to be replaced are changed at a frequency of 33 MHz. So C of 33MHz or more
In the case of the LK frequency, by preparing in advance the function of exchanging the signal lines of the CPU socket, it is possible to deal with CPUs having different signal lines of 33 MHz or more. Next, regarding the voltage change, it is also possible to change the voltage together with the CLK frequency when there is one socket as shown in FIG. 4b.
As a first example, a system intended to reduce power consumption can be considered. For example, C operating at a low voltage of 3.3V
If the PU is prepared at 25MHz or less and it is 33MHz or more, the CPU and the peripheral control IC are 3.3V.
In that case, since the delay time is too long to operate, it may be necessary to raise the voltage to 5V. Here, if a function for changing the voltage at a frequency of 33 MHz is prepared in advance, low power consumption can be realized at a frequency of 25 MHz or less, the battery life can be extended, and heat generation can be suppressed. When the CLK frequency is 33 MHz or higher, the system can be upgraded with high functionality by raising the voltage to 5V. As a second example, contrary to the above example, when the design rule of the device advances, the CLK frequency may increase and only 3.3V may be supported. For example, there is a case where a CPU that can operate at 5V up to 33MHz does not operate unless it is 3.3V at 100MHz or higher. In this case, 100MHz CL
By having the function of switching the voltage at the K frequency in advance, it is possible to support a wider range of CLK frequencies.

As described above, it can be understood that a wider range of CPUs can be dealt with by simultaneously exchanging the signal lines and changing the voltage while switching the CLK frequency.

Another embodiment of the present invention will be described below.

Even if the CPU is not replaced, it is possible to change the CLK frequency of the CPU by the information stored in the floppy disk, the IC card, the hard disk, or the program, so that the floppy disk,
It is a great advantage that the application software stored in the IC card or the like constructs an optimum user interface corresponding to each information processing device.

From the present viewpoint, the embodiment is exactly the same as the block diagram of the information processing apparatus of FIG. 1 described so far. However, needless to say, the function of replacing the CPU as shown in FIGS. 4A and 4B is not always necessary. It should be noted here that a separate CLK frequency selecting means is required in the information processing apparatus in combination with the function of changing the frequency from the application side. This is because it is necessary to support applications other than the application that supports this function.

FIG. 20 shows a block diagram. Circuit 1600 that outputs CLK corresponding to data set by the user
Is not necessarily a frequency synthesizer.

FIG. 20 will be briefly described. The application program stored in the floppy disk is loaded into the main memory, and the setting data of the CLK frequency is latched in the latch circuit section 1602 by issuing the IOW command 1601 to the port 0C12H. When the information processing apparatus is shipped or the CPU is replaced, the setting data of the CLK frequency of the corresponding CPU is sent to the port 0C13H by the IOW instruction 16
By issuing 04, the data is latched in the latch circuit unit 1603.

Both of the above data are selected by the CLK selection signal 1605 generated by the user operating the setting menu of the information processing apparatus, etc., and input to the CLK generation circuit 1600. CLK generation circuit 1600
Is CLK1 corresponding to the maximum frequency supplied to the CPU 11.
607 is output.

In the CLK selection circuit 1608, the maximum CLK frequency 1607 supplied to the CPU and the CLK (oscillator 16) having a relatively low frequency for realizing low power consumption and the like.
CLK created from 10 and CLK 1607 are divided) and selected by the CLK selection signal 1609 and output to the CPU 11 as CLK10.

With the above configuration, MS-Windows
In the case of running multiple applications at the same time in multi-window such as (Windows) or OS / 2, the most suitable CLK for the corresponding application is automatically selected in each window. In contrast, it is possible to provide an optimum user interface without considering the CLK frequency.

FIG. 21 shows an example in Windows. In this example, an example in which three application programs are operating in each window is shown. At present, the mouse cursor 1901 is the application program NO. Two
It is above 1902. In this case, the application program NO. 2 1902 is operating on the environment created by the environment setting file (tentatively referred to as environment setting file NO. 2) of a task with Windows (provisionally referred to as task NO. 2). Application program N
O. 2 1902 sets the environment setting file NO. 2, the CLK frequency suitable for the operation is written, and Windows is task NO. When recognizing that No. 2 has been selected, the environment setting file NO. 2, the CLK frequency is read, the data corresponding to the CLK frequency is latched in the latch circuit section 1602, and the CLK selection signal 160
5, 1609, the application program NO.
2 Change to the CLK frequency corresponding to 1902. Environment setting file NO. It is of course possible for the user to set the CLK frequency by preparing a menu screen for changing the CLK frequency in 2. Then mouse cursor 19
01 is the application program NO. Three 1903
Similarly, when Windows is moved to the upper position, Windows is not able to access the application program NO. The CLK frequency corresponding to 3 is changed again. Also, the current CLK frequency can be constantly monitored through the CLK display window 1905.

Further, a file for setting the environment of the entire Windows in preference to the environment setting file of each task (provisionally referred to as environment setting file No. 0) is Windows.
Environment setting file NO. The CLK frequency of 0 can be operated through the icon 1904 on the Windows screen. Move the mouse cursor 1901 to 10 MH
It is also possible to fix the CLK frequency to 10 MHz by bringing to the icon 1904 for designating the z operation and clicking.

Conventionally, all the applications had a means for moving them at high speed. Therefore, the function of operating the information processing device with a required minimum current consumption and the operation speed of the user such as a game program are required. There was no function to keep the speed as it was.

The present invention provides a technique necessary when the main body processing capacity becomes much higher than that of the environment provided by application software. It is different.

By the way, the description has been made so far focusing only on switching to the CLK frequency, but it goes without saying that this technique and other techniques can be used in combination. Here are two examples. The first is CLK frequency switching and CPU
CA built in or existing separately from the CPU
This is to specify whether the CHE memory is valid or invalid. CACH
Since the performance may vary depending on the existence of the E memory, it may be necessary to specify the valid / invalid of the CACHE memory at the same time as changing the CLK frequency in order to prepare an environment independent of the model. The second is to adjust the time of the bus hold signal of the CPU. Depending on the upgraded CPU, the CLK frequency cannot be changed in real time. It is a CPU that has a PLL and the like inside. In such a CPU, performance is relatively lowered by adjusting the time of a bus hold signal that is regularly generated such as a refresh signal. Therefore, CL is upgraded by the upgraded CPU.
The method of switching the K frequency and the method of changing the time of the bus hold signal are switched.

[0072]

As described above, in the information processing apparatus of the present invention, in the information processing apparatus capable of changing the clock frequency of the CPU, data relating to the clock frequency of the CPU provided by the external storage device is stored in the information processing apparatus. , The corresponding clock is generated based on the data in the storage means and replaced with the conventional clock. Therefore, the CLK of the information processing apparatus can be easily changed by the program of the external storage device. . Therefore, it becomes possible to set the CLK of the CPU such that the application program or the like has an optimum operation speed in consideration of the performance of the information processing apparatus.

Further, an operating system for managing a plurality of tasks executed on the information processing apparatus, a plurality of storage means for setting data on the CLK frequency corresponding to at least the plurality of tasks, and an instruction of the operating system. A selector that selects one from the plurality of storage means, and a CLK that generates CLK based on the data in the storage means selected by the selector.
Since it has a generating circuit, when a plurality of application programs are executed on a multi-window system such as Windows, CLK is set for each application program, and CLK is automatically switched every time the application program is switched. You can

A means for generating a READY signal when the CLK of the CPU is changed by the data of the external storage device,
A means for controlling the output of CLK by a reset signal or a signal generated by turning on / off the power supply, and CL generated by the frequency synthesizer by the data of the external storage device.
Since the second CLK different from K is generated and the means for switching the two CLKs is provided, the CLK can be switched without causing the information processing apparatus to run away.

Further, since it also has a function of initializing CLK to a predetermined arbitrary frequency by a detection signal indicating that the CPU has been added or replaced, CP
CLK can be automatically changed only by resetting after adding or replacing U.

Since the operating system of the information processing apparatus has means for selecting the CLK frequency of the entire operating system in preference to the CLK frequency of the task currently being executed, for example, Windows
Even if CLK is set for each application program above, it will take precedence over CL for all Windows.
K can be fixed.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing device according to the present invention.

FIG. 2 is a flowchart showing the operation of the information processing apparatus of the present invention.

FIG. 3 is a flowchart of a program for changing the CLK frequency.

FIG. 4 is a diagram of a mounting form of a CPU unit.

FIG. 5 is a circuit block diagram of a CPU unit.

FIG. 6 is an operation timing chart of the CPU unit.

FIG. 7 is a mounting view of a photodiode.

FIG. 8 is a circuit diagram for detecting that the CPU has been replaced.

FIG. 9 is a block diagram of a CLK selection circuit.

FIG. 10 is a block diagram of a CLK switching circuit.

FIG. 11 is an operation timing chart of the CLK switching circuit.

FIG. 12 is a circuit diagram for detecting that the CPU has been replaced.

FIG. 13 is a timing chart of CLR pulse generation when the CPU is replaced.

FIG. 14 is an operation timing chart of the CLK switching circuit at the time of RESET.

FIG. 15 is a block diagram of a CLK switching circuit.

FIG. 16 is an operation timing chart of the CLK switching circuit.

FIG. 17 is an operation timing chart of the memory / CPU control unit.

FIG. 18 is a block diagram of a READY signal generation circuit.

FIG. 19 is an operation timing chart of the READY signal generation circuit.

FIG. 20 is a block diagram of a CLK switching circuit.

FIG. 21 is a diagram showing a display example in WINDOWS of the information processing apparatus of the present invention.

FIG. 22 is a block diagram of a conventional CLK supply circuit.

FIG. 23 is a block diagram of a conventional CLK supply circuit using a PLL.

FIG. 24 is a diagram showing an example of a conventional CLK frequency switching circuit.

[Explanation of symbols]

 10 ... CLK 301 ... CPU part 302 ... Memory / CPU control part 303 ... CLK control part 304 ... VIDEO circuit part 305 ... LCD 306 ... CRT 307 ... Keyboard 308・ ・ ・ Keyboard control circuit unit 309 ・ ・ ・ FDD 310 ・ ・ ・ IC card 311 ・ ・ ・ I / O control circuit unit 312 ・ ・ ・ Expansion bus unit 313 ・ ・ ・ HDD 314 ・ ・ ・ BIOSROM

Claims (7)

[Claims] 1. An information processing apparatus capable of changing a CPU clock frequency, wherein data concerning a CPU clock frequency provided by an external storage device is written into a specific storage means of the information processing apparatus, and the data of the storage means is written. An information processing device which generates a corresponding clock based on the above, and replaces it with a conventional clock. 2. An operating system for managing a plurality of tasks executed on the information processing apparatus, a plurality of storage means for setting at least data regarding a clock frequency corresponding to the plurality of tasks, and an instruction of the operating system. An information processing apparatus comprising: a selector that selects one from the plurality of storage means according to the above; and a clock generation circuit that generates a clock based on the data in the storage means selected by the selector. 3. A first CPU and a second CPU that operates at a clock frequency different from that of the first CPU are added to the first CPU or the first CPU.
An information processing device that can be exchanged with the second CPU, and means for outputting a clock corresponding to the clock frequency of the second CPU, and a CPU cycle end signal (hereinafter referred to as a READY signal) corresponding to the second CPU. The information processing apparatus according to claim 1, further comprising: 4. The means for outputting a clock corresponding to the clock frequency of the second CPU is controlled by a reset signal or a signal generated in accordance with turning on / off of a power supply. Information processing equipment. 5. The means for outputting a clock corresponding to the clock frequency of the second CPU has a frequency synthesizer for generating a first clock to be given to the CPU based on information from an external storage device, and The frequency synthesizer further includes clock generating means for generating a second clock, and when outputting a clock corresponding to the clock frequency of the second CPU, the first clock and the second clock are output.
4. The information processing apparatus according to claim 3, further comprising means for switching the clock of. 6. A detection signal indicating that the second CPU is added to the first CPU or replaced with the first CPU, and a clock frequency is set to an arbitrary frequency predetermined by the detection signal. The information processing apparatus according to claim 3, further comprising means for initial setting. 7. The operating system of the information processing apparatus has means for selecting a clock frequency of the entire operating system in preference to a clock frequency of a task currently being executed. Information processing equipment.