JP3250268B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus capable of changing a clock frequency of a CPU.

[0002]

2. Description of the Related Art Conventionally, as a method of changing a clock frequency (hereinafter referred to as CLK frequency) of a CPU in an information processing apparatus having a CPU, there is a method of changing a CLK frequency by setting a switch of the information processing apparatus or inputting data from a keyboard. Was known. One is for maintaining the compatibility of software, and the other is for providing a mode for reducing the power consumption of the entire information processing apparatus.

Usually, the CLK frequency of the CPU can be set to a predetermined value such as a few settings such as low speed, medium speed, and high speed, and the BIOS can know the setting. However, the application software stored in the external storage device cannot accurately recognize the actual CLK frequency. This is because the CPU mounted in the information processing apparatus functions up with the progress of the device, and since the CLK frequency of the CPU in the future is not known, the application software can accurately determine the CLK frequency in advance.
This is because a function of notifying the CLK frequency of the PU cannot be provided in the information processing device.

As a conventional example, FIG.
The embodiment in which the K frequency is changed has been described. In this example, the CPU 11
This is to switch between the output of the oscillator that generates the CLK 102 corresponding to the maximum CLK frequency of 1 and the CLK 103 having a frequency lower than the maximum CLK frequency.

FIG. 22 shows an example in which the maximum CLK frequency is 40.
FIG. 3 is a circuit block diagram for switching a CLK110 of a CPU 111 at 0 MHz,
02 and an oscillation frequency 103 obtained by dividing the oscillation frequency 102 by １ ／ are selected by a CLK frequency switching signal 104 generated when a user operates a CLK switch or the like and supplied as a CLK 110 of the CPU 111.

In addition to the example using the oscillator shown in FIG. 22, a PLL (phase-locked) for generating a certain fixed frequency by applying an external signal to FIG.
CPU using frequency synthesizer of loop type
2 shows an example of the CLK supply circuit. Frequency synthesizer is IC
ICs that generate several arbitrarily set frequencies are commercially available due to the relative ease of implementation. In this example, the frequency synthesizer IC 105 includes Serial
The frequency of the output CLK 10 is changed according to an arbitrary setting value 107 provided from the system having the interface 106. In the conventional example, an arbitrary set value given from the system is fixed as the system, and the signal 107 is generally generated only by a circuit. Therefore, as a result, the frequency of CLK10 is also fixed as a system.

Conventionally, as a means for upgrading the CPU of the information processing apparatus, it has been common practice to replace the entire CPU board on which a memory and a control IC are mounted in addition to the CPU. Further, as a method of upgrading by replacing only the CPU, there are a method of changing the CLK frequency supplied from the outside to a predetermined frequency by a dip switch or the like, and a method of upgrading the internal CLK.
It has been known to replace the CPU with a CPU whose frequency has been increased from twice to several times.

FIG. 24 shows an example in which the CLK frequency supplied from the outside is changed to a predetermined frequency. In this example, a circuit example in which the CLK frequency corresponding to the CPU 111 is selected by the jumper 21 after replacing the CPU 111 is shown. (Examples of 16 MHz, 25 MHz, and 33 MHz are shown.) As another conventional example of CLK switching, a CPU is used.
Japanese Patent Publication No. 4-1842 discloses that the total power consumption of the microcomputer system is minimized by designating the required clock pulse frequency. The invention disclosed in Japanese Patent Publication No. 4-1842 is an invention that focuses on the fact that a frequency synthesizer generates a high-frequency CLK from a low-frequency CLK, and provides a CLK frequency necessary for performing a programmable task. When the task processing is completed, the operation is performed at a frequency lower than the highest frequency in order to reduce power consumption.

However, the invention disclosed in Japanese Patent Publication No. 4-12842 aims to construct a system that can operate with minimum power consumption, and therefore changes the CLK frequency of the CPU based on information from an external storage device. Features are not taken into account (because they need not be taken into account).
The invention disclosed in Japanese Patent Publication No. 4-1842 is effective for a limited system in which the CLK frequency can be finely controlled for each programmable task. In an information processing apparatus such as a personal computer having a possibility, it cannot be an effective means because it cannot be finely controlled by a program.
The biggest difference between the invention disclosed in Japanese Patent Publication No. 4-1842 and the present invention is that the invention disclosed in Japanese Patent Publication No. 4-1842 is limited to a frequency synthesizer. Is that it can be realized without using a frequency synthesizer.

[0010]

The first problem is that C
A case where a PU is upgraded will be described. As described in the section of the prior art, conventionally, it has been general to replace the entire CPU board. However, with this method, it is necessary to redesign the CPU board, and it is necessary to block the CPU board in advance so that the CPU board can be replaced and to have a structure that can be replaced with a connector or the like. Was.

In order to solve this problem, as described in the section of the prior art, a method of upgrading by replacing only the CPU has become general. As a method of replacing only the CPU, a method of changing the CLK frequency supplied from the outside to a predetermined frequency by a dip switch or the like, and a method of replacing the CPU with the internal CLK frequency raised from twice to several times are known. I was

First, the internal CLK frequency is increased. However, only the CPU corresponding to the frequency of the external CLK is targeted as a CPU to be upgraded.
There is a problem that the CPU cannot cope with CPUs having different LK frequencies and the range of upgrading is limited. Also, CPU
In the method in which the CLK frequency is increased twice or three times internally, since the PLL method or the like is used as the technique, the CLK frequency cannot be changed in real time from the outside.
For this reason, a large amount of current consumption is always consumed even when the CPU performs little processing. CL when the CPU is not processing like a notebook computer
In the case of an information processing apparatus having a function of extending the battery life by stopping or delaying K and further upgrading the CPU, an apparatus having no function of switching the CLK frequency in real time from the outside is excluded. In terms of power consumption, there are many problems in increasing the CLK frequency inside the CPU.

Next, in the method of changing the frequency to a predetermined frequency using a dip switch or the like, it is necessary to mount a plurality of CLK oscillators or the like on the substrate in advance, and it is naturally necessary to know the value of the corresponding frequency in advance. was there. Therefore, in the conventional design, the
If an information processing device having a U is purchased, the CPU technology advances and a high-performance CPU that operates at a high frequency can be obtained. If the operating frequency cannot be predicted in advance, there is no means for increasing the frequency. There is a problem that the function cannot be improved. High-speed C that could not be developed when the user purchased the information processing device
When a PU (of course, the frequency is not known when the user purchases it) is developed, it is becoming important from the viewpoint of effective use of resources that the user can upgrade his system by replacing the CPU. However, the conventional system cannot provide the above environment.

As a second problem, a problem viewed from the application software side will be described. As described in the section of the related art, in an information processing apparatus having a conventional CPU, application software stored in an external storage device cannot control the CLK frequency of the CPU in the information processing apparatus.

[0015] The processing capability of the CPU has been improved as at present.
If the user interface of the corresponding application can sufficiently cope with the operation speed of the user, depending on the application, the higher the processing power of the CPU, the better. For example, there is a case where an application corresponding to a notebook computer or the like wants to prioritize the battery life over the information processing ability. Conventionally, a means has been provided in the information processing apparatus for selecting the method for each predetermined frequency, and the user operates the means.

In an application such as a game, an optimum CPU CLK frequency for each information processing apparatus is described in an application software manual or the like in order to match the operation speed of the user.
K frequency had been changed. However, this requires the operation of the CLK frequency for each application, which is cumbersome and difficult. Especially MS-Window
When a plurality of application programs such as s (registered trademark) and OS / 2 (registered trademark) can be operated at the same time, the user is forced to change the CLK for each window or each program.

As described above, conventionally, there has been a problem that it is difficult for an application to provide an optimum user interface corresponding to each information processing apparatus (corresponding to the CLK frequency of each CPU).

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problem, and when a user purchases an information processing apparatus having a CPU, the processing ability is higher than that of the CPU mounted on the purchased information processing apparatus. Provided is a system capable of upgrading the functions of the information processing apparatus by replacing the CPU without purchasing the entire information processing apparatus when upgrading to a CPU that operates at a high frequency CLK. It is an object. It is another object of the present invention to provide a system in which application software stored in an external storage device can construct an optimal user interface corresponding to each information processing device.

[0019]

The present invention solves the above-mentioned problems by the following constitution. An information processing apparatus according to the present invention includes a CPU
A clock frequency selecting means for supplying a clock signal to the CPU, a multi-window operating system for managing a plurality of application programs, and the plurality of application programs when the plurality of application programs are started from an external storage device. A storage unit that receives and stores data relating to the clock frequency corresponding to each of the programs from each of the plurality of application programs, and when one of the activated plurality of application programs is selected, the selected one is selected. A latch unit that receives data related to the clock frequency corresponding to the one application program from the storage unit. Then, the clock frequency selection means changes the frequency of the clock signal based on the data on the clock frequency received by the latch unit.

In one embodiment, the information processing device is a second information processing device.
Can be added, or the CPU can be connected to the second C
PU exchangeable, and the corresponding C
A second latch unit for receiving data relating to the clock frequency of the PU, and the corresponding CP based on the data relating to the clock frequency received by the second latch unit;
A clock generation unit that generates a clock signal having a maximum frequency of U and supplies the clock signal having the maximum frequency to the clock frequency selection unit.

Preferably, a means for generating a detection signal indicating that the second CPU has been added or that the CPU has been replaced with the second CPU, and Means for setting the frequency of the clock signal to a predetermined initial value.

[0022]

[0023]

[0024]

[0025]

[0026]

According to the configuration of the present invention, when replacing a CPU initially mounted on an information processing apparatus with a high-performance CPU,
C corresponding to a high-performance CPU based on information in an external storage device
LK can be generated to switch CLK while preventing runaway of the device. In addition, even if the CPU is not replaced, the CPU is executed by the application program in the external storage device.
Can be changed, and an operation environment suitable for the ability of the user can be provided.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIG. 1 is a block diagram of an information processing apparatus according to the present invention. The information processing apparatus includes a CPU 301, a memory,
CPU control unit 302, CLK control unit 303, L
A VIDEO circuit unit 304 for controlling the CD 305 and the CRT 306; a keyboard control unit 308 for controlling the keyboard 307; an FDD 309 and an IC card 310;
The information processing apparatus includes an I / O control circuit unit 311 for controlling an external storage device such as an HDD 313, and an expansion bus unit 312 for connecting another device or the like outside the information processing apparatus.
First, the entire function of the present invention will be briefly described, and then detailed description will be given for each functional block.

FIG. 2 shows a case where the user enters C in the information processing apparatus.
A flowchart from the replacement of the PU (here, the CLK frequency of 16 MHz) with a functionally enhanced CPU (here, the CLK frequency of 20 MHz) to the setting of the CLK frequency in accordance with the CLK frequency of the CPU is shown. Also, on the left side of the flowchart, the CLK frequency changes by each step so that it can be understood.
A frequency change table is shown.

First, the user opens the back cover of an information processing device having a structure in which the CPU can be replaced, and
A CPU having a maximum CLK frequency of 16 MHz is taken out from the CPU SOCKET 501 as shown in FIG. 4B and replaced with a CPU having a maximum CLK frequency of 20 MHz.

At this time, the frequency of CLK10 output from the CLK control unit 303 in FIG.
It is necessary to have a function that is initially set to the maximum CLK frequency of the CPU built in when the user purchases the information processing device (for example, 16 MHz->
20Mh-> 25Mhz when function is improved 16M
Hz). This corresponds to, for example, CLK1 in FIG.
This is because, when the frequency of 0 is set to 20 MHz and a 16 MHz CPU is set in the information processing apparatus, the CPU runs out of control from the beginning. (Step 401) Next, the floppy disk attached to the purchased 20 MHz CPU is stored in the FDD (30 in FIG. 1) of the information processing apparatus.
9 (corresponding to 9). The floppy disk stores software for executing an instruction to write a value corresponding to the CLK frequency (in this case, 20 MHz) in the CLK control unit 303 of FIG. CPU CLK of FIG.
FIG. 10 shows a detailed example of the control unit. (Step 40
2) The user turns on the information processing apparatus and boots from the FDD. (Step 403) An instruction for writing a value corresponding to a CLK frequency of 20 MHz of the CPU in the information processing device into the CLK control unit 303 in FIG. 1 stored in the attached floppy disk is automatically executed.

FIG. 3 shows a simple flowchart of a program for changing the CLK frequency.

First, to know the current CLK frequency,
0C which is a register storing the value of the CLK frequency
READ 12 (H). (Program Step 41
0) Next, the current CLK frequency (16 MHz in this example) and the changed CLK frequency (25 MHz in this example) are displayed on the screen, and a message as to whether or not to change the CLK is output to the user. (Program step 411) If NO, a message not to change is displayed on the screen (program step 412). If YES,
The value of the CLK frequency to be changed is written to 0C12 (H). (Program Step 413) Next, a message indicating that the CLK frequency has been changed is displayed on the screen, and a message instructing the user to hit the keyboard to reboot is output. (Program Step 414) Receiving keyboard input, RESET P for reboot
Reboot is performed by accessing 0F0 (H), which is the ORT, and the CLK frequency is changed to 25 MHz according to the value written in the program step 413.
(Program step 415) The reason why the reboot is performed without immediately changing the CLK frequency by the instruction shown in the program step 413 is as follows.
This is because, when the CLK frequency is set by the PLL type frequency synthesizer circuit as shown in FIGS. 23 and 10, if the CLK is switched immediately, the waveform may fluctuate and the CPU may run away. As a matter of course, the memory / CPU control unit 302 in FIG. 1 needs to have a function that does not malfunction even when the CLK frequency changes. This can be realized by a ready signal control described later.

(Steps 404 and 405) After restarting, the application is executed by removing the attached floppy disk for setting the CLK frequency and inserting a normal application disk. If you want to boot from the hard disk, just remove the floppy disk. (Steps 406 and 407) In addition to the above steps, the step 405 in FIG.
It is also possible to move from step 4 to step 406. The circuit functions shown in FIG. 15 will be described later. (Step 407) As described above, when the user purchases the information processing device having the CPU, the high-frequency CLK having a higher processing capability than the CPU mounted on the purchased information processing device.
In the case of upgrading to a CPU that operates on a CPU, the information processing apparatus as shown in the block diagram of FIG. 1 replaces the CPU in accordance with the flowchart shown in FIG. 2 to improve the function without purchasing the entire information processing apparatus. It becomes possible to plan. Further, each function described in the above example, that is, information stored in a floppy disk, an IC card, a hard disk, or the like, or a C
A function of changing the LK frequency, a function of switching the CLK frequency by a RESET signal or the like,
A function for operating the information processing apparatus normally even if the CLK frequency fluctuates due to signal control or the like; a CPU initially installed when the user purchased the information processing apparatus by a signal indicating that the CPU was replaced It can be understood that the function initially set to the maximum CLK frequency is necessary to improve the function without purchasing the entire information processing apparatus.

Subsequently, a detailed description will be given for each functional block.

First, the CPU section 301 in FIG. 1 is usually mounted on a substrate in the form shown in FIGS. 4A and 4B.
In the embodiment of FIG. 4A, the CPU 502 is directly mounted on the board without using a socket. UPGRADE for mounting the upgraded CPU 504 later
SOCKET 503 is also mounted at the same time. The information processing apparatus of the present invention can easily open the lid and easily store the CP in the UPGRADE SOCKET 503 so that the user who has purchased the information processing apparatus can perform the function UP of the information processing apparatus by exchanging the CPU.
It has a structure in which U can be inserted.

FIG. 5 shows a circuit corresponding to FIG. 4a. FIG.
Of the CPU 502 and UPGRADE SOCKE
The signals of T503 are mutually connected except for a few signals. CPU504 is UPGRADE SOCKET5
03, the CPU 5 inside the CPU 504
Since the CHG signal 601 which is a signal connected to the GND terminal 04 is connected to GND, the pull-up resistor 60
6 changes the signal from "H" to "L". In response to this change (the waveform is shown in FIG. 601), the CPU 502
Puts the output signal (702 in FIG. 6) into a high impedance state. By the above operation, the CPU bus signal 604 includes:
The output signal from the CPU 504 becomes valid instead of the signal from the CPU 502.

A signal CLR70 for initializing the frequency of CLK10, which is generated in response to the change of the CHG signal.
1, the CLK control unit 303 of FIG. 1 is initialized to an arbitrary predetermined frequency among the CLK frequencies corresponding to the information processing apparatus. (The frequency to be initially set is usually determined so as not to affect the performance of the restarting operation.) By the way, in order to reduce power consumption, the CHG signal 60 in FIG.
In general, the CPU 502 is set to a standby mode by the CPU 1, but CLK is supplied only to the CPU 504 and CP
A circuit configuration in which the CLK signal of U502 is cut or fixed at L level may be employed. FIG. 9 shows a circuit example. Oscillator 1000, 10 by CHG signal 601
By selecting the power supply of 01, power consumption can be reduced to one CPU even if two CPUs are provided.
Also, even if the power of the oscillator 1000 that generates the CLK signal 1003 to be supplied to the CPU 502 when the CPU 504 is mounted is not turned off, even if the CLK signal 1003 is fixed at the L level, the internal circuit of the CPU 504 does not operate, so that the current consumption is reduced. Can be lowered.

Next, the configuration shown in FIG. 4B is also a commonly used configuration. In this case as well, if it is considered that the CPU 502 in FIG. 5 does not exist, it is the same as FIG.
It can be known from the HG signal 601.

As a method of knowing the replacement of the CPU, it can also be known by adopting the configuration shown in FIG. 7 and the circuit system shown in FIG. As shown in FIG. 7, a photodiode 81 which generates electromotive force by receiving light is mounted in a CPU socket. In FIG. 8, a photodiode 81 receives light when a CPU is replaced and generates an electromotive force. As a result, the transistor 91 turns on, and the CHGCPU 92, which is a signal indicating that the CPU has been replaced, changes from “H” to “L”. The CHG CPU signal 92 is the same as the CHG signal 60
1, and the CLR 701 generated by this signal initializes the CLK control unit 303 in FIG. 1 to an arbitrary predetermined frequency among the CLK frequencies to be supported by the information processing apparatus.

As a second detailed description, the CLK control unit 303 of FIG. 1 will be described. FIGS. 10 and 15 show typical examples in which a user purchases an information processing apparatus, replaces an internal CPU, and changes its CLK.

FIG. 10 shows a method for changing the output frequency of the frequency synthesizer by giving external data to the frequency synthesizer as in FIG. As a method of providing data from the outside, there are a method using an external storage device such as a floppy disk, an IC card, and a hard disk, and a method in which a user can change the CLK frequency in advance using a setup menu or the like. Here, if the frequency can be set to 1 to 150 MHz or the like by using a menu or the like so that the user can change the setting, there is a possibility that the information is likely to be set carelessly and the CPU runs away and the information stored in a floppy disk or the like is destroyed. is there.

Therefore, it is preferable to supply a setup program through an external storage device so as not to be easily set in a setup menu or the like for safety. The above program has a BIOS RO stored in a flash ROM.
If you have a program to rewrite M (such as BIOSROM 314 in FIG. 1) in accordance with the CLK frequency, CP
A flexible environment by U exchange can be provided at the same time.

Hereinafter, a description will be given with reference to FIGS. The data corresponding to the CLK frequency of the corresponding CPU (fine setting data composed of several registers) is I
I / O WR of O instructions 0C00 (H) to 0C08 (H)
The data is latched by the data latch circuit 1101 as a LAT signal 1100 as an ITE instruction and output to the code generation circuit 1103 as data 1102. Code generation circuit 11
03 (generate a code corresponding to the corresponding CLK frequency from the fine setting data) is a PW as shown in FIG.
It is latched by a LOAD signal 1104 that changes when the SW is turned on / off, and is output to the code conversion circuit 1106 as a corresponding code 1105. It should be noted here that the power supply of the data latch circuit 1101 is always backed up by a battery or the like. (The backup power supply is VBK1
It turns off the setting corresponding to the CLK frequency given by the LAT signal 1101.
This is because the data is sometimes held and the data is initialized when the CPU is replaced. When the CPU is replaced, the CHG signal 601 in FIG. 5 is received by the transistor 1120 in FIG.
The HGB 1121 is output. As shown in FIG. 13, in response to the change of the signal CHGB1121, the "L" pulse, CLR701, is input to the data latch circuit 1101, and is reset to initial data such that the CPU does not run away.

The corresponding code 1105 is converted by the code conversion circuit unit 1106 into the counter data 110 corresponding to CLK.
9 and converted to PROGRAMMABLE DIVIDE
It is input to the R unit 1110. As a result, the frequency of CLK10 is changed.

In the above example, after the user changes the CLK frequency based on information stored in a floppy disk or the like, the CLK frequency must be changed by turning on / off the PWSW once as shown in FIG.
(To generate the LOAD signal 1104) Therefore, as another example, the LOAD signal 11
FIG. 14 shows an example of generating CLK 04 and changing the CLK frequency. Signal 1123 generated by RESET button
Generates a RESET signal 1122. A LOAD signal 1104 is also generated by the signal 1123, and data corresponding to the new CLK frequency is given to the code generation circuit 1103 of FIG. 10 to change the frequency of CLK10.

The period 11 sufficient for the frequency synthesizer circuit 1108 to lock the main body RESET signal 1122
By setting to 24, the user does not need to turn off the power again after replacing the CPU and changing the CLK frequency.
By pressing the T button, a new frequency can be set.

FIG. 15 shows an application example of the CLK frequency generation circuit using the frequency synthesizer 1108 shown in FIG. According to the configuration of the present circuit example, after the user changes the CLK frequency based on information stored in a floppy disk or the like, the user does not need to perform an initial setting process of the information processing apparatus such as a power on / off and a RESET signal. 2
The processing can proceed as in step 407 of.
FIG. 16 showing the circuit of FIG.
The function of changing CLK10 from 25 MHz to 50 MHz after CPU replacement will be described with reference to FIG. FIG. 16 CLK1
0 is 25 MHz CL before switching the CLK frequency.
K is output. By the operation corresponding to step 404 in FIG. 2, the control circuit 1402 in FIG.
At the timing of 07, the frequency selection signal 1403 is set to “L”.
To "H". CLK 150
Is switched from the frequency synthesizer circuit output 1404 to the oscillator output 16 MHz 1405 by the selector 1406 in FIG.

Thereafter, the frequency synthesizer is set to 50 MHz.
Is the data latch signal 1407
Latched by the frequency synthesizer 25MHz
From 50 MHz to 50 MHz. Frequency selection signal 1
A period 1502 in which 403 is “H” corresponds to a period until the PLL circuit in the frequency synthesizer circuit locks to the set new frequency. At timing 1508 when the frequency synthesizer is stabilized, the frequency selection signal 140
3, CLK10 is switched from the oscillator output 1405 to the frequency synthesizer circuit output 1404,
Hz.

CLK10 in FIG. 15 corresponds to signal 14 in FIG.
However, if this value is input to the CPU as it is, the timing may not match at the time of memory access or the like, which may cause a malfunction. Therefore, by passing the signal through the CLK switching circuit 1409 in FIG.
0, CLK1401 is switched at a timing that does not affect the system operation as CLK10.
Feed to 1.

As a third detailed explanation, the memory CP shown in FIG.
The U control unit 302 will be described. Even when the CPU is replaced, the entire system must function normally. FIG. 17 shows typical waveforms of the memory / CPU control unit 302. As the frequency of CPU increases, C
The pulse width 1700 of LK becomes shorter.

As a result, the RAS pulse width of DRAM 1
DRAM standards such as 703 and CAS pulse width 1702 are not satisfied. Therefore, according to the present invention, a circuit for controlling a READY signal for instructing the CPU to wait upon receiving a frequency selection signal (data) such as the counter data 1109 in FIG. 10 or 1403 in FIG. 15 is provided in the memory / CPU control unit. It is characterized by.

IO for maintaining memory specification limits and compatibility
By finely controlling the cycle time adjustment for each CLK frequency, it is possible to guarantee a normal operation when the CPU of the information processing apparatus is replaced. Although it is a well-known fact that READY is controlled and weighted, the information processing apparatus of the present invention is novel in that its READY generation circuit is switched in accordance with the CLK frequency of the upgraded CPU. At first glance, in the present circuit, even if the CLK frequency increases, the operating frequency of the peripheral circuit does not change, so that the performance does not seem to change (intentionally such a circuit). However, this can be solved by improving the performance of the CPU itself without depending on peripheral circuits by incorporating the CACHE into the CPU. This circuit is also necessary even if a CLK synchronous DRAM is used. It is always REA at random access and IO cycle.
This is because DY needs to be controlled.

FIG. 18 shows a circuit block diagram as an embodiment. FIG. 18A shows a conventional circuit example, and FIG. 18B shows a circuit example of the present application. The corresponding waveform is shown in FIG.

Conventionally, a READY generation circuit has been created by counting CLK. In FIG. 19, the CPU
When the ADS 1704 is output from the
The control unit 302 determines that the command is an IOR command in this example, and outputs an IOR pulse 1800 after a certain command delay 1806. After receiving the IOR pulse, READY 1701 is output after a predetermined delay 1802 through a circuit 1805 including a counter and a shift register. At the same time, the command 1800 starts up.

If the frequency of the CPU is flexibly changed, it is not possible to take a circuit configuration synchronized with CLK in advance. Therefore, the command delay 1806 and the delay 1802 are changed to the ADS / status signal 1 from the CPU.
From 704, a reference clock 1807 (a reference CLK which does not change even when the frequency of the CPU is changed) is used and generated through a composite circuit 1808 including a counter / shift register. In practice, one consisting of several signals
A command signal 1800 and a READY signal 1701 are output by synchronizing 809 with CLK10. Each delay may be created by a delay line or the like instead of the reference clock. Although the circuit configuration becomes more complicated than that of the conventional circuit configuration shown in FIG. 18A, a function for replacing the CPU is added to the configuration, and it can be said that the present circuit configuration is a circuit configuration that is more flexible than the conventional one.

The above description has been made with emphasis only on the change of the CLK frequency at the time of CPU replacement. However, by simultaneously changing the CLK frequency and changing the signal lines and changing the voltage, it is possible to cope with a wider range of CPUs. Can do things. First of all, the signal lines are exchanged. For example, it is assumed that several signal lines of a CPU to be exchanged have been changed at a frequency of 33 MHz. Therefore, C of 33MHz or more
By preparing in advance the function of replacing the signal line of the CPU socket in the case of the LK frequency, it is possible to cope with a CPU having a different signal line of 33 MHz or more. Next, regarding the voltage change, it is possible to change the voltage together with the CLK frequency when there is only one socket as shown in FIG. 4B.
As a first example, a system for reducing power consumption can be considered. For example, C operating at a low voltage of 3.3 V
PU is prepared at 25MHz or less, and if it is 33MHz or more, CPU and peripheral control IC are 3.3V
In such a case, the operation is impossible due to too much delay time, and the voltage must be increased to 5V in some cases. If a function of changing the voltage at a frequency of 33 MHz is prepared in advance, low power consumption can be realized at a frequency of 25 MHz or less, battery life can be prolonged, and generation of heat can be suppressed. In the case of a CLK frequency of 33 MHz or more, the system can be upgraded to a high function by increasing the voltage to 5V. As a second example, contrary to the above example, when the design rule of the device advances, when the CLK frequency increases, only 3.3 V may be supported. For example, there is a case where a CPU that can operate at 5 V up to 33 MHz does not operate unless the voltage is set to 3.3 V at 100 MHz or higher. In this case, 100MHz CL
By having the function of switching the voltage at the K frequency in advance, it is possible to cope with a wider range of the CLK frequency.

As described above, it can be seen that by replacing the signal lines and changing the voltage at the same time as switching the CLK frequency, it is possible to cope with a wider range of CPUs.

Another embodiment of the present invention will be described below.

Even if the CPU is not replaced, the function of changing the CLK frequency of the CPU by information stored in a floppy disk, an IC card, a hard disk or the like, or by a program allows the floppy disk,
There is a great merit in that application software stored in an IC card or the like constructs an optimal user interface corresponding to each information processing apparatus.

From this point of view, the embodiment is exactly the same as the block diagram of the information processing apparatus shown in FIG. 1 described so far. However, needless to say, the function of exchanging CPUs as shown in FIGS. 4A and 4B is not always necessary. It should be noted here that the information processing apparatus requires a separate CLK frequency selecting means in addition to the function of changing the frequency from the application side. This is because applications other than the application corresponding to this function must be supported.

FIG. 20 is a block diagram. Circuit 1600 that outputs CLK in accordance with data set by the user
Need not necessarily be a frequency synthesizer.

FIG. 20 will be described briefly. The application program stored in the floppy disk is loaded into the main memory, and the setting data of the CLK frequency is latched in the latch circuit unit 1602 by issuing the IOW instruction 1601 to the port 0C12H. When the information processing apparatus is shipped or the CPU is replaced, the setting data of the CLK frequency of the corresponding CPU is transmitted to the port 0C13H by the IOW instruction 16.
04 is latched in the latch circuit section 1603.

The two data are selected by a CLK selection signal 1605 generated by a user operating a setting menu of the information processing apparatus and input to a CLK generation circuit 1600. CLK generation circuit 1600
Is CLK1 corresponding to the maximum frequency supplied to the CPU 11.
607 is output.

The CLK selection circuit 1608 includes a maximum CLK frequency 1607 supplied to the CPU and a relatively low frequency CLK (oscillator 16) for realizing low power consumption and the like.
10 and CLK 1607 are divided by CLK select signal 1609 and output to CPU 11 as CLK 10.

With the above configuration, MS-Windows
In the case of running multiple applications simultaneously in a multi-window such as (Windows) or OS / 2, the most suitable CLK for the corresponding application in each window is automatically selected. Therefore, an optimum user interface can be provided without considering the CLK frequency.

FIG. 21 shows an example in Windows. In this example, an example in which three application programs are operating in each window has been described. At present, the mouse cursor 1901 is moved to the application program No. 2
It is above 1902. In this case, the application program NO. Reference numeral 21902 operates on an environment created by an environment setting file (tentatively referred to as environment setting file No. 2) of a task having Windows (tentatively referred to as task No. 2). Application program N
O. 2 1902 is the environment setting file NO. 2 is written with a CLK frequency suitable for the operation. 2 is recognized, the environment setting file NO. 2, the data corresponding to the CLK frequency is latched in the latch circuit 1602, and the CLK selection signal 160
5, 1609, the application program NO.
2 Change to the CLK frequency corresponding to 1902. Environment setting file No. It is also possible to prepare a menu screen or the like for changing the CLK frequency in 2 and let the user set the CLK frequency by himself. Next, the mouse cursor 19
01 is the application program No. 3 1903
Similarly, when Windows moves up, the application program NO. In other words, the frequency is changed again to the CLK frequency corresponding to 3. The current CLK frequency can be constantly monitored by the CLK display window 1905.

Also, a file for setting the environment of Windows as a whole (temporarily environment setting file No. 0) is given priority over the environment setting file of each task.
To the environment setting file No. A CLK frequency of 0 can be operated through an icon 1904 on the Windows screen. Mouse cursor 1901 at 10 MH
It is also possible to fix the CLK frequency to 10 MHz by bringing it to the icon 1904 for designating the z operation and clicking it.

Conventionally, only a means for moving all applications at high speed is provided. Therefore, a function of operating the information processing apparatus with a necessary minimum current consumption or a user operation speed such as a game program can be reduced. There was no function to keep it at a certain speed.

The present invention provides the necessary technology when the processing power of the main body is much higher than the environment provided by the application software. Are different.

By the way, the description has been given focusing only on the switching to the CLK frequency, but it goes without saying that this technique can be used in combination with other techniques. Here are two examples. The first is CLK frequency switching and CPU
CA built in or present separately from the CPU
This is to specify whether the CHE memory is valid or invalid. CACH
Since the performance may vary depending on the existence of the E memory, in order to prepare an environment independent of the model, it may be necessary to specify the validity or invalidity of the CACHE memory at the same time as changing the CLK frequency. The second is to adjust the time of the bus hold signal of the CPU. Some CPUs that are upgraded cannot change the CLK frequency in real time. It is a CPU having a PLL inside. In such a CPU, the performance of the bus hold signal periodically generated such as a refresh signal is adjusted to relatively lower the performance. Therefore, depending on the upgraded CPU, CL
A method of switching the K frequency and a method of changing the time of the bus hold signal are switched.

[0072]

As described above, according to the information processing apparatus of the present invention, in an information processing apparatus capable of changing the clock frequency of a CPU, data relating to the clock frequency of the CPU provided by an external storage device is used. In this case, since the corresponding clock is generated and replaced with the conventional clock based on the data of the specific storage means, the CLK of the information processing apparatus can be easily changed by the program of the external storage device. . Therefore, it is possible for the application program or the like to set the CLK of the CPU so that the operation speed becomes optimum in consideration of the performance of the information processing apparatus.

Also, an operating system for managing a plurality of tasks executed on the information processing apparatus, a plurality of storage means for setting data relating to at least the CLK frequency corresponding to the plurality of tasks, and an instruction from the operating system A selector for selecting one of the plurality of storage units; and a CLK for generating a CLK based on data of the storage unit selected by the selector.
When a plurality of application programs are executed on a multi-window system such as Windows, for example, a CLK is set for each application program, and the CLK is automatically switched every time the application program is switched. Can be.

Further, the CPU stores the data in the external storage device.
Is changed, a second C different from the CLK generated by the frequency synthesizer based on the data in the external storage device.
LK is generated and means for switching between the two CLKs is provided.
K can be switched.

Also, since a detection signal indicating that the CPU has been added or replaced has a function of initially setting CLK to an arbitrary predetermined frequency, the CP
After adding or replacing U, CLK can be automatically changed only by resetting.

[0076]

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing apparatus according to the present invention.

FIG. 2 is a flowchart showing the operation of the information processing apparatus of the present invention.

FIG. 3 is a flowchart of a program for changing a CLK frequency.

FIG. 4 is a view showing a mounting mode of a CPU unit.

FIG. 5 is a circuit block diagram of a CPU unit.

FIG. 6 is an operation timing chart of a CPU unit.

FIG. 7 is a mounting diagram of a photodiode.

FIG. 8 is a circuit diagram for detecting that the CPU has been replaced.

FIG. 9 is a block diagram of a CLK selection circuit.

FIG. 10 is a block diagram of a CLK switching circuit.

FIG. 11 is an operation timing chart of a CLK switching circuit.

FIG. 12 is a circuit diagram for detecting that the CPU has been replaced.

FIG. 13 is a timing chart of CLR pulse generation at the time of CPU replacement.

FIG. 14 is an operation timing chart of the CLK switching circuit at the time of RESET.

FIG. 15 is a block diagram of a CLK switching circuit.

FIG. 16 is an operation timing chart of a CLK switching circuit.

FIG. 17 is an operation timing chart of a memory / CPU control unit.

FIG. 18 is a block diagram of a READY signal generation circuit.

FIG. 19 is an operation timing chart of a READY signal generation circuit.

FIG. 20 is a block diagram of a CLK switching circuit.

FIG. 21 is a view showing a display example in WINDOWS of the information processing apparatus of the present invention.

FIG. 22 is a block diagram of a conventional CLK supply circuit.

FIG. 23 is a block diagram of a conventional CLK supply circuit using a PLL.

FIG. 24 is a diagram showing an example of a conventional CLK frequency switching circuit.

[Description of Symbols] 10 CLK 301 CPU part 302 Memory CPU control part 303 CLK control part 304 VIDEO circuit part 305 LCD 306 CRT 307・ ・ ・ Keyboard 308 ・ ・ ・ Keyboard control circuit 309 ・ ・ ・ FDD 310 ・ ・ ・ IC card 311 ・ ・ ・ I / O control circuit 312 ・ ・ ・ Expansion bus 313 ・ ・ ・ HDD 314 ・ ・ ・ BIOSROM

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-155437 (JP, A) JP-A-62-298829 (JP, A) JP-A-2-220132 (JP, A) JP-A-4- 257010 (JP, A) JP-A-4-316112 (JP, A) JP-A-5-143195 (JP, A) JP-A-5-88773 (JP, A) JP-A-59-116856 (JP, A) JP-A-3-46014 (JP, A) JP-A-58-40642 (JP, A) JP-A-2-181252 (JP, A) JP-A-5-189369 (JP, A) JP-A-4-205425 (JP, A) JP-A-63-141119 (JP, A) JP-A-63-211034 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 1/04-1 / 08 G06F 3/14 G06F 9/06 G06F 9/22 G06F 9/30 G06F 9/46 G06F 15/78

Claims (3)

(57) [Claims] 1. A CPU, a clock frequency selection unit for supplying a clock signal to the CPU, a multi-window operating system for managing a plurality of application programs, and when the plurality of application programs are started from an external storage device A storage unit that receives and stores data on clock frequencies corresponding to each of the plurality of application programs from each of the plurality of application programs, and when one of the activated plurality of application programs is selected. A latch unit that receives data related to the clock frequency corresponding to the selected one application program from the storage unit;
An information processing apparatus, wherein the clock frequency selection unit changes the frequency of the clock signal based on data on the clock frequency received by the latch unit. 2. The method according to claim 1, wherein a second CPU can be added.
2. The information processing apparatus according to claim 1, wherein a PU is configured to be exchangeable with the second CPU, wherein a second latch unit that receives data related to a clock frequency of a corresponding CPU; A clock generation unit that generates a clock signal of the maximum frequency of the corresponding CPU based on the received data on the clock frequency and supplies the clock signal of the maximum frequency to the clock frequency selection unit. Information processing device. 3. A means for generating a detection signal indicating that the second CPU has been added or that the CPU has been replaced with the second CPU, and wherein the clock is generated when the detection signal is received. 3. The information processing apparatus according to claim 2, further comprising: means for setting a frequency of the signal to a predetermined initial value.