JPH0683247B2 - Autonomous exchange method - Google Patents

Description

DETAILED DESCRIPTION [Outline] A cyclic permutation device in the reverse direction and a cyclic permutation device in the forward direction are provided, and the number of cycles determined by an input terminal and an output terminal to be exchanged, that is, the value of cyclic control information is small. If the cyclic replacement is performed by one of the cyclic replacement devices and the cyclic control information reaches a predetermined value, the cyclic information is subjected to cyclic replacement in the opposite direction to the previous cyclic direction to reduce the number of cycles. In other words, the exchange switching is speeded up.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an autonomous switching system, and more specifically, an autonomous switching system for switching between cyclic replacement and reverse cyclic replacement applied to information in response to cyclic control information, according to selection information. Regarding

In high-speed packet switching, a distributed processing type packet switching method may be used in which a plurality of processing devices are used to process packets instead of a single processing device processing all packets. The performance in such a high-speed packet switching system depends on the switching speed and the switching processing speed of a switching device (coupling network) for exchanging information between distributed processing devices. (Switching speed and switching processing speed) is required.

[Conventional technology]

Conventional interconnection networks include Benes networks, buses, rings and the like. The Benes network is composed of a combination of 2 × 2 matrix switches, each of which is designed to be controlled by an external controller. Therefore, the switching speed of the Benes network is limited by the processing speed of the external control device, and thus there is a limit to the increase in speed.

Further, although the bus and the ring are capable of performing high-speed switching to some extent, the switching speed thereof is determined by the operating speed of the bus and the ring, so that there is a limit to the speedup.
Further, since control of arbitration and the like of the bus is complicated, there is a limit to increase the processing speed due to the overhead caused by this.

From the applicant of the present invention, in July 1986, an autonomous switching system that can eliminate the above-mentioned heterogeneous control and improve the high-speed switching is provided.
Already proposed on the 23rd. This exchange system is constructed as shown in FIG. The exchange method is summarized as follows. That is, the information including the cyclic control bit j input in parallel is cyclically replaced by the cyclic replacement device 1. For each cyclic permutation output, the determination circuit 3i [i = 1 to 3 (n)] performs a predetermined operation on the cyclic control bits of the cyclic permutation output information. If the calculation result has reached a predetermined value, the cyclic permutation output information is output to the output line Oi via the corresponding gate circuit 4i. In the opposite case, the cyclic permutation output information including the calculated cyclic control bits is fed back to the input of the cyclic permutation apparatus 1 via the corresponding gate circuit 4i and information feedback path 5i to perform cyclic permutation. By repeating the above operation, the exchange input information can be output to a desired exchange output.

[Problems to be solved by the invention]

In the above-mentioned prior application method, since self-routing is performed by cyclic substitution in one direction, the number of cyclic substitutions required to perform desired switching increases as the value of n increases. This means that the switching delay becomes large, which hinders the improvement of high-speed switching.

The present invention was created to solve such problems as much as possible, and an object of the present invention is to provide an autonomous switching system that can further promote improvement in high-speed switching while eliminating exclusive control. To do.

[Means for solving problems]

 FIG. 1 shows a block diagram of the principle of the present invention.

As shown in the figure, the present invention is an autonomous switching system that includes a first cyclic replacement means 1 and has a self-routing group 2 that self-routes information under the control of cyclic control information. The second cyclic replacement means 4 for performing the cyclic replacement opposite to the above is provided to add the selection information to the self-routed information, and the selection information and the selection means 3B allow the first cyclic replacement means 1 or the second cyclic replacement means. When one of the replacement means 4 is selected to exchange information by self-routing of information, and when the cyclic control information of self-routed information via the self-routing loop 2 reaches a predetermined value. The autonomous conversion method is configured such that the cyclic control information and the selection information of information are changed by the changing means 3A and sent to the selecting means 3B.

[Work]

While the first cyclic substitution means 1 is placed in the self-routing loop 2, it is self-routed through the loop 2 and outputted to a desired exchange output.
Of the self-routing group 2 by adding the second cyclic replacement means 4 for performing the cyclic replacement opposite to the cyclic replacement means 1 of FIG. Is output to a desired exchange output while being self-routed by. Furthermore, when the cyclic control information is equal to a predetermined value, for example, the number of parallel exchange inputs (at this time, the maximum number of cycles), the cyclic control information and the selection information attached to the information are changed by the changing unit 3A. Selection means 3B that is changed by
Thus, the cyclic permuting means is selected so as to perform the cyclic permutation that is the reverse of the cyclic permutation that has been performed up to that point, and the cyclic permutation is performed in the self-routing loop 2 to be exchanged while being self-routed.

As described above, the desired exchange can be performed with a small number of rounds. That is, the switching delay is shortened and the switching speed can be increased.

〔Example〕

FIG. 2 shows an embodiment of the present invention. This example is 3 × 3
Is an example of configuring the switch. In this figure, I1 ~
I3 indicates an incoming line. The information data input via these incoming lines is added with cyclic control information (cyclic control value) j and selection information k as information for switch control. However, in this cyclic control information j and selection information k, the number of switch inputs and switch outputs is n, the switch input address is i, and the switch output address is θ [iε
I (I is a switch input address set), θεO (O is a switch output address set)], and the smaller one of j given by the following equation is j, and j
Is selected as Equation (1), k = 0, and when Equation (2) is selected, k = 1.

However, when j = 0, j = n.

The incoming lines I1 to I3 are connected to the corresponding selectors 31 ₁ , 31 ₂ , 31 ₃ . Both selectors output iO ₀ , iO according to the value of k.
₁ [i = 1,2,3]. The output of iO ₀ of the selector is connected to the corresponding cyclic permutation inputs 1 _I1 to 1 _I3 of the cyclic permutation device 1,
The output of the selector iO ₁ is connected to the corresponding inverse cyclic permutation inputs 4 _I1 to 4 _I3 of the inverse cyclic permutation unit 4. Cyclic replacement device 1
The cyclic permutation outputs 1 _O1 to 1 _O3 and the inverse cyclic permutation outputs 4 _O1 to 4 _O3 of the inverse cyclic permutation device 4 are connected to the corresponding buffers 22 _{1 to} 22 ₃ , respectively. Different determination circuits (S / C) 23 ₁ to 23 ₃ are connected to these buffers, and these circuits perform processing in accordance with FIG. 3 as will be described later and whether or not j after the processing is 0. A determination signal indicating that is generated.

24 _{1 to} 24 ₃ are gate circuits, which output the information of the corresponding buffer to the corresponding output line according to the judgment signal from the corresponding judgment circuit or as the feedback output to the selector corresponding to the channel. To do. The feedback output of each gate circuit is connected to the selector input of the same input address as the output address via the information feedback paths 5 ₁ , 5 ₂ , 5 ₃ .

The operation of the 3 × 3 switch configured as described above will be described. Information entered in incoming line I1 (input address 1) is output in O3
First, the case where switch output is desired at (output address 3) will be described.

In this switch example, the cyclic control value j and the selection information k added to the information entering the incoming line I1 are j = (θ
When + 3−i) mod 3 and (i + 3−θ) mod 3 are calculated, they become 2 and 1, respectively, so the smaller one is the value of j, and the value of k corresponding thereto is 1. When the information to which the values of j and k are added is input to the input address 1, the selector 31 ₁
Then, since k of the information is 1, the information is sent to the reverse cyclic permutation device 4, cyclically (fixed switch) stored in the buffer 22 ₃ .

The determination circuit 23 ₁ takes out j and k from the buffer 22 ₃ and performs arithmetic processing according to the flow of FIG. That is, since j is not equal to 3 (step S2 in FIG. 3), 1 from j
Is subtracted (step S3 in FIG. 3), the obtained new j and k are stored in the buffer 22 ₃ (step S4 in FIG. 3), and it is determined whether or not the new j is 0. (Step S5 in FIG. 3), sends a judgment signal indicating its equality to the gate circuit 24 ₃ and outputs the information from the buffer 22 ₃ to the output line O ₃ via the gate circuit 24 ₃ as a switch output. To be done. In this example, one cyclic permutation switches. On the other hand, in the prior application system of FIG. 4, the switching requires two cyclic permutations.

As another switching example, switching from the input address "1" to the output address "1" will be described below.

In this case, the information that j = 3 and k = 0 (k = 1 may be used) is input to the selector 31 ₁ . Since k = 0, the information is input to the cyclic permutation device 1, switched, and stored in the buffer 22 ₂ .

The decision circuit 23 ₂ performs the arithmetic processing according to FIG. 3 flow as described above. That is, in the steps S2 and S5, there is a disagreement (that is, S1, S2, S7, S4, and S5 are passed in the flow of FIG. 3), so that j = 1 and k = 1 are added through the gate circuit 24 _2. The information with the bits is transferred to the selector 31 ₂ . k = 1
Therefore, the information is switched by the reverse cyclic permutation device 4 and stored in the buffer 22 ₁ . Then, the information of the buffer 22 ₁ is output to the output line O ₁ by the judgment circuit 23 ₁ by steps S1, S2, S3, S4, S5, and S6 of the flow in FIG. In this switching example, switching is completed by two cyclic permutations. This is required three times according to the prior application method of FIG.

As described above, according to the method of the present invention, it is possible to perform exchange output by using the cyclic permutation having the smaller number of cycles among the cyclic permutations in the forward direction or the backward direction. Furthermore, the number of cycles required to switch from the same input address to the same output address is nxn.
Even if the switch is set to 2 times, it is n in the prior application method of FIG.
You will need it twice.

Although the buffer, the determination circuit and the gate circuit are provided for each cyclic permutation output in the embodiment of FIG. 2, a configuration in which these are shared is also possible.

〔The invention's effect〕

As described above, according to the present invention, the number of cyclic permutations required for switching can be reduced, so that the switching delay can be reduced and a higher speed of switching in self-routing can be promoted.

[Brief description of drawings]

 FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a flow chart for explaining the operation of the decision circuit, and FIG. 4 is a proposed autonomous switching system. It is a figure. In FIGS. 1 and 2, 1 is a first cyclic permutation device, 2 is a self-routing loop, 3 is a switching unit, 3A is a changing unit, 3B is a selecting unit, and 4 is a second cyclic permutation device (reverse cyclic). Replacement device).

Claims (2)

[Claims] 1. An autonomous switching system comprising a first cyclic replacement means (1) and having a self-routing loop (2) controlled by cyclic control information and self-routing information, the first cyclic replacement means (1). A second cyclic permutation means (4) for performing cyclic permutation opposite to that in 1) is provided, and in addition to the cyclic control information, the self-routed information includes:
Selection information for selecting the first cyclic replacement unit (1) or the second cyclic replacement unit (4) is added, and the selection information and the selection unit (3B) are used to select the first cyclic replacement unit (1) or the second cyclic replacement unit (3B). An autonomous exchange method characterized in that the exchange is performed by selecting one of the cyclic permutation means (4) and cyclically permuting information. 2. When the cyclic control information of the information self-routed through the self-routing loop (2) reaches a predetermined value, the cyclic control information and the selection information of the information are changed by the switching means (3). The autonomous conversion system according to claim 1, characterized in that it is changed by means (3A).