KR100223227B1 - Multi-plexer for isdn lim board - Google Patents

Abstract

The present invention implements multiple ports such that a plurality of nodes are connected to one rim board, thereby enhancing scalability of the rim board and allowing one rim board to perform a plurality of rim boards to maintain and maintain the rim board. The present invention relates to an ISDN multiplexing device for ease of use, and the present invention provides a control program that operates throughout the rimboard, so that the ROM, RAM operating in the system memory of the rim, and interrupt request can be processed. A mask register having information representing each cell processor, a logic combiner for logically combining the cell processor information obtained from the mask registers and the interrupts obtained from the plurality of cell processors, and outputting a plurality of result values; Encoders that determine priority by encoding two output signals and then generate an interrupt A rim board performs the same role as a plurality of rim boards by configuring a control unit in a rim board as a central processing unit that controls the data processing order of the plurality of cell processing units according to the priority obtained when an interrupt occurs in the above encoder. It is possible to accommodate multiple subscribers in one rim board.

Description

Multiplexer of the rim (LIM) board for ISND

The present invention relates to the multiplexing of rim (line interface module) boards for ISDN, and in particular, to implement multiple ports so that a plurality of nodes are connected to one rim board, thereby enhancing scalability of the rim board and multiple rims. The present invention relates to a multiplexing device for an ISND rim board in which a rim board serves as a board to facilitate maintenance and repair of the rim board.

In general, an ATM exchange system applied to ISDN is provided with a rim (LIM) board that allows a node of a subscriber to be connected and process data after processing the subscriber's data.

The conventional configuration of a rim board having this function is as shown in FIG.

As shown. Only one node corresponding to one subscriber is connected and operated to one rim board.

That is, only one node corresponding to one subscriber is connected to the first rim board 1, and only one node corresponding to one subscriber is connected to and operated on the second rim board 2.

Here one rim board 1 is shown in FIG. A cell boundary identification and cell discard for a transmission unit 1c for transmitting and receiving subscriber data when the subscriber's lost interest is connected and data obtained from the transmission unit 1c. And a control unit 1d for performing cell header error checking and correction, and controlling the cell processing unit 1a for modifying the VPI / VCI value and controlling the cell processing unit 1a.

The rim board 1 configured as described above receives the subscriber data of the node connected by the transmission unit 1c and transmits it to the cell processing unit Qa. The cell processing unit 1a notifies the control unit 1b that the data has been transferred. Under the general control of exchange, cell boundary identification, cell discard, cell header error check and correction are performed, and VPI / VCI value is modified and transmitted to other subscriber.

However, since the conventional rim board is operated in such a manner that only one node is connected, the demand of the same rim board is required to be equal to the number of nodes in order to accommodate multiple terminals at the same time. There was a problem that the board must be expanded.

These problems make system maintenance and repair difficult, and node expansion also leads to difficult problems.

In addition, since all of the rim boards are expanded according to the number of nodes, there is a disadvantage in that a unit for determining and controlling priorities must be added separately in order to provide differential services among subscribers.

Therefore, the present invention has been proposed to solve the above-mentioned problems of the conventional rim board, and an object of the present invention is to extend the rim board by implementing multiple ports so that a plurality of nodes are connected to one rim board. It is to provide a multiplexing device for ISDN rim boards, which enhances the performance and allows a single rim board to perform a number of rim boards to facilitate maintenance and repair of the rim board.

The present invention for achieving the above object. A plurality of transmitters for transmitting and receiving data of the subscriber, generating an interrupt when the data is transmitted from the plurality of transmitters, cell boundary identification for the transmitted data under the control of the controller, cell discard. A rim board comprising a plurality of cell processing units for checking and correcting cell header errors, and a control unit for controlling data processing of the cell processing unit when an interrupt occurs from the plurality of cell processing units, wherein the control unit operates over the entire rim board. A ROM with stored control program; A mask register having information indicative of each cell processing unit for processing an interrupt request;

A logic combining unit for logically combining the cell processing unit information obtained in the mask register and the interrupts obtained in the plurality of cell processing units, respectively, and outputting a plurality of result values;

A rank encoder which encodes a plurality of output signals obtained from the logic combiner to determine priority and generate an interrupt;

And a central processing unit that controls the data processing order of the plurality of cell processing units according to the priority obtained when an interrupt occurs in the rank encoder.

1 is a diagram illustrating a connection state between a conventional node and a rim board.

2 is a detailed block diagram of a conventional rim board.

3 is a diagram illustrating a connection state between a node and a rim board port in the present invention.

4 is a detailed block diagram of the rim board of FIG.

5 is a block diagram of an apparatus for multiplexing a rim board for an ISDN according to the present invention.

* Explanation of symbols for the main parts of the drawings

13: control unit 13a: ROM

13b: RAM 13c: Mask Register

13d: logical combination unit 13e: rank encoder

13f: central processing unit

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention according to the technical spirit as described above in detail.

3 is a schematic configuration diagram of a rim board 10 to which the present invention is applied, and as shown, a plurality of subscriber nodes are connected by multiple ports.

FIG. 4 is a detailed block diagram of the rim board 10. When the data is transmitted from the plurality of transmitters 11a to 11n and the plurality of transmitters 11a to 11n, the interrupt is interrupted. Cell boundary identification and cell discard for the data generated by generating (IREQ1 to IREQn) and controlled by the control unit 13. When interrupts are generated from the plurality of cell processing units 12a through 12n and the plurality of cell processing units 12a through 12n which perform cell header error auditing and correction, the priority is determined by analyzing the generated interrupts. The control unit 13 controls the data processing order of the plurality of cell processing units 12a to 12n according to the ranking.

As shown in FIG. 5, the control unit 13 includes a ROM 13a in which a control program operating throughout the rim board is stored, a RAM 13b operating as a system memory of the rim, and an interrupt request. A mask register 13c having information indicating each cell processing unit, cell processing unit information obtained from the mask register 13c, and interrupts obtained from the plurality of cell processing units 12a to 12n, respectively. A logic combiner 13d for outputting a plurality of result values, a rank encoder 13e for encoding a plurality of output signals obtained from the logic combiner 13d to determine priority, and generate an interrupt; It consists of a central processing unit (13f) for controlling the data processing order of the plurality of cell processing units in accordance with the priority obtained when an interrupt occurs in the encoder (13e) .

In the apparatus for implementing a multiple port of a rim board according to the present invention configured as described above, when data is transmitted through each subscriber node, a plurality of transmitters 11a to 11n connected to each subscriber node in one-to-one correspondence with the transmitted data. The cell processing units 12a to 12n are connected one to one, respectively.

Then, when the data is transmitted, the plurality of cell processors 12a to 12n generate interrupts IREQ1 to IREQn corresponding to the data and transmit the interrupt to the controller 13, and the corresponding data based on the data processing order transmitted from the controller 13. Process and transmit to the next switching module (not shown in the figure).

Here, the control unit 13 for controlling the overall operation of the rim board multiplexing apparatus according to the present invention is the central processing unit 13f by the control program stored in the ROM (13a) when the interrupt occurs, as shown in FIG. The control operation starts, and the logic combination unit 13d performs an AND on each of the interrupts obtained by the cell processing unit 12 and the data set in the mask register 13c, respectively, and transfers the result to the rank encoder 13e.

That is, the logic combining unit 13d performs a logical AND on the first and gate 13d-1 by the first bit in the interrupt IREQ1 and the mask register 13c obtained by the first cell processing unit 12a and the resultant value. The rank encoder 13e transfers the result to the second encoder 13d-2 and logically multiplies the interrupt IREQ2 obtained from the second cell processor 12d by the second bit in the mask register 13c. The rank echoer 13e is transferred to the rank echoer 13e. Similarly, the nth gate 13d-n performs a logical AND operation on the interrupt IREQn obtained by the Nth cell processor 12n and the Nth bit in the mask register 13c. The result is transmitted to the rank encoder 13e.

When each value is input in this way, the rank encoder 13e determines a node having a high priority according to the priority of the internal logic circuit, and inputs the result to the port PC of the CPU 13f. At the same time, it generates an interrupt and delivers it to the interrupt input port (INT).

Herein, if there are four subscribers and four interrupt request signals, the truth table and the Boolean function of the rank encoder 13e are as shown in Table 1-1 below.

Table 1-1

In [Table 1-1], X represents don't care condition, signals of OUTO and OUT1 are input to input / output port (PC) of central processing unit 13f, and INT signal is interrupt port (INT). Is entered.

Then, when an interrupt is input to the interrupt port INT, the CPU 13f analyzes a signal input to the port PC to determine a node having the highest priority, and a data processing permission signal to the cell processor connected to the node. Send it.

In addition, by setting the corresponding bit in the mask register 13e corresponding to the cell processing unit to receive the data processing permission signal to 0, a data transmission request having a lower priority is performed as described above.

On the other hand, the cell processing unit (for example, the first cell processing unit 12a) receiving the data processing permission signal as described above performs cell boundary identification, cell discarding, cell header error checking and correction on input cell data, and simultaneously Modify the VPI / PCI value.

The cell data thus processed is transmitted to the next switching module to be transmitted to other subscribers.

After the data transfer request of all the cell processing units is processed by the above process, the interrupt port INT no longer requires an interrupt so that the mask register 13c is set to accommodate the data transfer requests of the following cell processing units. .

As described above, the present invention has the effect of accommodating several subscriber nodes in one rim board, and one controller can control a plurality of transmitters and cell processors, which is efficient and gives priority to each subscriber. It is possible to provide various grades of service by processing data by assigning them, and it is easy to expand the capacity when the subscriber node is expanded in the whole exchange.

In addition, since the subscriber capacity of a single rim board is increased, it is not necessary to have a plurality of rim boards as in the prior art, thereby simplifying the structure of the ATM switch for ISDN and improving the efficiency of the entire system.

Claims (2)

A plurality of transmitters for transmitting and receiving subscriber data, and when data is transmitted from the plurality of transmitters, generates an interrupt and performs cell boundary identification, cell discard, and cell header error check and correction on the transmitted data under control of the controller. In the rim board comprising a plurality of cell processing unit to perform, the control unit for controlling the data processing of the cell processing unit when an interrupt occurs from the plurality of cell processing unit, The control unit, ROMs that store control programs that operate throughout the rimboard; A RAM operating as a system memory of the rim; A mask register having information indicative of each cell processing unit for processing an interrupt request; A logic combining unit for logically combining the cell processing unit information obtained in the mask register and the interrupts obtained in the plurality of cell processing units, respectively, and outputting a plurality of result values; A rank encoder which encodes a plurality of output signals obtained from the logic combiner to determine priority and generate an interrupt; And a central processing unit for controlling the data processing order of the plurality of cell processing units according to the priority obtained when an interrupt occurs in the rank encoder. 2. The plurality of ANDs according to claim 1, wherein the logic combination unit logically multiplies the interrupts IREQ1 to IREQn obtained by the plurality of cell processing units 12a to 12n and the corresponding information in the mask register 13c and outputs the result values. A multiplexing device for rim boards for ISDN, characterized in that the gates (13d-1 to 13d-n).