JPH0683036B2 - Complementary signal amplifier circuit for semiconductor memory - Google Patents

Description

The present invention relates to a complementary signal amplifier circuit for semiconductor memory, and more particularly to a complementary signal amplifier circuit for semiconductor memory that uses a plurality of current mirror type sense amplifiers.

[Conventional technology]

Conventionally, an equalizer circuit of a complementary signal amplifier circuit for a semiconductor memory using a plurality of current mirror type sense amplifiers has a circuit configuration as shown in FIGS. 3 and 4.

Next, a conventional technique will be described with reference to FIGS. 4 and 5. FIG. 4 shows a complementary signal amplifier circuit composed of two current mirror type sense amplifiers, each of T31 to T34 has two
P-channel MOSFETs for load of two current mirror type sense amplifiers, T35 to T38 are n-channel MOSFETs for driving two current mirror type sense amplifiers, respectively, T39, T4
0 is an n-channel MOSFET for selecting two current mirror sense amplifiers, and T31 is each MOSFET described above.
P for equalizing the output of the complementary signal amplification circuit configured by
It is a channel MOSFET.

First, the operation when the equalizing TE31 is not connected will be described. Now, the complementary signal amplifier circuit is activated by the activation signal φ ₃₁ and the first and second complementary signals are complementary to each other.
Input signals φ ₃₂ and φ _32B change as shown by the chain line in FIG. Such a change occurs because a selected memory cell is different due to a change in address in the semiconductor memory. The complementary signal amplifier circuit is used when amplifying a signal on a digit line pair of a semiconductor memory. In this case, the number of stages is not limited to one, and multiple stages may be connected and used. Next, the driving MOSFETs T35 to T38 operate, and first the terminals SR3 and SR3B of the input circuit of the current mirror circuit are input.
Potential changes like the curve shown by the broken line. Next, the potentials of the terminals S3 and S3B of the output circuit of the current mirror circuit change like the curves shown by the three-dot chain line. The potential at the starting point of this change is the saturation potential of the terminals S3 and S3B, and the inversion of the signal is delayed as the load capacitance of S3 and S3B increases.

A transistor for equalization in order to shorten the time required to complete the change of the output signal in response to the change of the input signal accompanying the address change (this is referred to as access hereinafter) (this is referred to as access speedup). TE31 to terminal S
Insert between 3, S3B. The input signal of the equalizing signal φ _E3 changes as the address changes, and then the terminals SR3 and SR
The potentials of the terminals S3 and S3B are forcibly set to the intermediate potential at the timing when the potential level of the 3B terminal is inverted. That is, it is a single pulse that is generated by detecting an address change and is active until the potential levels of the terminals SR3 and SR3B are inverted, and becomes a curve shown by a chain double-dashed line. Output terminal S
The output signals φ ₃₂ and φ _32B of 3, S3B change like the curve shown by the solid line. In this way, the access speed can be increased by the time Δ.

Next, another conventional example of the complementary signal amplifier circuit and its operation will be described in the third section.
This will be described with reference to FIGS.

In FIG. 3, T21 to T24 are load MOSFETs of two current mirror type sense amplifiers forming a complementary signal amplifier circuit.
, T25 to T28 are for driving the current mirror type sense amplifier
In the MOSFET, T29 and T30 are selection MOSFETs for a current mirror type sense amplifier, and TE21 to TE23 are equalization MOSFETs for a complementary signal amplifier circuit. Now, when the complementary signal amplifier circuit is activated by the activation signal φ ₂₁ , and the complementary input signals φ ₂₂ and φ _22B change as shown by the dotted line in FIG. 6, φ ₂₂ and φ ₂₂ Drive MO for gate input of _22B
SFET T25 to T28 operate, output terminal of complementary signal amplifier circuit
The output signals φ ₂₃ and φ _23B of S2 and S2B change like the curve shown by the solid line. At this time, output equalizing MOSFET TE2
1, TE22 and TE23 receive the equalizing signal φ _E2 to force access to the complementary signal amplifier circuit, and force the output terminals S2, S2B terminals SR2, SR2B of the complementary signal amplifier circuit to the same potential. The equalizing signal φ _E2 is a single pulse generated by detecting an address change, and its trailing edge is synchronized with the inversion of the input signals φ ₂₂ and φ _{22B to make} the terminals S2 and S2B have the same potential, and the terminal S
It has a pulse width sufficient to make 2 and SR2, S2B and SR2B the same potential. Since the input side as well as the output side of the current mirror circuit is forcibly set to the intermediate potential, this pulse width may be shorter than that of the conventional example of FIG. 4, and the access speed can be further increased.

[Problems to be solved by the invention]

As described above, in the conventional complementary signal amplifying circuit, in the case of the circuit configuration shown in FIG. 4, the potentials of the terminals SR3 and SR3B are reversed only by the capabilities of the driving MOSFETs T35 and T38 of the complementary signal amplifying circuit. The output data of the output terminals S3 and S3B does not reverse unless the potentials of SR3 and SR3B reverse. Therefore, the output equalize signal φ _E3 is, as shown in FIG.
TE31 must be activated until SR3B reverses, which has the disadvantage that the complementary signal amplifier circuit is not accessed very fast.

In the case of the circuit configuration shown in Fig. 3, SR2 and SR2B are
Since it is equalized through TE21, TE22, and TE23, the equalization period is shorter and access is faster than in the case of the circuit configuration shown in FIG. 4 described above.
Since three SFETs are required, the number of circuit elements increases, and the output terminals S2 and S2B are connected to diffusion layers TE21, TE22, and TE23, increasing parasitic capacitance and increasing the output after equalization. There is a drawback in that it is difficult for the potential difference of signals to be made.

[Means for solving problems]

A complementary signal amplifier circuit for semiconductor memory according to the present invention is connected with a first driving transistor connected with an input circuit of a first current mirror circuit as a load and an output circuit of the first current mirror circuit as a load. A first dynamic differential amplifier including a second driving transistor, a third driving transistor connected with the input circuit of the second current mirror circuit as a load, and an output circuit of the second current mirror circuit A second dynamic differential amplifier composed of a fourth driving transistor connected as a load, and a first input for commonly applying a first input signal to the gates of the first and fourth driving transistors. A second input signal commonly applied to the signal supply means and the gates of the second and third driving transistors, the second input signal having a complementary relationship with the first input signal. An input signal supply means, a connection point between the first driving transistor and its load, and the third
A first semiconductor switch inserted between the connection point between the driving transistor and the load thereof, the connection point between the second driving transistor and the load, and the fourth driving transistor and the load. The second semiconductor switch inserted between the connection points and the first semiconductor switch generated when an address change is detected.
Control signal applying means for supplying an equalizing signal which is a single pulse for conducting the first and second semiconductor switches, and the trailing edge of the equalizing signal is synchronized with the inversion of the first and second input signals. Then, the pulse width causes the first semiconductor switch to make the potential at the connection point between the first driving transistor and its load and the potential at the connection point between the third driving transistor and its load equal. And sufficient time for the second semiconductor switch to have equal potentials at the connection point between the second driving transistor and its load and the connection point between the fourth driving transistor and its load. Is set to.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In this embodiment, the output of the first driving transistor T ₁₆ and the first current mirror circuit 1 connected with the input circuit of the first carreto mirror circuit 1 composed of p-channel MOSFETs T ₁₁ and T ₁₂ as a load. An input circuit of a first dynamic differential amplifier 2 composed of a second driving transistor T ₁₅ connected with the circuit as a load, and a second current mirror circuit 3 composed of p-channel MOSFETs T ₁₃ and T _14. A second dynamic type differential amplifier 4 comprising a third driving transistor T ₁₇ connected as a load and a fourth driving transistor T ₁₈ connected as an output circuit of the second current mirror circuit 3; , First input signal supply means for commonly applying the first input signal φ ₁₂ to the gates of the first and fourth driving transistors T ₁₆ and T ₁₈ , and the second and third driving transistors T ₁₅ and 1st common to the gates of T ₁₇ Input signal φ ₁₂
A second input signal supply means for adding a second input signal φ _12B complementary to the connection point, a connection point SR1 between the first driving transistor and its load, and a third driving transistor T ₁₇ and its load. P-channel MOSF inserted between the connection points SR1B of
ET T _E1 is inserted between the first semiconductor switch, the connection point S1 between the second driving transistor T ₁₅ and its load, and the connection point S1B between the fourth driving transistor T ₁₈ and its load. The second semiconductor switch consisting of p-channel MOS FET T _E2 and the first and second
Control signal applying means for supplying an equalizing signal which is a single pulse for turning on the semiconductor switches TE1 and TE2, and the trailing edge of the equalizing signal is the first and second input signals φ ₁₂ and φ _12B. In synchronism with the inversion of, the pulse width of the first semiconductor switch TE1 is set to the connection point between the first driving transistor T ₁₆ and its load and the connection point between the third driving transistor T ₁₇ and its load. is a potential to equipotential, and the potential at the connection point between the second of the second driving transistor T ₁₅ and the semiconductor switch TE2 and the connection point and the fourth and the load of the driving transistor T ₁₈ and its load It is set to a time sufficient to bring the electric potentials to equipotential.

FIG. 2 is an operation signal waveform diagram of the circuit of FIG.

Now, when the complementary signal amplifier circuit is activated by the activation signal φ ₁₁ , and the first and second input signals φ ₁₂ and φ _12B change like the curves shown by the one-dot chain line, for example, the address change of the semiconductor memory When the control signal φ _E1 for equalizing, which is a single pulse generated in accordance with, is generated as shown by the chain double-dashed line, S1 and S1B and SR1 and SR1B are equalized, and from the end of the single pulse of φ _E1 Start amplification. At this time, S1, S1B
Since SR1 and SR1B start amplification from the same potential, higher-speed amplification can be performed compared to the case where equalization is not performed. In order to equalize SR1 and SR1B, φ _E1
Pulse width may be shorter than that of the complementary signal amplifier circuit having the configuration shown in FIG. 4, and the number of constituent elements is smaller than that of the complementary signal amplifier circuit having the configuration shown in FIG. Since the capacitance can be reduced, the potential difference between the output signals after equalization can be easily made.

〔The invention's effect〕

As described above, according to the present invention, the positive phase output terminals S1 and S1B and the negative phase output terminals SR1 and SR1B of the first and second dynamic differential amplifiers, which are the current mirror type sense amplifiers forming the complementary signal amplifying circuit, are provided. Among these, by equalizing S1 and S1B and SR1 and SR1B in which output signals of mutually opposite phases appear, high-speed complementary signal amplification can be performed without using many circuit components.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an operation signal waveform diagram of the circuit shown in FIG. 1, FIG. 3 is a circuit diagram of a conventional example, and FIG. 4 is another conventional example. Circuit diagrams, FIGS. 5 and 6 are operation signal waveform diagrams of the circuits shown in FIGS. 4 and 3, respectively. 1 ... First current mirror circuit, 2 ... First dynamic differential amplifier, 3 ... Second current mirror circuit, 4 ... Second dynamic differential amplifier, S1, S1B, S
2, S2B, S3, S3B ... Connection point between output side of current mirror circuit and driving transistor, SR1, SR1B, SR2, SR2B, SR3, SR3B
...... The connection point between the input side of the current mirror circuit and the driving transistor, T ₁₁ , T ₁₂ , T ₁₃ , T ₁₄ , T ₂₁ ,, T ₂₂ ,, T ₂₃ , T ₂₄ , T ₃₁ , T
₃₂ , T ₃₃ , T ₃₄ , T _E1 , T _E2 , T _E21 , T _E22 , T _E23 , T _E31 ...... p channel MOSFET, T _{15 ,,} T _{16 ,,} T ₁₇ ,, T ₁₈ ,, T ₁₉ ,, T ₂₀ ,, T ₂₅ , T ₂₆ , T ₂₇ , T ₂₈ ,
T ₂₉ , T ₃₀ ,, T ₃₅ , T ₃₆ , T ₃₇ , T ₃₈ , T ₃₉ , T ₄₀ ...... n channel MOSFE
T, φ ₁₂ , φ ₂₂ , φ ₃₂ …… First input signal, φ _12B , φ _22B ,
φ _32B ...... second input signal, φ ₁₃ , φ ₂₃ , φ ₃₃ ...... first output signal, φ _13B , φ _23B , φ _33B ...... second output signal, φ
₁₁ , φ ₂₁ , φ ₃₁ ...... Activation signal, φ _E1 , φ _E2 , φ _E3 ...... Control signal (equalizing signal).

Claims (1)

[Claims] 1. A first driving transistor connected to an input circuit of a first current mirror circuit as a load, and a second driving transistor connected to an output circuit of the first current mirror circuit as a load. A first dynamic differential amplifier, a third driving transistor connected to the input circuit of the second current mirror circuit as a load, and a third driving transistor connected to the output circuit of the second current mirror circuit as a load. A second dynamic differential amplifier including four driving transistors; first input signal supply means for commonly applying a first input signal to the gates of the first and fourth driving transistors; Second input signal supply means for applying a second input signal having a complementary relationship to the first input signal to the gates of the second and third driving transistors in common; A first semiconductor switch inserted between a connection point between a driving transistor and its load and a connection point between the third driving transistor and its load, and a connection between the second driving transistor and its load Point and a second semiconductor switch inserted between the connection point between the fourth driving transistor and its load, and a single semiconductor switch that conducts the first and second semiconductor switches by detecting an address change. Control signal applying means for supplying an equalizing signal which is a pulse, a trailing edge of the equalizing signal is synchronized with the inversion of the first and second input signals, and a pulse width of the first semiconductor switch. Then, the potentials of the connection point between the first driving transistor and its load and the connection point between the third driving transistor and its load are set to the same potential, and the second semiconductor switch is set to the Two For the semiconductor memory, the potential of the connection point between the driving transistor and the load thereof and the potential of the connection point between the fourth driving transistor and the load is set to an equal potential. Complementary signal amplifier circuit.