JPH0682749A - Chip mounting method, chip mounting structure, and electro-optical device and electronic printing device using it - Google Patents

Chip mounting method, chip mounting structure, and electro-optical device and electronic printing device using it

Info

Publication number
JPH0682749A
JPH0682749A JP4233482A JP23348292A JPH0682749A JP H0682749 A JPH0682749 A JP H0682749A JP 4233482 A JP4233482 A JP 4233482A JP 23348292 A JP23348292 A JP 23348292A JP H0682749 A JPH0682749 A JP H0682749A
Authority
JP
Japan
Prior art keywords
chip
chip mounting
photoresist layer
mounting structure
mounting method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4233482A
Other languages
Japanese (ja)
Inventor
Kenji Uchiyama
憲治 内山
Hiroshi Watabe
寛 渡部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP4233482A priority Critical patent/JPH0682749A/en
Publication of JPH0682749A publication Critical patent/JPH0682749A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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Abstract

PURPOSE:To prevent the contact and crosstalk of a chip to an active surface by electrically connecting the surface electrode of the chip to a wiring electrode formed on an insulating base through a specified photoresist layer. CONSTITUTION:A photoresist layer 14 containing a conductive particle 13 is patterned only in the position of the connecting pad of a wiring electrode 12 on a base 11, and the surface electrode 16 of a chip 15 is connected to the photoresist layer 14. The base 11 and the chip 15 may be mutually fixed through an adhesive. According to such a constitution, no material is present between the surface electrodes 16 even if the pitch between the surface electrodes 16 is small. In this case, the photoresist containing the conductive particle means a one which can be patterned by photolithography and is obtained by dispersing the conductive particle in an ultraviolet ray hardening type resin which is thermally or optically hardened after patterning, and the kind of ultraviolet ray hardening resins is never particularly limited as long as they have such a property.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、チップの実装方法並び
に実装構造に関し、チップの各表面電極間のピッチが小
さい場合にもクロストークが生じないようにしたもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting method and a mounting structure for a chip, which prevent crosstalk even when the pitch between surface electrodes of the chip is small.

【０００２】[0002]

【従来の技術】例えば液晶テレビの表示装置として用い
られる液晶表示装置では、多数の画素を有する表示部を
複数の駆動用ＩＣで駆動することにより画像を形成する
が、複数の駆動用ＩＣは表示部を囲む額部に配置されて
いる。そして、近年、例えば液晶表示装置においては、
集積度向上や配線信頼性向上を図るため、いわゆるチッ
プオングラス実装が採用され、また、パッケージに組込
まれない裸のままのベアチップが実装される。2. Description of the Related Art In a liquid crystal display device used as a display device of a liquid crystal television, for example, an image is formed by driving a display section having a large number of pixels with a plurality of driving ICs. It is located on the forehead part that surrounds the part. In recent years, for example, in liquid crystal display devices,
In order to improve integration and wiring reliability, so-called chip-on-glass mounting is adopted, and bare chips that are not incorporated in a package are mounted as they are.

【０００３】一方、チップオングラス実装やベアチップ
実装において、チップの表面電極と基板の配線用電極と
の間を半田で接続すると、熱的にストレスが発生し、ま
た、作業性が良くないという問題がある。そして、かか
る問題を解消する技術として、異方性導電膜によりチッ
プを基板に接続する技術が提案されている（特開平２−
２３３８７号公報）。On the other hand, in the chip-on-glass mounting or the bare chip mounting, when the surface electrode of the chip and the wiring electrode of the substrate are connected by solder, thermal stress is generated and workability is not good. There is. Then, as a technique for solving such a problem, a technique for connecting a chip to a substrate by an anisotropic conductive film has been proposed (JP-A-2-
No. 23387).

【０００４】ここで、異方性導電膜を用いたチップオン
グラス実装の一例を図１１を参照しながら説明する。同
図に示すように、基板１の配線用電極２を覆うように異
方性導電膜３が形成されており、ベアチップ４は異方性
導電膜３を介して配線用電極２上に熱圧着されている。
異方性導電膜３は接着剤樹脂に導電粒子を含有させたも
のであり、熱圧着によりバンプ５で厚み方向に押しつぶ
された接続部分３ａのみに、導電性が生じるようになっ
ている。また、この場合の熱圧着には半田を用いる場合
のような高温を必要とせず、作業性も良好である。An example of chip-on-glass mounting using an anisotropic conductive film will be described with reference to FIG. As shown in the figure, an anisotropic conductive film 3 is formed so as to cover the wiring electrode 2 of the substrate 1, and the bare chip 4 is thermocompression bonded onto the wiring electrode 2 via the anisotropic conductive film 3. Has been done.
The anisotropic conductive film 3 is made of an adhesive resin containing conductive particles, and conductivity is generated only in the connection portion 3a crushed by the bumps 5 in the thickness direction by thermocompression bonding. Further, the thermocompression bonding in this case does not require a high temperature as in the case of using solder, and the workability is good.

【０００５】[0005]

【発明が解決しようとする課題】しかし、前述した異方
性導電膜３は接続部分３ａ以外にも導電粒子が存在する
ので、この導電粒子がベアチップ４のＩＣ能動面に接触
したり、バンプ５間の絶縁抵抗が下がってクロストーク
が発生したりするという問題がある。したがって、特に
バンプ５間のピッチが例えば８０μｍ以下の小さい場合
に問題となる。また、異方性導電膜３を用いて接続する
場合には、接続部分３ａのみを押しつぶさなければなら
ないので、ベアチップ４に必ずバンプ５が必要となる。However, since the above-mentioned anisotropic conductive film 3 has conductive particles other than the connection portion 3a, the conductive particles come into contact with the IC active surface of the bare chip 4 or the bump 5 is formed. There is a problem that the insulation resistance between them decreases and crosstalk occurs. Therefore, it becomes a problem especially when the pitch between the bumps 5 is small, for example, 80 μm or less. Further, when the anisotropic conductive film 3 is used for connection, only the connecting portion 3a needs to be crushed, so that the bare chip 4 always needs the bump 5.

【０００６】本発明はこのような事情に鑑み、チップの
能動面への接触やクロストークの問題がなく、電極間の
ピッチが小さい場合にも対応でき、チップにバンプを形
成する必要のないチップ実装方法、並びにチップ実装構
造及びそれを用いた液晶表示装置等の電気光学装置及び
電子印字装置を提供することを目的とする。In view of such circumstances, the present invention has no problem of contact with the active surface of the chip or crosstalk, and can cope with a case where the pitch between the electrodes is small, and it is not necessary to form bumps on the chip. An object of the present invention is to provide a mounting method, a chip mounting structure, an electro-optical device such as a liquid crystal display device using the same, and an electronic printing device.

【０００７】[0007]

【課題を解決するための手段】前記目的を達成する本発
明に係るチップ実装方法は、チップの表面電極と接続さ
れる配線用電極が形成された絶縁用基板上に、導電粒子
を含有するフォトレジストを塗布し、該配線用電極上に
選択的にフォトレジスト層をパターニング形成し、該フ
ォトレジスト層と前記表面電極とが対向するように配置
しチップを電気的接続したことを特徴とし、また、本発
明に係るチップ実装構造は、チップの表面電極と絶縁用
基板上に形成された配線用電極とが、パターニングされ
た導電粒子を含有するフォトレジスト層を介して電気的
接続されていることを特徴とする。A chip mounting method according to the present invention which achieves the above object, comprises a photo-conductive film containing conductive particles on an insulating substrate having wiring electrodes connected to surface electrodes of the chip. A resist is applied, a photoresist layer is selectively patterned and formed on the wiring electrode, and the chip is electrically connected by arranging the photoresist layer and the surface electrode so as to face each other. In the chip mounting structure according to the present invention, the surface electrode of the chip and the wiring electrode formed on the insulating substrate are electrically connected via a photoresist layer containing patterned conductive particles. Is characterized by.

【０００８】以下、本発明の構成を詳細に説明する。本
発明でチップとは、受動素子、能動素子もしくは集積回
路が作りつけられた、または作りつけられることを前提
とした、半導体または絶縁物の細片をいい、特に集積度
を増すためにパッケージに込まれていないベアチップを
いう。また、チップは直接表面に電極を有するものをい
うが、表面電極の形状は特に限定されず、アルミパッド
のみのものや金バンプ，銅バンプ，樹脂に金属めっきし
たバンプ等のバンプとしたものなどを挙げることができ
る。The structure of the present invention will be described in detail below. In the present invention, a chip refers to a strip of a semiconductor or an insulator on which a passive element, an active element, or an integrated circuit is or has been presumed to be built, and particularly a package for increasing the degree of integration. A bare chip that is not embedded. Also, the chip refers to one having electrodes directly on the surface, but the shape of the surface electrodes is not particularly limited, and those having only aluminum pads, bumps such as gold bumps, copper bumps, bumps plated with metal on resin, etc. Can be mentioned.

【０００９】本発明で用いる、導電粒子を含有するフォ
トレジストとは、フォトリソグラフィーによりパターニ
ングでき且つパターニングした後さらに熱硬化もしくは
光硬化する紫外線硬化型樹脂中に導電粒子を分散したも
のをいい、かかる性質を有すれば紫外線硬化型樹脂の種
類は特に限定されない。また、導電粒子は導電性を有す
る粒子であれば特に限定されず、例えばニッケル、金、
半田等の金属微粒子やカーボン微粉末、またはポリマー
粒子表面にニッケル、金、銀、銅等の金属めっきを施し
たものを挙げることができる。かかる導電性粒子のフォ
トレジスト中の含有量は、熱硬化もしくは光硬化した層
が導電性を有する程度であればよく、一般的には１〜１
０重量％程度とすればよい。The photoresist containing conductive particles used in the present invention is one in which conductive particles are dispersed in an ultraviolet curable resin which can be patterned by photolithography and which is further cured by heat or light. The type of ultraviolet curable resin is not particularly limited as long as it has properties. Further, the conductive particles are not particularly limited as long as they are particles having conductivity, for example, nickel, gold,
Examples thereof include fine metal particles such as solder and fine carbon powder, or those obtained by plating the surface of polymer particles with a metal such as nickel, gold, silver and copper. The content of such conductive particles in the photoresist may be such that the heat-cured or photo-cured layer has conductivity, and generally 1 to 1
It may be about 0% by weight.

【００１０】本発明で用いることがことができる紫外線
硬化型樹脂の一例を挙げる。例えば、ノボラック型エポ
キシ化合物、不飽和モノカルボン酸、および多塩基酸無
水物を順次反応させて得る光重合性樹脂２０〜５０重量
部と、少なくとも１個のエチレン性不飽和二重結合を有
する光重合性化合物２〜３０重量部と、光ラジカル重合
開始剤０．２〜１０重量部と、溶剤可溶性エポキシ樹脂
１０〜３０重量部と、エポキシ硬化剤０．０５〜５重量
部と、有機溶剤２０〜４０重量部とを混合し、総量が１
００重量部となるように調整したものである。An example of the ultraviolet curable resin that can be used in the present invention will be given. For example, 20 to 50 parts by weight of a photopolymerizable resin obtained by sequentially reacting a novolac type epoxy compound, an unsaturated monocarboxylic acid, and a polybasic acid anhydride, and a light having at least one ethylenically unsaturated double bond 2 to 30 parts by weight of a polymerizable compound, 0.2 to 10 parts by weight of a radical photopolymerization initiator, 10 to 30 parts by weight of a solvent-soluble epoxy resin, 0.05 to 5 parts by weight of an epoxy curing agent, and 20 an organic solvent. -40 parts by weight are mixed, and the total amount is 1
It was adjusted so that it would be 00 parts by weight.

【００１１】本発明のチップ実装構造の例を図１及び図
２に示す。同図に示すように、基板１１上の配線用電極
１２の接続パッドの位置のみに、導電粒子１３を含有す
るフォトレジスト層１４がパターニングされ、このフォ
トレジスト層１４上にチップ１５の表面電極１６が接続
されている。なお、図２に示すように基板１１とチップ
１４とは接着剤１７を介して固定するようにしてもよ
い。かかる構造では、表面電極１６間のピッチが小さく
ても間には何も存在しないので、クロストーク等の問題
が生じない。また、フォトレジスト層１４はフォトリソ
グラフィーによるパターニングにより形成できるので、
微小ピッチでも容易に形成することができる。An example of the chip mounting structure of the present invention is shown in FIGS. As shown in the figure, the photoresist layer 14 containing the conductive particles 13 is patterned only on the position of the connection pad of the wiring electrode 12 on the substrate 11, and the surface electrode 16 of the chip 15 is formed on the photoresist layer 14. Are connected. As shown in FIG. 2, the substrate 11 and the chip 14 may be fixed to each other with an adhesive 17. In such a structure, even if the pitch between the surface electrodes 16 is small, there is nothing between them, so that problems such as crosstalk do not occur. Further, since the photoresist layer 14 can be formed by patterning by photolithography,
It can be easily formed even with a fine pitch.

【００１２】[0012]

【実施例】以下、本発明を実施例に基づいて説明する。EXAMPLES The present invention will be described below based on examples.

【００１３】（実施例１）一実施例に係るベアチップ実
装方法を図３を参照しながら説明する。まず、基板１１
の配線用電極１２、接続パッド１２ａを覆うように導電
粒子を含有するフォトレジスト層１４Ａを塗布する（図
３（Ａ），（Ｂ））。本実施例では、基板１１はガラス
基板を用いたが、その他にガラスエポキシ，フェノー
ル，紙フェノール，セラミックス，プラスチック，ポリ
マーフィルム等絶縁性を有する基材ならば適用可能であ
る。また配線用電極１２にはＩＴＯ（酸化インジウム）
を用いたが、その他に銅，アルミニウム，金，ニッケ
ル，クロム，スズ，半田等の金属等や酸化スズ等の導電
性を有する物質を、単独または複数組み合わせて用いる
ことができる。次に、接続パッド１２ａの位置のみに開
口を有するマスク１８を設けた後、紫外線を照射して露
光する（図３（Ｃ））。その後、水系のアルカリ現像液
でフォトレジスト層を現像し、接続パッド１２ａ部分の
みにフォトレジスト層１４Ｂを残す（図３（Ｄ））。そ
して、チップ１５の表面電極１６をフォトレジスト層１
４Ｂ上に位置合せし、ツール１９で加熱・加圧すること
によりチップ１５を基板１１に接続する（図３（Ｅ），
（Ｆ）及び図１参照）。このときの実装構造を図１及び
図２（Ｆ）に示す。(Embodiment 1) A bare chip mounting method according to an embodiment will be described with reference to FIG. First, the substrate 11
A photoresist layer 14A containing conductive particles is applied so as to cover the wiring electrode 12 and the connection pad 12a (FIGS. 3A and 3B). In this embodiment, a glass substrate is used as the substrate 11, but any other insulating base material such as glass epoxy, phenol, paper phenol, ceramics, plastics, polymer films, etc. can be applied. Further, ITO (indium oxide) is used for the wiring electrode 12.
However, in addition to these, metals such as copper, aluminum, gold, nickel, chromium, tin, and solder, and conductive substances such as tin oxide can be used alone or in combination. Next, after providing a mask 18 having an opening only at the position of the connection pad 12a, it is irradiated with ultraviolet rays to be exposed (FIG. 3C). After that, the photoresist layer is developed with an aqueous alkaline developing solution, and the photoresist layer 14B is left only on the connection pad 12a portion (FIG. 3D). Then, the surface electrode 16 of the chip 15 is formed on the photoresist layer 1
4B, and the chip 15 is connected to the substrate 11 by heating and pressurizing with the tool 19 (FIG. 3 (E),
(F) and FIG. 1). The mounting structure at this time is shown in FIGS. 1 and 2 (F).

【００１４】ここで、導電粒子１３を含有するフォトレ
ジスト層１４Ａの一例を説明する。フェノールノボラッ
ク型エポキシ樹脂、アクリル酸およびコハク酸無水物
を、ノボラックエポキシ型エポキシ樹脂のエポキシ基１
当量に対して、アクリル酸のカルボキシル基が０．７〜
１．１当量、コハク酸無水物が０．５〜１．０当量とな
るようにして順次反応させて得た光重合性樹脂と、光硬
化性化合物としてのエチレングリコールアクリレート
と、光ラジカル重合開始剤としての２，２′−ジメトシ
キ−２−フェニルアセトフェノンと、溶剤可溶性エポキ
シ樹脂としての２，６，２′，６′−テトラメチル−ビ
フェニルグリシジルエーテルと、エポキシ硬化促進剤と
してのジシアンジアミドと、有機溶剤としてセロソルブ
アセテートとからなる紫外線硬化型樹脂に、５〜１０重
量％の導電粒子（例えば、ニッケル，半田等の金属粒子
またはプラスチック粒子に金属メッキ（ニッケル，金
等）した粒子等を分散し、フォトレジスト層１４Ａとし
た。Here, an example of the photoresist layer 14A containing the conductive particles 13 will be described. Phenol novolac type epoxy resin, acrylic acid and succinic anhydride, epoxy group 1 of novolac epoxy type epoxy resin
Acrylic acid has a carboxyl group of 0.7-
1.1 equivalents, a photopolymerizable resin obtained by sequentially reacting succinic anhydride to 0.5 to 1.0 equivalents, ethylene glycol acrylate as a photocurable compound, and initiation of photoradical polymerization 2,2'-dimethoxy-2-phenylacetophenone as an agent, 2,6,2 ', 6'-tetramethyl-biphenylglycidyl ether as a solvent-soluble epoxy resin, dicyandiamide as an epoxy curing accelerator, and organic 5 to 10% by weight of conductive particles (for example, metal particles such as nickel and solder or metal particles such as metal particles such as plastic particles (nickel, gold, etc.) dispersed in an ultraviolet curable resin composed of cellosolve acetate as a solvent, This is the photoresist layer 14A.

【００１５】（実施例２）他の一実施例に係るベアチッ
プ実装方法を図４を参照しながら説明する。フォトレジ
スト層１４Ｂを形成する工程（方法）は実施例１の
（Ａ）〜（Ｄ）と同様である。フォトレジスト層１４Ｂ
形成後、接続パッド１２ａ間に、エポキシ系，アクリル
系，ポリエステル系等の熱硬化性接着剤、または、ポリ
スチレンブタジエン系等の熱可塑性接着剤、または、そ
れらのいくつかの種類の混合した接着剤１７をポッティ
ングまたは印刷等の方法により載置する。（図４
（Ｅ））。そして、チップ１５の表面電極１６をフォト
レジスト層１４Ｂ上に位置合わせし、ツール１９で加熱
・加圧することによってチップ１５を基板１１に接続す
る（図４（Ｆ），（Ｇ））。なお、この実装構造は図
２，図４（Ｇ）に示す。(Embodiment 2) A bare chip mounting method according to another embodiment will be described with reference to FIG. The process (method) of forming the photoresist layer 14B is the same as that of (A) to (D) of the first embodiment. Photoresist layer 14B
After formation, a thermosetting adhesive such as an epoxy-based, acrylic-based, or polyester-based adhesive or a thermoplastic adhesive such as polystyrene-butadiene-based adhesive or a mixed adhesive of several kinds thereof is formed between the connection pads 12a. 17 is placed by a method such as potting or printing. (Fig. 4
(E)). Then, the surface electrode 16 of the chip 15 is aligned on the photoresist layer 14B, and the chip 15 is connected to the substrate 11 by heating and pressurizing with the tool 19 (FIGS. 4F and 4G). Note that this mounting structure is shown in FIGS.

【００１６】（実施例３）他の一実施例に係るベアチッ
プ実装方法を図５を参照しながら説明する。フォトレジ
スト層１４Ｂを形成し、チップ１５を基板１１に接続す
る工程（方法）は実施例１と同様である。本実施例は、
チップ１５の表面電極１６に金バンプ等のバンプ１６ａ
を形成したものに適用した例である。なお、この実装装
置は図５（Ｆ）に示す。(Embodiment 3) A bare chip mounting method according to another embodiment will be described with reference to FIG. The process (method) of forming the photoresist layer 14B and connecting the chip 15 to the substrate 11 is the same as in the first embodiment. In this example,
Bumps 16a such as gold bumps on the surface electrodes 16 of the chip 15
It is an example applied to the one formed with. Note that this mounting device is illustrated in FIG.

【００１７】（実施例４）他の一実施例に係るベアチッ
プ実装方法を図６を参照しながら説明する。フォトレジ
スト層１４Ｂを形成し、接続パッド１２ａの間に接着剤
１７を載置し、チップ１５を基板１１に接続する工程
（方法）は実施例２と同様である。本実施例は、チップ
１５の表面電極１６に金バンプ等のバンプ１６ａを形成
したものに適用した例である。なお、この実装構造は図
６（Ｇ）に示す。(Embodiment 4) A bare chip mounting method according to another embodiment will be described with reference to FIG. The process (method) of forming the photoresist layer 14B, placing the adhesive 17 between the connection pads 12a, and connecting the chip 15 to the substrate 11 is the same as that of the second embodiment. The present embodiment is an example in which the chip 15 is provided with bumps 16 a such as gold bumps formed on the surface electrodes 16. Note that this mounting structure is shown in FIG.

【００１８】（実施例５）本発明のベアチップ実装方法
を液晶表示装置に用いた一実施例を図７，図８を参照し
ながら説明する。この液晶表示パネル２１は６４０×４
８０ドットの単純マトリックス液晶表示パネルであり、
これを駆動するドライバーＩＣ１５ＡをＸ側片側４個
（両側で８個）、本発明のベアチップ実装方法（実施例
２）で搭載した。Ｙ側ドライバー５個も同様に本発明の
ベアチップ実装方法（実施例２）で搭載してあるが図示
を省略した。また、パネルの配線及びそれぞれのドライ
バーＩＣの入出力関係の配線も図示を省略した（図
７）。図８は図７の主要部分のVIII−VIII線断面を示し
た。ここで、配線用電極１２の露出部分及び、ＩＣ搭載
部分にはシリコン系モールド剤２２を塗付して、防じ
ん，防湿効果を持たせてある。なお、図８において図４
と同一作用を示す部分には同一符号を付し、重複する説
明は省略する。同様に本発明のベアチップ実装方法並び
に実装構造は、ＥＬ表示装置、及びプラズマ表示装置等
の電気光学装置にも適用できる。(Embodiment 5) An embodiment in which the bare chip mounting method of the present invention is used in a liquid crystal display device will be described with reference to FIGS. This liquid crystal display panel 21 is 640 × 4
An 80-dot simple matrix liquid crystal display panel,
Four driver ICs 15A for driving the same were mounted on one side of the X side (eight on both sides) by the bare chip mounting method of the present invention (Example 2). Five Y-side drivers are similarly mounted by the bare chip mounting method of the present invention (Example 2), but are not shown. In addition, the wiring of the panel and the wiring related to the input / output of each driver IC are also omitted (FIG. 7). FIG. 8 shows a cross section taken along line VIII-VIII of the main part of FIG. Here, the exposed portion of the wiring electrode 12 and the IC mounting portion are coated with a silicon type molding agent 22 to have dustproof and moistureproof effects. In addition, in FIG.
The same reference numerals are given to the portions having the same operation as, and duplicate description will be omitted. Similarly, the bare chip mounting method and mounting structure of the present invention can be applied to electro-optical devices such as EL display devices and plasma display devices.

【００１９】（実施例６）本発明のベアチップ実装方法
を電子印字装置に用いた一実施例を図９，図１０を参照
しながら説明する。この電子印字装置は基板となるサー
マルヘッド１１ＡにドライバーＩＣ１５Ｂを本発明のベ
アチップ実装方法（実施例１）で搭載したものである。
サーマルヘッド及びドライバーＩＣの入出力関係の配線
は図示を省略してある（図９）。図１０には図９の主要
部分のＸ−Ｘ線断面を示した。ここで、配線用電極１２
の露出部分及びＩＣ搭載部分にはシリコン系モールド剤
２２を塗付して、防じん，防湿効果を持たせてある。な
お、図１０において図３と同一作用を示す部分には同一
符号を付し、重複する説明は省略する。(Embodiment 6) An embodiment in which the bare chip mounting method of the present invention is used in an electronic printer will be described with reference to FIGS. 9 and 10. In this electronic printing apparatus, a driver IC 15B is mounted on a thermal head 11A as a substrate by the bare chip mounting method of the present invention (Example 1).
Wiring related to input / output of the thermal head and the driver IC is omitted (FIG. 9). FIG. 10 shows a cross section taken along line XX of the main part of FIG. Here, the wiring electrode 12
A silicon type molding agent 22 is applied to the exposed portion and the IC mounting portion to provide dustproof and moistureproof effects. In FIG. 10, the same parts as those in FIG. 3 are designated by the same reference numerals, and the duplicated description will be omitted.

【００２０】[0020]

【発明の効果】以上説明したように、本発明のチップ実
装構造は、電極間のピッチが小さくても容易に実装可能
であり、電極以外の部分にレジスト層がないのでクロス
トーク等の問題が生じないものである。As described above, the chip mounting structure of the present invention can be easily mounted even if the pitch between the electrodes is small, and there is no resist layer other than the electrodes, so that problems such as crosstalk occur. It does not occur.

【図面の簡単な説明】[Brief description of drawings]

【図１】一実施例に係るチップ実装構造を示す断面図で
ある。FIG. 1 is a cross-sectional view showing a chip mounting structure according to an embodiment.

【図２】他の実施例に係るチップ実装構造を示す断面図
である。FIG. 2 is a sectional view showing a chip mounting structure according to another embodiment.

【図３】実施例１に係るチップ実装方法の製造工程を示
す説明図である。FIG. 3 is an explanatory diagram showing a manufacturing process of the chip mounting method according to the first embodiment.

【図４】実施例２に係るチップ実装方法の製造工程を示
す説明図である。FIG. 4 is an explanatory diagram showing a manufacturing process of the chip mounting method according to the second embodiment.

【図５】実施例３に係るチップ実装方法の製造工程を示
す説明図である。FIG. 5 is an explanatory diagram showing the manufacturing process of the chip mounting method according to the third embodiment.

【図６】実施例４に係るチップ実装方法の製造工程を示
す説明図である。FIG. 6 is an explanatory diagram showing the manufacturing process of the chip mounting method according to the fourth embodiment.

【図７】実施例５を示すチップ実装方法の製造工程を示
す説明図である。FIG. 7 is an explanatory diagram showing the manufacturing process of the chip mounting method showing the fifth embodiment.

【図８】実施例５を示すチップ実装方法の製造工程を示
す説明図である。FIG. 8 is an explanatory diagram showing the manufacturing process of the chip mounting method showing the fifth embodiment.

【図９】実施例６を示すチップ実装方法の製造工程を示
す説明図である。FIG. 9 is an explanatory diagram showing the manufacturing process of the chip mounting method showing the sixth embodiment.

【図１０】実施例６を示すチップ実装方法の製造工程を
示す説明図である。FIG. 10 is an explanatory diagram showing the manufacturing process of the chip mounting method showing the sixth embodiment.

【図１１】従来技術に係るチップ実装構造を示す断面図
である。FIG. 11 is a sectional view showing a chip mounting structure according to a conventional technique.

【符号の説明】[Explanation of symbols]

１１ 基板 １２ 配線用電極 １３ 導電粒子 １４ 導電粒子を含有するレジスト層 １５ チップ １６ 表面電極 １７ 接着剤 １８ マスク 11 substrate 12 wiring electrode 13 conductive particles 14 resist layer containing conductive particles 15 chip 16 surface electrode 17 adhesive 18 mask

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 チップの表面電極と接続される配線用電
極が形成された絶縁用基板上に、導電粒子を含有するフ
ォトレジストを塗布し、該配線用電極上に選択的にフォ
トレジスト層をパターニング形成し、該フォトレジスト
層と前記表面電極とが対向するように配置しチップを電
気的接続したことを特徴とするチップ実装方法。1. A photoresist containing conductive particles is coated on an insulating substrate on which wiring electrodes connected to surface electrodes of a chip are formed, and a photoresist layer is selectively formed on the wiring electrodes. A chip mounting method comprising patterning and forming, and arranging the photoresist layer and the surface electrode so as to face each other and electrically connecting the chip. 【請求項２】 チップの表面電極と絶縁用基板上に形成
された配線用電極とが、パターニングされた導電粒子を
含有するフォトレジスト層を介して電気的接続されてい
ることを特徴とするチップ実装構造。2. A chip characterized in that the surface electrode of the chip and the wiring electrode formed on the insulating substrate are electrically connected via a photoresist layer containing patterned conductive particles. Mounting structure. 【請求項３】 請求項２記載のチップ実装構造を用いた
ことを特徴とする電気光学装置。3. An electro-optical device using the chip mounting structure according to claim 2. 【請求項４】 請求項２記載のチップ実装構造を用いた
ことを特徴とする電子印字装置。4. An electronic printing apparatus using the chip mounting structure according to claim 2.
JP4233482A 1992-09-01 1992-09-01 Chip mounting method, chip mounting structure, and electro-optical device and electronic printing device using it Pending JPH0682749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4233482A JPH0682749A (en) 1992-09-01 1992-09-01 Chip mounting method, chip mounting structure, and electro-optical device and electronic printing device using it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4233482A JPH0682749A (en) 1992-09-01 1992-09-01 Chip mounting method, chip mounting structure, and electro-optical device and electronic printing device using it

Publications (1)

Publication Number Publication Date
JPH0682749A true JPH0682749A (en) 1994-03-25

Family

ID=16955704

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4233482A Pending JPH0682749A (en) 1992-09-01 1992-09-01 Chip mounting method, chip mounting structure, and electro-optical device and electronic printing device using it

Country Status (1)

Country Link
JP (1) JPH0682749A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11287862A (en) * 1998-02-09 1999-10-19 Sharp Corp Two-dimensional image detector and its manufacture
US6356333B1 (en) * 1998-11-25 2002-03-12 Seiko Epson Corporation Conductive adhesive with conductive particles, mounting structure, liquid crystal device and electronic device using the same
KR100350852B1 (en) * 1999-10-05 2002-09-09 밍-퉁 센 Electro - optic device and method for manufacturing the same
CN100342513C (en) * 2001-02-19 2007-10-10 索尼化学&信息部件株式会社 Bumpless semiconductor device
WO2019082758A1 (en) * 2017-10-26 2019-05-02 株式会社ブイ・テクノロジー Board connection structure, board mounting method, and micro-led display

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11287862A (en) * 1998-02-09 1999-10-19 Sharp Corp Two-dimensional image detector and its manufacture
US6356333B1 (en) * 1998-11-25 2002-03-12 Seiko Epson Corporation Conductive adhesive with conductive particles, mounting structure, liquid crystal device and electronic device using the same
KR100350852B1 (en) * 1999-10-05 2002-09-09 밍-퉁 센 Electro - optic device and method for manufacturing the same
CN100342513C (en) * 2001-02-19 2007-10-10 索尼化学&信息部件株式会社 Bumpless semiconductor device
WO2019082758A1 (en) * 2017-10-26 2019-05-02 株式会社ブイ・テクノロジー Board connection structure, board mounting method, and micro-led display
JP2019079985A (en) * 2017-10-26 2019-05-23 株式会社ブイ・テクノロジー Substrate connection structure, substrate mounting method, and micro led display
CN111264089A (en) * 2017-10-26 2020-06-09 株式会社V技术 Substrate connection structure, substrate mounting method and micro LED display

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