JPH0680750B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0680750B2 JPH0680750B2 JP63041070A JP4107088A JPH0680750B2 JP H0680750 B2 JPH0680750 B2 JP H0680750B2 JP 63041070 A JP63041070 A JP 63041070A JP 4107088 A JP4107088 A JP 4107088A JP H0680750 B2 JPH0680750 B2 JP H0680750B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- metal cap
- back surface
- lead
- sealing resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73261—Bump and TAB connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はテープキヤリア・ボンデイング方式によつて半
導体チツプが接合された半導体装置に関し、特にそのパ
ツケージ構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which semiconductor chips are joined by a tape carrier bonding method, and more particularly to a package structure thereof.
従来、テープキヤリア・ボンデイング方式（TAB方式と
いう）に裏面電位を必要とする半導体チツプを用いる場
合には、基板上の配線に半導体チツプの裏面を接着し、
その配線と半導体チツプの表面端子とをリード配線を介
して接続することにより半導体チツプの裏面電位を得て
いた。Conventionally, when a semiconductor chip that requires a back surface potential is used for the tape carrier bonding method (called the TAB method), the back surface of the semiconductor chip is adhered to the wiring on the substrate.
The back surface potential of the semiconductor chip is obtained by connecting the wiring and the front surface terminal of the semiconductor chip via a lead wiring.
第３図はTAB方式によつてキヤリアテープに半導体チツ
プが固着された状態を示す斜視図、第４図は半導体装置
が基板に実装された状態を示す側断面図である。これら
の図において、符号１は表面に突起電極２が形成された
半導体チツプ、３はキヤリアテープで、このキヤリアテ
ープ３はポリイミドテープ等によつて形成され、半導体
チツプ１を臨む開口部3aと、後述する半導体チツプ１の
切り離し工程でキヤリアテープ３から半導体チツプ１を
切断する位置となるアウターリード孔3bとが設けられ、
これら開口部3aとアウターリード孔3bによってサポート
部3cが形成されており、インナーリード4aおよびアウタ
ーリード4bからなるリード配線４が貼着されている。ま
た、このリード配線４はテープ基材に銅等の金属箔を貼
り合わせ、その後リードパターンに形成されており、リ
ードのパターンが複雑になつたり、あるいは長くなつた
際には、リードの載置が不安定にならないよう前記サポ
ート部3cによつて保持されることになる。すなわち、半
導体チツプ１は、TAB方式におけるインナーリードボン
デイング工程において、ボンデイングツール等により前
記インナーリード4aに突起電極２が熱圧着されることに
よって、キヤリアテープ３に固着されることになる。な
お、突起電極２は半導体チツプに形成される他、インナ
ーリード4aに形成されるものもある。５は半導体チツプ
１をキヤリアテープ３に固定すると共に保護するための
封止樹脂、６は半導体装置と他の回路を接続するための
基板で、この基板６上には前記アウターリード4bが接合
される基板配線7aおよび半導体チツプ１の裏面が接着さ
れる基板配線7bが設けられている。８は半導体チツプ１
の裏面と基板配線7bを接着するダイスボンデイング材、
９は外装樹脂である。FIG. 3 is a perspective view showing a state in which a semiconductor chip is fixed to a carrier tape by the TAB method, and FIG. 4 is a side sectional view showing a state in which a semiconductor device is mounted on a substrate. In these drawings, reference numeral 1 is a semiconductor chip having a protruding electrode 2 formed on the surface, 3 is a carrier tape, and the carrier tape 3 is formed by a polyimide tape or the like, and an opening 3a facing the semiconductor chip 1 is formed. An outer lead hole 3b, which is a position where the semiconductor chip 1 is cut from the carrier tape 3 in a step of separating the semiconductor chip 1 described later, is provided,
A support portion 3c is formed by the opening 3a and the outer lead hole 3b, and the lead wiring 4 including the inner lead 4a and the outer lead 4b is attached. Further, the lead wiring 4 is formed by bonding a metal foil such as copper to a tape base material and then forming a lead pattern. When the lead pattern becomes complicated or becomes long, the lead is placed. Will be held by the support portion 3c so that it does not become unstable. That is, the semiconductor chip 1 is fixed to the carrier tape 3 by thermocompression bonding the protruding electrode 2 to the inner lead 4a by a bonding tool or the like in the inner lead bonding process in the TAB method. The protruding electrode 2 may be formed on the inner chip 4a in addition to being formed on the semiconductor chip. 5 is a sealing resin for fixing the semiconductor chip 1 to the carrier tape 3 and protecting it, 6 is a substrate for connecting the semiconductor device and other circuits, and the outer leads 4b are bonded on the substrate 6. The board wiring 7a and the board wiring 7b to which the back surface of the semiconductor chip 1 is adhered are provided. 8 is a semiconductor chip 1
Die bonding material that bonds the backside of the board to the board wiring 7b,
9 is an exterior resin.
したがつて、キヤリアテープ３に固着された半導体チツ
プ１はキヤリアテープ３におけるアウターリード孔3bか
らアウターリード4bと共に所定寸法に打ち抜かれ、次い
で基板配線7aおよび7bにアウターリード4bと切断端およ
び半導体チツプ１の裏面が接合され、外装樹脂９によつ
て固定される。この際、半導体チツプの裏面は基板配線
7bおよび図示しないリード配線を介して突起電極２に接
続されている。Therefore, the semiconductor chip 1 fixed to the carrier tape 3 is punched to a predetermined size from the outer lead hole 3b in the carrier tape 3 together with the outer lead 4b, and then the outer leads 4b, the cut end and the semiconductor chip are attached to the board wirings 7a and 7b. The back surface of 1 is joined and fixed by the exterior resin 9. At this time, the backside of the semiconductor chip is the substrate wiring.
It is connected to the bump electrode 2 via 7b and a lead wire (not shown).
TAB方式によつてキヤリアテープに固着された裏面電位
を要する半導体チツプは最終的に基板上に接合させてか
らでないと半導体チツプの裏面と表面端子が接続されな
いので、インナーリードボンデイング後の動作の確認が
できなかつた。このような不具合を解決するために、内
側底面に半導体チツプの裏面が接合される金属キヤツプ
を形成し、インナーリードボンデイング後の半導体チツ
プをこの金属キヤツプに接合させると共に金属キヤツプ
と半導体チツプの裏面電位接続用リードとを接続させれ
ばよいが、このようにすると、半導体チツプの裏面と金
属キヤツプとの接合時および樹脂封止時に半導体チツプ
と金属キヤツプの線膨張係数の違いによつて生じる熱応
力により半導体チツプが割れたり、パツケージが反つた
りし、製品としての歩留が落ちることとなる。The semiconductor chip fixed to the carrier tape by the TAB method, which requires the back surface potential, must be finally joined to the substrate before the back surface of the semiconductor chip and the surface terminals are connected, so check the operation after inner lead bonding. I couldn't do it. In order to solve such a problem, a metal cap to which the back surface of the semiconductor chip is bonded is formed on the inner bottom surface, and the semiconductor chip after inner lead bonding is bonded to this metal cap, and at the same time the back surface potential of the metal cap and the semiconductor chip is fixed. Although it is sufficient to connect the connecting leads, this makes it possible to reduce the thermal stress caused by the difference in the coefficient of linear expansion between the semiconductor chip and the metal cap when bonding the backside of the semiconductor chip and the metal cap and during resin sealing. As a result, the semiconductor chip is cracked or the package is warped, resulting in a reduction in product yield.
本発明に係る半導体装置は、半導体チツプの表面電極と
接続された裏面電位接続用リードと連結されかつ封止樹
脂が充填される金属キヤツプを備え、この金属キヤツプ
の底部を開口側に突出させることによつて突起を形成
し、この突起を半導体チツプの裏面と接続したものであ
る。また、半導体チツプの表面電極と接続された裏面電
位接続用リードと連結されかつ封止樹脂が充填される金
属キヤツプを備え、この金属キヤツプの内側底面にスペ
ーサを介して半導体チツプの裏面を接続したものであ
る。A semiconductor device according to the present invention includes a metal cap connected to a back surface potential connecting lead connected to a front surface electrode of a semiconductor chip and filled with a sealing resin, and a bottom portion of the metal cap is projected toward an opening side. To form a protrusion, and the protrusion is connected to the back surface of the semiconductor chip. Further, a metal cap connected to the back surface potential connection lead connected to the front surface electrode of the semiconductor chip and filled with a sealing resin is provided, and the back surface of the semiconductor chip is connected to the inner bottom surface of the metal cap via a spacer. It is a thing.
半導体チツプ全体が封止樹脂で覆われ、その熱によつて
平均的に膨張されることになり、しかも半導体チツプの
裏面における金属キヤツプとの接合部分の面積を小さく
することができる。The entire semiconductor chip is covered with the sealing resin and is expanded on average by the heat, and the area of the joint portion with the metal cap on the back surface of the semiconductor chip can be reduced.
以下、その構成等を図に示す実施例により詳細に説明す
る。Hereinafter, the configuration and the like will be described in detail with reference to the embodiments shown in the drawings.
第１図は本発明に係る半導体装置を示す側断面図で、同
図において前記第３図および第４図で説明したものと同
一もしくは同等部材については同一符号を付し、ここに
おいて詳細な説明は省略する。同図において、11は金属
キヤツプで、この金属キヤツプ11は開口縁にフランジ11
aが形成され、底部には底部を開口側に突出させること
によつて突起11bが形成されている。また、前記金属キ
ヤツプ11のフランジ11aは半導体チツプ１の突起電極２
に接続された裏面電位接続用リード（図示せず）と連結
されており、突起11bはダイスボンデイング材８によつ
て半導体チツプ１の裏面と接合されている。なお12は封
止樹脂である。FIG. 1 is a side sectional view showing a semiconductor device according to the present invention. In FIG. 1, the same or equivalent members as those described in FIG. 3 and FIG. Is omitted. In the figure, 11 is a metal cap, and this metal cap 11 has a flange 11 at the opening edge.
a is formed, and a protrusion 11b is formed on the bottom by projecting the bottom toward the opening side. In addition, the flange 11a of the metal cap 11 is connected to the protruding electrode 2 of the semiconductor chip 1.
Is connected to a back surface potential connecting lead (not shown) connected to the semiconductor chip 1, and the projection 11b is joined to the back surface of the semiconductor chip 1 by the die bonding material 8. 12 is a sealing resin.
このように構成された半導体装置を組立てるには、先
ず、TAB方式におけるインナーリードボンデイング工程
においてキヤリアテープ３にリード配線４を介して半導
体チツプ１を固着させる。そして、半導体チツプ１の裏
面と金属キヤツプ11の突起11bとを接合させ、フランジ1
1aと裏面電位接続用リード（図示せず）とを接続させ
る。しかる後、封止樹脂12を金属キヤツプ11内に充填
し、半導体チツプ１およびインナーリード4a等を封止す
る。樹脂封止後、アウターリード4bを切断することによ
つてキヤリアテープ３から半導体装置として分断される
ことになり、組立てが終了する。To assemble the semiconductor device having the above structure, first, the semiconductor chip 1 is fixed to the carrier tape 3 via the lead wiring 4 in the inner lead bonding process in the TAB method. Then, the back surface of the semiconductor chip 1 and the projection 11b of the metal cap 11 are joined to each other, and the flange 1
1a and the back surface potential connection lead (not shown) are connected. Thereafter, the sealing resin 12 is filled in the metal cap 11 to seal the semiconductor chip 1 and the inner leads 4a. After the resin is sealed, the outer lead 4b is cut, so that the carrier tape 3 is separated as a semiconductor device, and the assembly is completed.
したがって、半導体チツプ全体が封止樹脂で覆われ、そ
の熱によつて平均的に膨張されることになり、しかも半
導体チツプの裏面における金属キヤツプとの接合部分の
面積を小さくすることができるから、金属キヤツプと半
導体チツプの線膨張係数の違いによつて生じる熱応力を
緩和させることができる。Therefore, the entire semiconductor chip is covered with the sealing resin, and it will be expanded on average by the heat thereof, and moreover, the area of the joint portion with the metal cap on the back surface of the semiconductor chip can be reduced, The thermal stress caused by the difference in linear expansion coefficient between the metal cap and the semiconductor chip can be relaxed.
なお、本実施例の半導体装置においては、金属キヤツプ
11の底部に突起11bを形成することによつて形成された
凹部11cを、金属キヤツプ11の下面に放熱用のフイン
（図示せず）を取付ける際の位置合わせ用の凹みとして
利用することもできる。In the semiconductor device of this embodiment, the metal cap
The recess 11c formed by forming the protrusion 11b on the bottom of the 11 can also be used as a recess for alignment when attaching a fin (not shown) for heat dissipation to the lower surface of the metal cap 11. .
また、本発明は第２図に示すように、金属キヤツプ11の
内側底面を平坦に形成し、半導体チツプ１の裏面と金属
キヤツプ11との間にスペーサ13を介装させて半導体チツ
プ１と金属キヤツプ11とを接続してもよい。第２図にお
いては前記第１図で説明したものと同一もしくは同等部
材については同一符号を付し、詳細な説明は省略する。
スペーサ13は、金属キヤツプ11の内側底面と半導体チツ
プ１の裏面との間に間隙14が形成され、この部分に封止
樹脂12が充填されるものであれば、どのような形状に形
成してもよく、第２図に示した金属ブロツクのほかに、
金属板を折り曲げることによつて形成されたものでもよ
い。Further, according to the present invention, as shown in FIG. 2, the inner bottom surface of the metal cap 11 is formed to be flat, and a spacer 13 is interposed between the back surface of the semiconductor chip 1 and the metal cap 11 so that the semiconductor chip 1 and the metal chip 11 are connected to each other. It may be connected to the cap 11. In FIG. 2, members that are the same as or equivalent to those described in FIG. 1 are given the same reference numerals, and detailed description thereof is omitted.
The spacer 13 is formed in any shape as long as a gap 14 is formed between the inner bottom surface of the metal cap 11 and the back surface of the semiconductor chip 1 and this portion is filled with the sealing resin 12. Well, in addition to the metal block shown in Fig. 2,
It may be formed by bending a metal plate.
さらにまた、本発明においては裏面電位を必要としない
半導体チツプを使用してもよく、半導体チツプがTAB方
式によつてキヤリアテープに固着されてなる半導体装置
であれば、どのようなものにでも適用することができ
る。Furthermore, in the present invention, a semiconductor chip that does not require a back surface potential may be used, and any semiconductor device can be used as long as the semiconductor chip is fixed to a carrier tape by the TAB method. can do.
以上説明したように本発明によれば、半導体チツプの表
面電極と接続された裏面電位接続用リードと連結されか
つ封止樹脂が充填される金属キヤツプを備え、この金属
キヤツプ底部を開口側に突出させることによつて突起を
形成し、この突起を半導体チツプの裏面と接続したた
め、また、半導体チツプの表面電極と接続された裏面電
位接続用リードと連結されかつ封止樹脂が充填される金
属キヤツプを備え、この金属キヤツプの内側底面にスペ
ーサを介して半導体チツプの裏面を接続したため、半導
体チツプをキヤリアテープに固着した時点で動作の確認
ができ、半導体チツプの異常を早期に発見することがで
きる。このため、歩留りの向上およびコストダウンが実
現される。As described above, according to the present invention, the metal cap, which is connected to the back surface potential connection lead connected to the front surface electrode of the semiconductor chip and is filled with the sealing resin, is provided with the bottom of the metal cap protruding toward the opening side. To form a protrusion and connect the protrusion to the back surface of the semiconductor chip, and the metal cap that is connected to the back surface potential connection lead connected to the front surface electrode of the semiconductor chip and is filled with the sealing resin. Since the back surface of the semiconductor chip is connected to the inner bottom surface of this metal cap via the spacer, the operation can be confirmed when the semiconductor chip is fixed to the carrier tape, and the abnormality of the semiconductor chip can be detected early. . Therefore, the yield is improved and the cost is reduced.
また、半導体チツプの裏面と金属キヤツプの内側底面に
間隙が設けられることになり、この間隙にも封止樹脂が
充填されるので、半導体チツプ全体が封止樹脂で覆わ
れ、その熱によつて平均的に膨張され、しかも、半導体
チツプの裏面における金属キヤツプとの接合部分の面積
を小さくできるので、ダイボンド時に金属キヤツプと半
導体チツプの線膨張係数の違いによつて生じる熱応力を
緩和させることができる。したがつて、ダイボンド時、
樹脂封止時に生じるパツケージの反り、半導体チツプの
割れ等を減少させることができる。In addition, a gap is provided between the back surface of the semiconductor chip and the inner bottom surface of the metal cap, and this gap is also filled with the sealing resin, so that the entire semiconductor chip is covered with the sealing resin and the heat generated by It is expanded on average, and since the area of the joint portion with the metal cap on the back surface of the semiconductor chip can be reduced, it is possible to reduce the thermal stress caused by the difference in the linear expansion coefficient between the metal cap and the semiconductor chip during die bonding. it can. Therefore, at the time of die bonding,
It is possible to reduce the warpage of the package, the cracking of the semiconductor chip, and the like that occur during resin sealing.
第１図および第２図は本発明に係る半導体装置を示す側
断面図、第３図はTAB方式によつてキヤリアテープに半
導体チツプが固着された状態を示す斜視図、第４図は半
導体装置が基板に実装された状態を示す側断面図であ
る。 １……半導体チツプ、２……突起電極、４……リード配
線、11……金属キヤツプ、11b……突起、12……封止樹
脂、13……スペーサ。1 and 2 are side sectional views showing a semiconductor device according to the present invention, FIG. 3 is a perspective view showing a state in which a semiconductor chip is fixed to a carrier tape by a TAB method, and FIG. 4 is a semiconductor device. FIG. 3 is a side sectional view showing a state in which is mounted on a substrate. 1 ... semiconductor chip, 2 ... projection electrode, 4 ... lead wiring, 11 ... metal cap, 11b ... projection, 12 ... sealing resin, 13 ... spacer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 寺岡 康宏 兵庫県伊丹市瑞原４丁目１番地 三菱電機 株式会社北伊丹製作所内 (72)発明者 関 博司 兵庫県伊丹市瑞原４丁目１番地 三菱電機 株式会社北伊丹製作所内 (72)発明者 上田 哲也 兵庫県伊丹市瑞原４丁目１番地 三菱電機 株式会社北伊丹製作所内 (56)参考文献 特公 昭52−3275（ＪＰ，Ｂ２) ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yasuhiro Teraoka 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation Kita-Itami Works (72) Inventor Hiroshi Seki 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation Company Kita Itami Works (72) Inventor Tetsuya Ueda 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation Kita Itami Works (56) References Japanese Patent Publication No. Sho 52-3275 (JP, B2)
Claims (2)
電位接続用リードと連結されかつ封止樹脂が充填される
金属キヤツプを備え、この金属キヤツプ底部を開口側に
突出させることによつて突起を形成し、この突起を半導
体チツプの裏面と接続したことを特徴とする半導体装
置。1. A metal cap, which is connected to a back surface potential connecting lead connected to a front surface electrode of a semiconductor chip and is filled with a sealing resin, is provided with a protrusion by projecting a bottom portion of the metal cap toward an opening side. And a protrusion is connected to the back surface of the semiconductor chip.
電位接続用リードと連結されかつ封止樹脂が充填される
金属キヤツプを備え、この金属キヤツプの内側底面にス
ペーサを介して半導体チツプの裏面を接続したことを特
徴とする半導体装置。2. A back surface of the semiconductor chip is provided with a metal cap that is connected to a back surface potential connecting lead connected to a front surface electrode of the semiconductor chip and is filled with a sealing resin, the bottom surface of the inside of the metal cap having a spacer interposed therebetween. A semiconductor device characterized by being connected to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63041070A JPH0680750B2 (en) | 1988-02-24 | 1988-02-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63041070A JPH0680750B2 (en) | 1988-02-24 | 1988-02-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01215050A JPH01215050A (en) | 1989-08-29 |
| JPH0680750B2 true JPH0680750B2 (en) | 1994-10-12 |
Family
ID=12598187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63041070A Expired - Lifetime JPH0680750B2 (en) | 1988-02-24 | 1988-02-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0680750B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0823042A (en) * | 1994-07-07 | 1996-01-23 | Fujitsu Ltd | Semiconductor device, its manufacture and mold used for it |
| JPH0831988A (en) * | 1994-07-20 | 1996-02-02 | Nec Corp | Sealing structure of tape carrier package |
-
1988
- 1988-02-24 JP JP63041070A patent/JPH0680750B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01215050A (en) | 1989-08-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5409866A (en) | Process for manufacturing a semiconductor device affixed to an upper and a lower leadframe | |
| US5218229A (en) | Inset die lead frame configuration lead frame for a semiconductor device having means for improved busing and die-lead frame attachment | |
| US6285074B2 (en) | Semiconductor device | |
| JP2852178B2 (en) | Film carrier tape | |
| JPH0427145A (en) | Semiconductor device | |
| JPH0746713B2 (en) | Semiconductor mounting board | |
| US6225558B1 (en) | Chip size semiconductor package and fabrication method thereof | |
| US6717244B1 (en) | Semiconductor device having a primary chip with bumps in joined registration with bumps of a plurality of secondary chips | |
| JPH0680750B2 (en) | Semiconductor device | |
| JPH01132142A (en) | Package structure of semiconductor device | |
| EP0474224B1 (en) | Semiconductor device comprising a plurality of semiconductor chips | |
| EP0671763A2 (en) | Ultrasonically welded plastic support ring for handling and testing semiconductor devices | |
| JP2840166B2 (en) | Semiconductor device | |
| JP2001077266A (en) | Manufacture of resin sealed semiconductor device | |
| JP2842854B2 (en) | Method for manufacturing semiconductor device | |
| JP3270883B2 (en) | Semiconductor device | |
| JPH06120403A (en) | Lead frame for mounting electronic circuit element | |
| JPH06268144A (en) | Semiconductor integrated circuit device | |
| JP3284853B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2551243B2 (en) | Semiconductor device | |
| JPH08250545A (en) | Semiconductor device and manufacture thereof | |
| JP2513781B2 (en) | Semiconductor device | |
| JP2718299B2 (en) | Large-scale integrated circuits | |
| JPH08181168A (en) | Semiconductor device | |
| JPH05235260A (en) | Semiconductor device |