JPH0677585B2 - Ultrasonic Doppler device - Google Patents

Description

TECHNICAL FIELD The present invention relates to an ultrasonic Doppler device that measures the blood flow velocity in a living body by utilizing the Doppler effect of ultrasonic waves and displays the result as an image.

(B) Conventional technology and its problems In the conventional ultrasonic Doppler device, the echo signal obtained by pulse-radiating the ultrasonic beam into the living body is phase-detected to extract the Doppler signal, and this Doppler signal is After D conversion, fast Fourier transform (FFT) is performed to obtain the power spectrum of each frequency. As shown in FIG. 4, the horizontal axis corresponds to time, the vertical axis corresponds to Doppler frequency, and the luminance corresponds to the power of each frequency component. There are some that are designed to display images.

By the way, when the Doppler signal is subjected to the fast Fourier transform, the required operation length differs depending on the number of target data points. For example, when handling data sampled at 128 points, about 16 bits are required. Therefore, both the real part data and the imaginary part data obtained by the fast Fourier transform are both 16 bits. To obtain the power spectrum from both data, it is necessary to calculate the square root of the sum of squares of both data, but the 16-bit sum of squares operation has a complicated circuit configuration.
Because of the large scale, both the real part and the imaginary part of the data are usually calculated with 8 bits.

That is, when calculating the power spectrum,
As shown in FIG. 3, first and second bit shift circuits B1 and B2 composed of multiplexers and the like are provided in front of the power spectrum arithmetic circuit A, and the first and second bit shift circuits B1 and B2 are used. 8 bits are selected by shifting the most significant bit (MSB) of 16 bits by a predetermined number of bits. In this case, when it is desired to observe the power spectrum based on the echo signal from a comparatively thin blood vessel such as the groin and brachial artery, the signal intensity level is generally low, so the lower bits must be selected. I won't. At this time, if data having a large value is input, overflow occurs in the first and second bit shift circuits B1 and B2. As a result, there has been a problem that the power spectrum should be displayed brightly in the opposite direction, that is, the phenomenon of so-called reverse display of luminance occurs.

The present invention has been made in view of the above circumstances, and an object thereof is to prevent a phenomenon such as reverse display of luminance due to overflow from occurring even when bit shifting is performed.

(C) Means for Solving Problems The present invention adopts the following configuration in order to achieve the above object. That is, the ultrasonic Doppler device of the present invention is a Fourier transform circuit for Fourier transforming a Doppler signal obtained by phase-detecting an echo signal, and a power spectrum from both real part and imaginary part data obtained by this Fourier transform circuit. A bit shift circuit that shifts both of the data by a predetermined number of bits between the power spectrum calculation circuit that calculates and the overflow of both data given by the Fourier transform circuit and the number of bits shifted by the bit shift circuit. Discriminating circuit for discriminating presence / absence of overflow due to bit shift based on the margin bits up to, and fixing the values of both data to the maximum value in response to the overflow discriminating signal output from the discriminating circuit. A level fixing circuit is provided.

(D) Action In the ultrasonic Doppler device of the present invention, the Doppler signal obtained by phase-detecting the echo signal is Fourier transformed by the Fourier transform circuit. As a result of the Fourier transform, both data of the real part and the imaginary part are output from the same circuit, so both of these data are commonly input to the bit shift circuit and the discrimination circuit. The discriminating circuit discriminates the presence / absence of overflow due to the bit shift based on the number of bits to be shifted by the bit shift circuit and the margin bits up to the overflow of both 16-bit data given from the Fourier transform circuit.

When an overflow occurs, the determination circuit outputs a determination signal indicating overflow, and the determination signal is input to the level fixing circuit. The level fixing circuit fixes the values of both data to the maximum value in response to the overflow determination signal. When no overflow occurs, both data are shifted by a predetermined number of bits by the bit shift circuit. Then, the 8-bit real part data and the imaginary part data are sent to the power spectrum arithmetic circuit of the next stage.

(E) Embodiment FIG. 1 is a block diagram showing an entire ultrasonic Doppler device according to an embodiment of the present invention.

In the ultrasonic Doppler device 1 of this embodiment, an echo signal obtained by pulse-radiating an ultrasonic beam into a living body is amplified by an amplifier 2 and then commonly input to the first and second phase detectors 4 and 6. To be done. At this time, a sine wave signal is given from the reference signal generator 8 to the first phase detector 4 and a cos wave signal is given to the second phase detector 6, and the echo signal is quadrature detected. The above sin wave signal and cos wave signal both have the same ultrasonic transmission frequency and a phase difference between them.
It is set to 90 °. As a result, the first phase detector 4
From the second phase detector 6 and the second Doppler signal from the second phase detector 6. The outputs from the first and second phase detectors 4 and 6 are digitized by the first and second A / D converters 14 and 16 via the bandpass filters 10 and 12, respectively, and then the Fourier transform circuit. Entered in 18. The Fourier transform circuit 18 performs fast Fourier transform on the first and second Doppler signals and outputs real part data and imaginary part data each consisting of 16 bits. These real part and imaginary part data are bit-shifted into 8-bit data by the data selection processing circuit 20 in the next stage, and the arithmetic circuit 22 calculates the square root of the sum of squares of both data to calculate the power spectrum. It Then, the obtained power spectrum data is sent to the display circuit 24, and an image is displayed in which the horizontal axis represents time, the vertical axis represents the Doppler frequency, and the brightness corresponds to the power of each frequency component.

FIG. 2 is a block diagram of a data selection processing circuit which is a feature of the present invention.

In the figure, reference numeral 20 is the above-mentioned data selection processing circuit, which is a Fourier transform circuit 18 and a power spectrum calculation circuit.
It is provided between 22 and. 26 and 28 are Fourier transform circuits
First and second bit shift circuits for selecting 8 bits by shifting the real part and imaginary part data consisting of 16 bits output from 18 by the predetermined number of bits Nf from the most significant bit (MSB), The number of bits to shift Nf is appropriately set by the user.

30 is the number of bits Nf shifted by the first and second bit shift circuits 26 and 28, and the margin bit Na until the overflow of both data given from the Fourier transform circuit 18, based on the overflow due to the bit shift. It is a determination circuit for determining the presence or absence. The discrimination circuit 30 includes first and second margin bit detection circuits 32 and 34 for detecting the margin bit Na until the 16-bit data input from the Fourier transform circuit 18 overflows, and the first and second margin bit detection circuits 32 and 34, respectively. 2 The margin bits Na detected by the margin bit detection circuits 32 and 34 are compared with the number of bits Nf to be shifted, and when the number of bits Nf to be shifted is larger than the margin bit Na (Nf ≧ Na), “H” It is composed of first and second comparators 36 and 38 which respectively output level overflow determination signals. The first and second margin bit detection circuits 32 and 34 previously store the value of the margin bit Na until the 16-bit data overflows.
It is composed of EPROM, and the real part and imaginary part data is input as the read address for each EPROM.

Reference numeral 40 is a level fixing circuit for fixing the values of the real part and imaginary part data to the maximum value in response to the "H" level overflow judgment signals output from the first and second comparators 36, 38 of the judgment circuit 30. Is. That is, the level fixing circuit 40 is
The first and second maximum setting devices 42 and 44 in which "01111111" (7F) is set as the positive maximum value of bit data, the output of the first bit shift circuit 26, and the output of the first maximum setting device 42 And a first data selection circuit 46 that selects the output of the first maximum value setting device 42 in response to an "H" level overflow determination signal from the first comparator 36, and a second bit shift circuit 28.
And the output of the second maximum value setting unit 44 are commonly input, and the second maximum value setting unit 44 output is selected in response to the "H" level overflow determination signal from the second comparator 38. And a data selection circuit 48.

Next, the operation of the data selection processing circuit 20, which is a feature of the present invention, will be described. In the circuit 20, the processing operation of the real part data and the imaginary part data output from the Fourier transform circuit 18 is almost the same, so here, the processing of the imaginary part data will be mainly described.

When the real part data composed of 16 bits is output from the Fourier transform circuit 18, this data is the first bit shift circuit.
26 and the first margin bit detection circuit 32 of the discrimination circuit 30 are commonly input. In response to this, the first margin bit detection circuit 32
Outputs data indicating the margin bit Na until 16-bit data overflows. For example, the real part data is “00001011 ...” in order from the most significant bit (MSB).
When the value is “3”, the value “3” is output. When the value is “00101011 ...”, the value “1” is output. Then, the value of this margin bit is given to the first comparator 36. The first comparator 36 compares the value Na of this margin bit with a predetermined number of bits Nf to be shifted with the most significant bit as a reference.

When the number of bits Nf to be shifted is larger than the margin bit Na (Nf ≧ Na), overflow occurs due to the bit shift. In this case, therefore, the first comparator 36 outputs an “H” level overflow determination signal. It is output and this determination signal is input to the first data selection circuit 46. The first data selection circuit 46 selects the output of the first maximum value setting unit 42 in response to the "H" level overflow determination signal. Therefore, the value of "01111111" (7F), which is the maximum positive value of 8-bit data, is selected from the first data selection circuit 46. That is, when the bit shift causes an overflow, the value of the 8-bit real part data is fixed to the maximum positive value.

When the number of bits Nf to be shifted is smaller than the margin bit Na (Nf <Na), overflow does not occur even if the bits are shifted. In this case, the discrimination signal output of the first comparator 36 is "L". Then, the first data selection circuit 46 selects the output of the first bit shift circuit 26. Therefore, the first bit shift circuit 26 shifts the 16-bit data from the most significant bit (MSB) by a predetermined number of bits Nf, and then the 8-bit selected data is output via the first data selection circuit 46. Then, the 8-bit data is sent to the power spectrum calculation circuit 22 in the next stage as the real part data.

The above description is for the case of processing the real part data, but the same is true for the processing of the imaginary part data, and when the imaginary part data overflows due to bit shifting by the second bit shift circuit 28, , Second data selection circuit
At 48, the output of the second maximum value setting unit 44 is selected. Therefore, the maximum positive value of 8-bit data is "01111111" (7
The value of F) is selected. That is, when the bit shift causes an overflow, the imaginary part data is also fixed to the maximum value.

(F) Effect As described above, according to the present invention, when overflow occurs as a result of bit shift, the data is uniformly fixed to the maximum value as a saturated state, and therefore, the reverse display of the luminance based on the overflow is caused. An excellent effect is exhibited such that the phenomenon does not occur.

[Brief description of drawings]

1 and 2 show an embodiment of the present invention, FIG. 1 is a block diagram of an ultrasonic Doppler apparatus, FIG. 2 is a block diagram of a data selection processing circuit of the apparatus shown in FIG. 1, and FIG. FIG. 4 is a block diagram of a conventional bit shift circuit and an arithmetic circuit, and FIG. 4 is an explanatory diagram showing a display example of a power spectrum. 1 ... Ultrasonic Doppler device, 18 ... Fourier transform circuit, 20
... data selection processing circuit, 22 ... power spectrum operation circuit, 26 ... first bit shift circuit, 28 ... second bit shift circuit, 30 ... discrimination circuit, 40 ... level fixed circuit.

Claims (1)

[Claims] 1. A Fourier transform circuit for Fourier transforming a Doppler signal obtained by phase-detecting an echo signal, and a power spectrum calculation for calculating a power spectrum from both real part and imaginary part data obtained by this Fourier transform circuit. Between the circuit and a bit shift circuit that shifts both the data by a predetermined number of bits, and the number of bits shifted by this bit shift circuit and a margin bit until the overflow of both data given from the Fourier transform circuit. A discriminating circuit for discriminating the presence / absence of overflow due to bit shift based on the above, and a level fixing circuit for fixing the values of both data to the maximum value in response to an overflow discriminating signal outputted from the discriminating circuit, An ultrasonic Doppler device characterized by being provided.